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    • 4. 发明授权
    • Manufacturing method of a nonvolatile semiconductor memory device
    • 非易失性半导体存储器件的制造方法
    • US07651914B2
    • 2010-01-26
    • US12176559
    • 2008-07-21
    • Hiroshi AkahoriWakako TakeuchiYoshio Ozawa
    • Hiroshi AkahoriWakako TakeuchiYoshio Ozawa
    • H01L21/336H01L21/3205H01L21/28
    • H01L29/7881H01L27/115H01L27/11521H01L27/11524H01L29/42324H01L29/513
    • A manufacturing method of a nonvolatile semiconductor memory device including: providing a first insulating film and a silicon film on a semiconductor substrate; providing a fifth insulating film containing silicon and oxygen on the silicon film; providing a second insulating film containing silicon and nitrogen on the fifth insulating film; providing a third insulating film on the second insulating film, the third insulating film is composed of a single-layer insulating film containing oxygen or multiple-layer stacked insulating film at least whose films on a top layer and a bottom layer contain oxygen, and relative dielectric constant of the single-layer insulating film and the stacked insulating film being larger than relative dielectric constant of a silicon oxide film; providing a fourth insulating film containing silicon and nitrogen on the third insulating film; and providing a control gate above the fourth insulating film.
    • 一种非易失性半导体存储器件的制造方法,包括:在半导体衬底上提供第一绝缘膜和硅膜; 在硅膜上提供含有硅和氧的第五绝缘膜; 在第五绝缘膜上提供含有硅和氮的第二绝缘膜; 在所述第二绝缘膜上提供第三绝缘膜,所述第三绝缘膜由包含氧或多层堆叠绝缘膜的单层绝缘膜组成,所述单层绝缘膜至少其顶层和底层上的膜含有氧,并且相对 单层绝缘膜和叠层绝缘膜的介电常数大于氧化硅膜的相对介电常数; 在所述第三绝缘膜上提供含有硅和氮的第四绝缘膜; 以及在所述第四绝缘膜上方设置控制栅极。
    • 7. 发明授权
    • Nonvolatile semiconductor memory device and manufacturing method thereof
    • 非易失性半导体存储器件及其制造方法
    • US08133782B2
    • 2012-03-13
    • US13028730
    • 2011-02-16
    • Hiroshi AkahoriWakako TakeuchiAtsuhiro Sato
    • Hiroshi AkahoriWakako TakeuchiAtsuhiro Sato
    • H01L21/8247
    • H01L27/11521H01L21/28273H01L27/115H01L29/42336
    • A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.
    • 存储器件包括:半导体衬底,以行和列形成在衬底上方的存储元件,位线和字线与各个列和行中的存储元件选择性地连接,每个存储元件包括形成在衬底上的第一栅极绝缘体 ,形成在第一栅极绝缘体上的电荷累积层,形成在电荷累积层上的第二栅极绝缘体和形成在第二栅极绝缘体上的控制电极,其中比率r / d不小于0.5,其中r:a 上角部的曲率半径或电荷蓄积层的表面粗糙度,d:沿着与位线垂直的方向的截面中的第二栅极绝缘体的等效氧化物厚度。
    • 10. 发明授权
    • Nonvolatile semiconductor memory device and manufacturing method thereof
    • 非易失性半导体存储器件及其制造方法
    • US07906804B2
    • 2011-03-15
    • US11798888
    • 2007-05-17
    • Hiroshi AkahoriWakako TakeuchiAtsuhiro Sato
    • Hiroshi AkahoriWakako TakeuchiAtsuhiro Sato
    • H01L29/78
    • H01L27/11521H01L21/28273H01L27/115H01L29/42336
    • A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.
    • 存储器件包括:半导体衬底,以行和列形成在衬底上方的存储元件,位线和字线与各个列和行中的存储元件选择性地连接,每个存储元件包括形成在衬底上的第一栅极绝缘体 ,形成在第一栅极绝缘体上的电荷累积层,形成在电荷累积层上的第二栅极绝缘体和形成在第二栅极绝缘体上的控制电极,其中比率r / d不小于0.5,其中r:a 上角部的曲率半径或电荷蓄积层的表面粗糙度,d:沿着与位线垂直的方向的截面中的第二栅极绝缘体的等效氧化物厚度。