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1. 发明申请

US20120311245A1 SEMICONDUCTOR STORAGE DEVICE WITH VOLATILE AND NONVOLATILE MEMORIES 有权
标题翻译：具有易失性和非易失性存储器的半导体存储器件
公开(公告)号：US20120311245A1
公开(公告)日：2012-12-06
申请号：US13571034
申请日：2012-08-09
申请人： Hirokuni YANO , Shinichi Kanno , Toshikatsu Hida , Hidenori Matsuzaki , Kazuya Kitsunai , Shigehiro Asano
发明人： Hirokuni YANO , Shinichi Kanno , Toshikatsu Hida , Hidenori Matsuzaki , Kazuya Kitsunai , Shigehiro Asano
IPC分类号： G06F12/02
CPC分类号： G06F3/0604 , G06F3/0616 , G06F3/0631 , G06F3/064 , G06F3/0656 , G06F3/0658 , G06F3/0679 , G06F3/0685 , G06F12/0246 , G06F12/0804 , G06F12/0866 , G06F2212/7201 , G06F2212/7202 , G06F2212/7203 , G06F2212/7209 , G11C11/5628
摘要： A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
摘要翻译：半导体存储装置包括配置在易失性半导体存储器中的第一存储区域，配置在非易失性半导体存储器中的第二和第三存储区域，以及执行以下处理的控制器。控制器执行第一处理，用于通过第一存储区中的第一单元存储多个数据;第二处理，用于存储由第二存储区中的第一管理单元从第一存储区输出的数据;以及第三处理，通过第二管理单元将从第一存储区域输出的数据存储在第三存储区域中。

2. 发明申请

US20120239992A1 METHOD OF CONTROLLING A SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：控制半导体存储器件的方法
公开(公告)号：US20120239992A1
公开(公告)日：2012-09-20
申请号：US13486718
申请日：2012-06-01
申请人： Toshikatsu HIDA , Shinichi KANNO , Hirokuni YANO , Kazuya KITSUNAI , Shigehiro ASANO , Junji YANO
发明人： Toshikatsu HIDA , Shinichi KANNO , Hirokuni YANO , Kazuya KITSUNAI , Shigehiro ASANO , Junji YANO
IPC分类号： G11C29/00 , G06F11/16
CPC分类号： G06F11/1412 , G06F11/1068 , G06F11/1402 , G06F12/02 , G11C16/0483 , G11C16/3418 , G11C16/3431
摘要： A method of controlling a nonvolatile semiconductor memory including a plurality of blocks, each one of the plurality of blocks being a unit of data erasing, includes determining a monitored block as a candidate for refresh operation from among the plurality of blocks based on a predetermined condition. The method includes monitoring an error count of data stored in the monitored block and not monitoring an error count of data stored in blocks excluding the monitored block among the plurality of blocks. The method also includes performing the refresh operation on data stored in the monitored block in which the error count is larger than a first threshold value.
摘要翻译：一种控制包括多个块的非易失性半导体存储器的方法，所述多个块中的每一个是数据擦除单元，包括：基于预定条件，将所监视的块作为所述多个块中的刷新操作的候补确定。该方法包括监视存储在所监视的块中的数据的错误计数，并且不监视存储在多个块中的被监视块之外的块中存储的数据的错误计数。该方法还包括对存储在监视块中的数据执行刷新操作，其中错误计数大于第一阈值。

3. 发明申请

US20120033496A1 SEMICONDUCTOR STORAGE DEVICE WITH VOLATILE AND NONVOLATILE MEMORIES 审中-公开
公开(公告)号：US20120033496A1
公开(公告)日：2012-02-09
申请号：US13271838
申请日：2011-10-12
申请人： Hirokuni YANO , Shinichi KANNO , Toshikatsu HIDA , Hidenori MATSUZAKI , Kazuya KITSUNAI , Shigehiro ASANO
发明人： Hirokuni YANO , Shinichi KANNO , Toshikatsu HIDA , Hidenori MATSUZAKI , Kazuya KITSUNAI , Shigehiro ASANO
IPC分类号： G11C14/00
CPC分类号： G06F3/0604 , G06F3/0616 , G06F3/0631 , G06F3/064 , G06F3/0656 , G06F3/0658 , G06F3/0679 , G06F3/0685 , G06F12/0246 , G06F12/0804 , G06F12/0866 , G06F2212/7201 , G06F2212/7202 , G06F2212/7203 , G06F2212/7209 , G11C11/5628
摘要： A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

4. 发明申请

US20100169553A1 MEMORY SYSTEM, CONTROLLER, AND METHOD OF CONTROLLING MEMORY SYSTEM 有权
标题翻译：存储器系统，控制器和控制存储器系统的方法
公开(公告)号：US20100169553A1
公开(公告)日：2010-07-01
申请号：US12566236
申请日：2009-09-24
申请人： Hirokuni YANO , Shinichi Kanno
发明人： Hirokuni YANO , Shinichi Kanno
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F12/0866 , G06F2212/7202
摘要： A memory system according to an embodiment of the present invention includes a volatile first storing unit, a nonvolatile second storing unit, a controller that transfers data between a host apparatus and the second storing unit via the first storing unit. The memory system monitors whether data written from the host apparatus in the first storing unit has a specific pattern in management units. When data to be flushed to the second storing unit has the specific pattern, the memory system set an invalid address value that is not in use in the second storing unit to the data.
摘要翻译：根据本发明的实施例的存储器系统包括易失性第一存储单元，非易失性第二存储单元，经由第一存储单元在主机设备和第二存储单元之间传送数据的控制器。存储系统监视从第一存储单元中的主机设备写入的数据是否具有管理单元中的特定模式。当要刷新到第二存储单元的数据具有特定模式时，存储器系统将不在第二存储单元中使用的无效地址值设置为数据。

5. 发明申请

US20120221776A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20120221776A1
公开(公告)日：2012-08-30
申请号：US13462905
申请日：2012-05-03
申请人： Eiji YOSHIHASHI , Hirokuni YANO , Shinji YONEZAWA
发明人： Eiji YOSHIHASHI , Hirokuni YANO , Shinji YONEZAWA
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0804 , G06F12/0246 , G06F12/0866 , G06F2212/214 , G06F2212/7201 , G06F2212/7205
摘要： According to the embodiments, a first storage area and a second storage area specified by a trim request is managed by a first management unit, and the second storage area specified by the trim request is managed by a second management unit. A block in which data of the first management unit are all specified by the trim request from the first or second storage areas and a block in which data of the second management unit are all specified by the trim request from the second storage area are released.
摘要翻译：根据实施例，由修剪请求指定的第一存储区域和第二存储区域由第一管理单元管理，并且由修剪请求指定的第二存储区域由第二管理单元管理。其中第一管理单元的数据全部由来自第一或第二存储区域的修剪请求指定的块和第二管理单元的数据全部由来自第二存储区域的修剪请求指定的块被释放。

6. 发明申请

US20100169549A1 MEMORY SYSTEM AND CONTROLLER 有权
标题翻译：存储系统和控制器
公开(公告)号：US20100169549A1
公开(公告)日：2010-07-01
申请号：US12542222
申请日：2009-08-17
申请人： Hirokuni YANO , Naoki Otsuka
发明人： Hirokuni YANO , Naoki Otsuka
IPC分类号： G06F12/00 , G06F17/30 , G06F12/08
CPC分类号： G06F12/0862 , G06F12/0868 , G06F2212/214 , G06F2212/222 , G06F2212/6028
摘要： A controller sets, out of a data range that is specified in a read request from a host device, a predetermined size of a first data range that follows a top portion of the data range and a predetermined size of a second data range that follows the first data range, and after transfer, to the host device, of data corresponding to the first data range from a second storage unit or a third storage unit having smaller data output latency than the first storage unit in which read/write of data is performed is started, the controller searches for data corresponding to the second data range in the second storage unit or the third storage unit.
摘要翻译： A控制器在从主机设备的读取请求中指定的数据范围内设置遵循该数据范围的顶部部分的第一数据范围的预定大小和在该数据范围之后的第二数据范围的预定大小第一数据范围，并且在从具有比执行数据的读/写数据的第一存储单元的数据输出延迟更小的第二存储单元或第三存储单元传送对应于第一数据范围的数据的主机设备之后控制器在第二存储单元或第三存储单元中搜索对应于第二数据范围的数据。

7. 发明申请

US20120159050A1 MEMORY SYSTEM AND DATA TRANSFER METHOD 审中-公开
标题翻译：存储系统和数据传输方法
公开(公告)号：US20120159050A1
公开(公告)日：2012-06-21
申请号：US13328471
申请日：2011-12-16
申请人： Hirokuni YANO , Eiji Yoshihashi
发明人： Hirokuni YANO , Eiji Yoshihashi
IPC分类号： G06F12/00 , G06F12/10
CPC分类号： G06F13/1668 , G06F12/0246
摘要： According to one embodiment, a memory system comprises a nonvolatile memory including a memory cell array and a read buffer and a controller configured to receive a read request and to issue a first read command and a second read command to the memory. When issuing the first read command, the memory transfers data of the first size from the memory cell array to the read buffer and outputs the data from the read buffer to the controller. When issuing the second read command, the memory transfers first data of the first size from the memory cell array to the read buffer, outputs the first data from the read buffer to the controller, and transfers second data of the first size from the memory cell array to the read buffer. The controller selects one command from the two commands according to the read request.
摘要翻译：根据一个实施例，存储器系统包括非易失性存储器，其包括存储单元阵列和读取缓冲器以及被配置为接收读取请求并向存储器发出第一读取命令和第二读取命令的控制器。当发出第一读命令时，存储器将第一大小的数据从存储单元阵列传送到读缓冲器，并将数据从读缓冲器输出到控制器。当发出第二读命令时，存储器将第一大小的第一数据从存储单元阵列传送到读缓冲器，将第一数据从读缓冲器输出到控制器，并从存储单元传送第一大小的第二数据数组到读缓冲区。控制器根据读取请求从两个命令中选择一个命令。

8. 发明申请

US20130232296A1 MEMORY SYSTEM AND CONTROL METHOD OF MEMORY SYSTEM 有权
标题翻译：存储系统的存储系统和控制方法
公开(公告)号：US20130232296A1
公开(公告)日：2013-09-05
申请号：US13599087
申请日：2012-08-30
申请人： Shinji YONEZAWA , Takashi HIRAO , Hirokuni YANO , Mitsunori TADOKORO , Hiroki MATSUDAIRA , Akira SAWAOKA
发明人： Shinji YONEZAWA , Takashi HIRAO , Hirokuni YANO , Mitsunori TADOKORO , Hiroki MATSUDAIRA , Akira SAWAOKA
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7205 , G06F2212/7209 , G11C2211/5641
摘要： A memory system in embodiments includes a nonvolatile semiconductor memory that stores user data, a forward lookup address translation table and a reverse lookup address translation table, and a controller. The controller is configured to determine that the user data stored in the nonvolatile semiconductor memory is valid or invalid based on these two tables. The controller may perform data organizing of selecting data determined valid and rewriting the data in a new block. The controller may perform write processing and rewriting processing to the new block alternately at a predetermined ratio. The controller may determine whether a predetermined condition is satisfied on a basis of addresses included in write requests and write data in the MLC mode when the condition is satisfied and write data in the SLC mode when the condition is not satisfied.
摘要翻译：实施例中的存储器系统包括存储用户数据的非易失性半导体存储器，正向查找地址转换表和反向查找地址转换表以及控制器。控制器被配置为基于这两个表来确定存储在非易失性半导体存储器中的用户数据有效或无效。控制器可以执行数据组织，选择确定有效的数据并在新的块中重写数据。控制器可以以预定的比例交替地对新的块执行写入处理和重写处理。当条件满足时，控制器可以基于写入请求中包括的地址和写入数据来确定是否满足预定条件，并且当条件不满足时将控制器写入SLC模式中的数据。

9. 发明申请

US20130227246A1 MANAGEMENT INFORMATION GENERATING METHOD, LOGICAL BLOCK CONSTRUCTING METHOD, AND SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：管理信息生成方法，逻辑块构造方法和半导体存储器件
公开(公告)号：US20130227246A1
公开(公告)日：2013-08-29
申请号：US13609991
申请日：2012-09-11
申请人： Takashi HIRAO , Hirokuni YANO , Aurelien Nam Phong TRAN , Mitsunori TADOKORO , Hiroki MATSUDAIRA , Tatsuya SUMIYOSHI , Yoshimi NIISATO , Kenji TANAKA
发明人： Takashi HIRAO , Hirokuni YANO , Aurelien Nam Phong TRAN , Mitsunori TADOKORO , Hiroki MATSUDAIRA , Tatsuya SUMIYOSHI , Yoshimi NIISATO , Kenji TANAKA
IPC分类号： G06F12/10
CPC分类号： G06F12/0246 , G06F12/1009 , G06F2212/1032 , G06F2212/7201 , G11C16/349
摘要： A management information generating method wherein logical and physical block addresses (BAs) of continuous addresses are associated with each other in the BA translation table. When a logical block is constructed, an allowable value is set for the number of defective physical blocks. A logical block having fewer defects than the set number is set usable, and a logical block having more defects than the set number is set unusable. System logical block construction is performed to preferentially select physical blocks from a plane list including a large number of usable blocks to equalize the number of usable blocks in each plane list. It is determined whether the number of free blocks is insufficient on the basis of a first management unit and whether the storage area for the indicated capacity can be reserved on the basis of the management unit different from the first unit.
摘要翻译：一种管理信息生成方法，其中连续地址的逻辑和物理块地址（BA）在BA转换表中彼此相关联。当构建逻辑块时，为有缺陷的物理块的数量设置允许值。具有比设定号码少的缺陷的逻辑块被设置为可用，并且具有比设定号码多的缺陷的逻辑块被设置为不可用。执行系统逻辑块构造以从包括大量可用块的平面列表中优先选择物理块以均衡每个平面列表中的可用块的数量。基于第一管理单元确定空闲块的数量是否不足，以及是否可以基于与第一单元不同的管理单元来保留指示容量的存储区域。

10. 发明申请

US20120159244A1 MEMORY SYSTEM 失效
标题翻译：记忆系统
公开(公告)号：US20120159244A1
公开(公告)日：2012-06-21
申请号：US13326872
申请日：2011-12-15
申请人： Takashi HIRAO , Mitsunori TADOKORO , Hirokuni YANO
发明人： Takashi HIRAO , Mitsunori TADOKORO , Hirokuni YANO
IPC分类号： G06F12/16 , G06F11/14
CPC分类号： G06F11/1441
摘要： According to one embodiment, a memory system includes a data manager and a data restorer. The data manager multiplexes difference logs by a parallel writing operation and stores them in a second storage area, the difference logs being difference logs indicating difference information before and after update of a management table; and thereafter multiplexes predetermined data as finalizing logs and stores them in the second storage area. The data restorer determines a system status at startup of the memory system, by judging whether irregular power-off occurs or data destruction occurs in the second storage area, based on a data storage state of the difference logs and the finalizing logs stored in the second storage area.
摘要翻译：根据一个实施例，存储器系统包括数据管理器和数据恢复器。数据管理器通过并行写入操作来复用差异日志，并将它们存储在第二存储区域中，差异日志是指示更新管理表之前和之后的差异信息的差异日志; 然后将预定数据多路复用为完成日志并将它们存储在第二存储区域中。数据恢复器通过基于存储在第二存储区域中的不同日志的数据存储状态和存储的完成日志来判断在启动存储器系统时的系统状态，通过判断是否发生不规则的电源关闭或在第二存储区域中发生数据破坏储藏区域。

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