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1. 发明申请

US20120033496A1 SEMICONDUCTOR STORAGE DEVICE WITH VOLATILE AND NONVOLATILE MEMORIES 审中-公开
公开(公告)号：US20120033496A1
公开(公告)日：2012-02-09
申请号：US13271838
申请日：2011-10-12
申请人： Hirokuni YANO , Shinichi KANNO , Toshikatsu HIDA , Hidenori MATSUZAKI , Kazuya KITSUNAI , Shigehiro ASANO
发明人： Hirokuni YANO , Shinichi KANNO , Toshikatsu HIDA , Hidenori MATSUZAKI , Kazuya KITSUNAI , Shigehiro ASANO
IPC分类号： G11C14/00
CPC分类号： G06F3/0604 , G06F3/0616 , G06F3/0631 , G06F3/064 , G06F3/0656 , G06F3/0658 , G06F3/0679 , G06F3/0685 , G06F12/0246 , G06F12/0804 , G06F12/0866 , G06F2212/7201 , G06F2212/7202 , G06F2212/7203 , G06F2212/7209 , G11C11/5628
摘要： A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

2. 发明申请

US20100161885A1 SEMICONDUCTOR STORAGE DEVICE AND STORAGE CONTROLLING METHOD 审中-公开
标题翻译：半导体存储设备和存储控制方法
公开(公告)号：US20100161885A1
公开(公告)日：2010-06-24
申请号：US12555274
申请日：2009-09-08
申请人： Shinichi KANNO , Shigehiro Asano , Kazuya Kitsunai , Hirokuni Yano , Toshikatsu Hida
发明人： Shinichi KANNO , Shigehiro Asano , Kazuya Kitsunai , Hirokuni Yano , Toshikatsu Hida
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/105 , G11C2216/14
摘要： A semiconductor storage device includes a first storage unit having a plurality of first blocks as data write regions; an instructing unit that issues a write instruction of writing data into the first blocks; a converting unit that converts an external address of input data to a memory position in the first block with reference to a conversion table in which external addresses of the data are associated with the memory positions of the data in the first blocks; and a judging unit that judges whether any of the first blocks store valid data associated with the external address based on the memory positions of the input data, wherein the instructing unit issues the write instruction of writing the data into the first block in which the valid data is not stored, when any of the first blocks does not store the valid data.
摘要翻译：半导体存储装置包括具有作为数据写入区域的多个第一块的第一存储单元; 指示单元，其发出将数据写入到所述第一块中的写入指令; 转换单元，参照其中数据的外部地址与第一块中的数据的存储位置相关联的转换表，将输入数据的外部地址转换为第一块中的存储器位置; 以及判断单元，其基于所述输入数据的存储器位置判断所述第一块是否存储与所述外部地址相关联的有效数据，其中，所述指示单元发出将所述数据写入到所述第一块中的写入指令，当任何第一个块不存储有效数据时，不存储数据。

3. 发明申请

US20120239992A1 METHOD OF CONTROLLING A SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：控制半导体存储器件的方法
公开(公告)号：US20120239992A1
公开(公告)日：2012-09-20
申请号：US13486718
申请日：2012-06-01
申请人： Toshikatsu HIDA , Shinichi KANNO , Hirokuni YANO , Kazuya KITSUNAI , Shigehiro ASANO , Junji YANO
发明人： Toshikatsu HIDA , Shinichi KANNO , Hirokuni YANO , Kazuya KITSUNAI , Shigehiro ASANO , Junji YANO
IPC分类号： G11C29/00 , G06F11/16
CPC分类号： G06F11/1412 , G06F11/1068 , G06F11/1402 , G06F12/02 , G11C16/0483 , G11C16/3418 , G11C16/3431
摘要： A method of controlling a nonvolatile semiconductor memory including a plurality of blocks, each one of the plurality of blocks being a unit of data erasing, includes determining a monitored block as a candidate for refresh operation from among the plurality of blocks based on a predetermined condition. The method includes monitoring an error count of data stored in the monitored block and not monitoring an error count of data stored in blocks excluding the monitored block among the plurality of blocks. The method also includes performing the refresh operation on data stored in the monitored block in which the error count is larger than a first threshold value.
摘要翻译：一种控制包括多个块的非易失性半导体存储器的方法，所述多个块中的每一个是数据擦除单元，包括：基于预定条件，将所监视的块作为所述多个块中的刷新操作的候补确定。该方法包括监视存储在所监视的块中的数据的错误计数，并且不监视存储在多个块中的被监视块之外的块中存储的数据的错误计数。该方法还包括对存储在监视块中的数据执行刷新操作，其中错误计数大于第一阈值。

4. 发明申请

US20130080863A1 STORAGE DEVICE 失效
标题翻译：储存设备
公开(公告)号：US20130080863A1
公开(公告)日：2013-03-28
申请号：US13601707
申请日：2012-08-31
申请人： Toshikatsu HIDA , Shinichi KANNO , Osamu TORII , Koji HORISAKI , Dong ZHANG
发明人： Toshikatsu HIDA , Shinichi KANNO , Osamu TORII , Koji HORISAKI , Dong ZHANG
IPC分类号： H03M13/05
CPC分类号： G06F11/10 , H03M13/1515 , H03M13/152 , H03M13/1525 , H03M13/1545 , H03M13/159 , H03M13/3715 , H03M13/3746
摘要： According to one embodiment, a storage device performs error correction processing of a code of which the maximum correction performance is T bits, the decoding device including an error correction processor for performing error correction processing using calculating devices capable of handling errors of J bits (J is an integer equal to or more than one and less than T), wherein an initial value of an error number expectation value is set to I (I is an integer equal to or more than one and less than T), and execution of increment of the error number expectation value and execution of the error correction processing is repeated until no error is detected or the error number expectation value becomes T bits.
摘要翻译：根据一个实施例，存储装置执行最大校正性能为T比特的代码的纠错处理，所述解码装置包括纠错处理器，用于使用能够处理J比特错误的计算装置（J 是等于或大于1且小于T的整数），其中错误数量期望值的初始值被设置为I（I是等于或大于1且小于T的整数），并且执行增量的误差数量期望值和纠错处理的执行被重复，直到没有检测到错误或者错误数量期望值变为T位为止。

5. 发明申请

US20080048718A1 PROGRAMMABLE GATE ARRAY APPARATUS AND METHOD FOR SWITCHING CIRCUITS 失效
标题翻译：可编程门阵列装置和切换电路的方法
公开(公告)号：US20080048718A1
公开(公告)日：2008-02-28
申请号：US11874981
申请日：2007-10-19
申请人： Shinichi KANNO , Toshikatsu Hida
发明人： Shinichi KANNO , Toshikatsu Hida
IPC分类号： G06F7/38
CPC分类号： H03K19/17776
摘要： A programmable gate array apparatus includes macrocells connected in series, each macrocell including first group of storage elements in which active context data item is stored and second group of storage elements corresponding to storage elements of first group respectively, in which idle context data item is stored, connects storage elements of second group in series, loads context data item into second group whose storage elements are connected in series, connects first group and second group by connecting storage elements of first group to corresponding storage elements of second group respectively, and swaps context data items between first group and second group.
摘要翻译：可编程门阵列装置包括串联连接的宏小区，每个宏小区包括其中存储有活动上下文数据项的第一组存储单元和对应于第一组存储单元的第二组存储单元，其中存储空闲上下文数据项将第二组的存储元件串联连接，将上下文数据项加载到其存储元件串联连接的第二组中，通过将第一组的存储元件分别连接到第二组的相应存储元件，并将交换上下文第一组与第二组之间的数据项。

6. 发明申请

US20120072795A1 SEMICONDUCTOR MEMORY DEVICE AND CONTROLLING METHOD 有权
标题翻译：半导体存储器件和控制方法
公开(公告)号：US20120072795A1
公开(公告)日：2012-03-22
申请号：US13038804
申请日：2011-03-02
申请人： Kazumasa YAMAMOTO , Shinichi KANNO , Shigehiro ASANO , Hiroyuki NAGASHIMA
发明人： Kazumasa YAMAMOTO , Shinichi KANNO , Shigehiro ASANO , Hiroyuki NAGASHIMA
IPC分类号： G06F11/267
CPC分类号： G11C16/3418 , G11C16/00 , G11C29/028
摘要： According to one embodiment, a semiconductor memory device includes a plurality of semiconductor memory chips configured to store therein information depending on an amount of accumulated charge; a plurality of parameter storage units that are provided in correspondence with the semiconductor memory chips, each of the plurality of parameter storage units being configured to store therein a parameter that defines an electrical characteristic of a signal used for writing information into or reading information from a corresponding one of the semiconductor memory chips; an error correction encoding unit configured to generate a first correction code capable of correcting an error in the information stored in a number of semiconductor memory chips no greater than a predetermined number out of the semiconductor memory chips, from the information stored in the semiconductor memory chips; and a parameter processing unit configured to change the parameters respectively corresponding to the number of semiconductor memory chips no greater than the predetermined number, and writes the parameters changed into the parameter storage units, respectively.
摘要翻译：根据一个实施例，半导体存储器件包括多个半导体存储器芯片，其被配置为根据累积电荷的量来存储信息; 多个参数存储单元，与所述半导体存储器芯片对应地设置，所述多个参数存储单元中的每一个被配置为在其中存储定义用于将信息写入信息或从其读取信息的信号的电特性的参数对应的一个半导体存储器芯片; 错误校正编码单元，被配置为从存储在半导体存储器芯片中的信息生成能够校正存储在半导体存储器芯片中的不大于预定数量的多个半导体存储器芯片中的信息中的误差的第一校正代码 ; 以及参数处理单元，被配置为分别对应于不大于预定数量的半导体存储器芯片的数量分别改变参数，并将改变的参数分别写入参数存储单元。

7. 发明申请

US20110060863A1 CONTROLLER 有权
标题翻译：控制器
公开(公告)号：US20110060863A1
公开(公告)日：2011-03-10
申请号：US12716547
申请日：2010-03-03
申请人： Tetsuro KIMURA , Shinichi KANNO , Shigehiro ASANO , Kazuhiro FUKUTOMI
发明人： Tetsuro KIMURA , Shinichi KANNO , Shigehiro ASANO , Kazuhiro FUKUTOMI
IPC分类号： G06F12/00 , G06F12/02 , G06F12/10
CPC分类号： G06F12/0246 , G06F3/0611 , G06F3/064 , G06F3/0679 , G06F2212/7201 , G06F2212/7205
摘要： A controller stores therein a sector address set indicating logical storage positions within a nonvolatile-memory storage area; page addresses indicating, in units of pages, physical storage positions within the nonvolatile-memory storage area; and pieces of management information each indicating whether one or more special sectors each being either a bad sector or a trimmed sector trimmed by a TRIM command are present in the corresponding page, while associating them with each other. When an access to a specified sector address is requested, the device refers to the piece of management information and judges whether any special sector is present in the page identified by the page address corresponding to the sector address. The device generates predetermined response data if the page contains one or more special sectors and accesses the nonvolatile-memory storage position corresponding to the sector address if the page contains no special sector.
摘要翻译：控制器在其中存储指示非易失性存储器存储区域内的逻辑存储位置的扇区地址集合; 页面地址，以页为单位指示非易失性存储器存储区域内的物理存储位置; 以及各管理信息，每个管理信息指示在相应的页面中是否存在各自为坏扇区的一个或多个特殊扇区或由TRIM命令修剪的修剪扇区，同时将它们相互关联。当请求对指定的扇区地址的访问时，设备参考管理信息，并判断由扇区地址对应的页地址所标识的页面中是否存在特殊扇区。如果页面包含一个或多个特殊扇区，则该设备产生预定的响应数据，并且如果页面不包含特殊扇区，则访问对应于扇区地址的非易失性存储器存储位置。

8. 发明申请

US20100005228A1 DATA CONTROL APPARATUS, STORAGE SYSTEM, AND COMPUTER PROGRAM PRODUCT 有权
标题翻译：数据控制设备，存储系统和计算机程序产品
公开(公告)号：US20100005228A1
公开(公告)日：2010-01-07
申请号：US12393654
申请日：2009-02-26
申请人： Kazuhiro FUKUTOMI , Hideaki SATO , Shinichi KANNO , Shigehiro ASANO
发明人： Kazuhiro FUKUTOMI , Hideaki SATO , Shinichi KANNO , Shigehiro ASANO
IPC分类号： G06F12/00 , G06F13/00 , G06F12/02 , G06F11/07
CPC分类号： G06F12/0246 , G06F11/108 , G06F2212/7208 , G06F2212/7211
摘要： A data control apparatus includes a mapping-table managing unit that manages a mapping table that is associated with a corrupted-data recovery function of recording data and error correcting code data as redundant data that is given separately from the data, distributed and stored in units of stripe blocks in the plural nonvolatile semiconductor memory devices, the mapping table containing arrangement information of the data and the error correcting code data; a determining unit that determines whether to differentiate frequencies of writing the data into the semiconductor memory devices; and a changing unit that changes the arrangement information by switching the data stored in units of the stripe blocks managed using the mapping table to differentiate the frequencies of writing the data into the semiconductor memory devices, when the determining unit determines that the frequencies of writing the data into the semiconductor memory devices are to be differentiated.
摘要翻译：数据控制装置包括映射表管理单元，其管理与记录数据的损坏数据恢复功能和纠错码数据相关联的映射表，作为与数据分开地分配并以单元分布和存储的冗余数据所述多个非易失性半导体存储器件中的条形块，所述映射表包含所述数据的排列信息和所述纠错码数据; 确定单元，其确定是否将写入数据的频率区分成半导体存储器件; 以及改变单元，其通过切换存储在使用映射表管理的条带块的单元中的数据来改变排列信息，以将写入数据的频率区分为半导体存储器件，当确定单元确定写入的频率差分数据到半导体存储器件中。

9. 发明申请

US20120221918A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20120221918A1
公开(公告)日：2012-08-30
申请号：US13465624
申请日：2012-05-07
申请人： Shinichi KANNO , Hironori UCHIKAWA
发明人： Shinichi KANNO , Hironori UCHIKAWA
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： H03M13/2906 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1068 , G06F13/1673 , G06F13/4068 , G11C29/52 , H03M13/03 , H03M13/29 , H03M13/35 , H03M13/6561 , Y02D10/14 , Y02D10/151
摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
摘要翻译：半导体存储器件包括多个检测码发生器，其被配置为分别产生多个检测码以分别检测多个数据项中的错误;多个第一校正码发生器，被配置为产生多个第一校正码以校正错误在多个第一数据块中，分别包含数据项之一和相应检测码的第一数据块，被配置为生成用于校正第二数据块中的错误的第二校正码的第二校正码发生器，包含第一数据块的第二数据块，以及被配置为非易失性地存储第二数据块，第一校正码和第二校正码的半导体存储器。

10. 发明申请

US20110239083A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110239083A1
公开(公告)日：2011-09-29
申请号：US12889018
申请日：2010-09-23
申请人： Shinichi KANNO
发明人： Shinichi KANNO
IPC分类号： H03M13/00 , G06F11/08
CPC分类号： G06F11/1068 , G06F11/1012 , G06F11/1072 , G06F11/1076 , G11C16/10 , G11C29/52 , G11C2029/0411 , H03M13/1515 , H03M13/29 , H03M13/2906
摘要： A CRC code is generated from an original data, a BCH code is generated with respect to the original data and the CRC code, and the original data, the CRC code, and the BCH code are recorded in pages selected from different planes of a plurality of memory chips. An RS code is generated from the original data across pages, a CRC code is generated with respect to the RS code, a BCH code is generated with respect to the RS code and the CRC code, and the RS code, the CRC code, the BCH code are recorded in a memory chip different from a memory chip including the original data. When reading data, error correction is performed on the original data by using the BCH code, and then CRC is calculated. If the number of errors is the number of errors that is correctable by erasure correction using the RS code, the original data is corrected by the erasure correction. If the number of errors exceeds an erasure correction capability of the RS code, normal error correction using the RS code is performed, and further error correction using the BCH code is performed.
摘要翻译：从原始数据生成CRC码，生成相对于原始数据和CRC码的BCH码，原始数据，CRC码和BCH码被记录在从多个不同平面中选择的页面中的内存芯片通过跨页面的原始数据生成RS码，相对于RS码生成CRC码，生成相对于RS码和CRC码的BCH码，RS码，CRC码， BCH码被记录在与包括原始数据的存储芯片不同的存储芯片中。当读取数据时，通过使用BCH码对原始数据进行纠错，然后计算CRC。如果错误的数量是通过使用RS代码的擦除校正可校正的错误的数量，则通过擦除校正来校正原始数据。如果错误数量超过了RS码的擦除校正能力，则使用RS码进行正常纠错，并进一步利用BCH码进行纠错。

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