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1. 发明申请

US20090011242A1 Carbon Commutator and Process for Producing the Same 有权
标题翻译：碳交换器及其生产工艺
公开(公告)号：US20090011242A1
公开(公告)日：2009-01-08
申请号：US12224311
申请日：2007-03-02
申请人： Hiroaki Tanaka , Hiroyuki Takayanagi , Seiji Otake , Mitsunari Ishizaki
发明人： Hiroaki Tanaka , Hiroyuki Takayanagi , Seiji Otake , Mitsunari Ishizaki
IPC分类号： B32B15/04 , B22F7/04
CPC分类号： C04B37/026 , C04B2237/123 , C04B2237/363 , C04B2237/407 , H01R39/045 , H01R39/06 , H01R43/06 , Y10T428/30
摘要： A commutator utilizing a carbon composite base material, the carbon composite base material including a carbon base material; and an iron layer. The iron layer, to which a metal material can be joined, is formed on a surface of the carbon base material, iron powders, which are used to form the iron layer, are subjected to a treatment so as to increase surface-adsorbed oxygen before placing the iron powders to the surface of the carbon base material that is formed in advance by sintering, and sintering is applied to the iron powders placed on the surface of the carbon base material at a temperature not less than a diffusion temperature of carbon and not more than a melting point of iron in order to form the iron layer on the surface of the carbon base material.
摘要翻译：一种利用碳复合基材的换向器，所述碳复合基材包括碳基材料; 和铁层。在碳基材的表面上形成可以接合金属材料的铁层，对用于形成铁层的铁粉进行处理，以增加表面吸附的氧气将铁粉放置在预先通过烧结而形成的碳基材料的表面上，并且在不低于碳的扩散温度的温度下对放置在碳基材的表面上的铁粉施加烧结多于铁的熔点以在碳基材料的表面上形成铁层。

2. 发明授权

US07799430B2 Carbon commutator and process for producing the same 有权
标题翻译：碳换向器及其制造方法
公开(公告)号：US07799430B2
公开(公告)日：2010-09-21
申请号：US12224311
申请日：2007-03-02
申请人： Hiroaki Tanaka , Hiroyuki Takayanagi , Seiji Otake , Mitsunari Ishizaki
发明人： Hiroaki Tanaka , Hiroyuki Takayanagi , Seiji Otake , Mitsunari Ishizaki
IPC分类号： B32B9/00 , H01R43/06
CPC分类号： C04B37/026 , C04B2237/123 , C04B2237/363 , C04B2237/407 , H01R39/045 , H01R39/06 , H01R43/06 , Y10T428/30
摘要： A commutator utilizing a carbon composite base material, the carbon composite base material including a carbon base material; and an iron layer. The iron layer, to which a metal material can be joined, is formed on a surface of the carbon base material, iron powders, which are used to form the iron layer, are subjected to a treatment so as to increase surface-adsorbed oxygen before placing the iron powders to the surface of the carbon base material that is formed in advance by sintering, and sintering is applied to the iron powders placed on the surface of the carbon base material at a temperature not less than a diffusion temperature of carbon and not more than a melting point of iron in order to form the iron layer on the surface of the carbon base material.
摘要翻译：一种利用碳复合基材的换向器，所述碳复合基材包括碳基材料; 和铁层。在碳基材的表面上形成可以接合金属材料的铁层，对用于形成铁层的铁粉进行处理，以增加表面吸附的氧气将铁粉放置在预先通过烧结而形成的碳基材料的表面上，并且在不低于碳的扩散温度的温度下对放置在碳基材的表面上的铁粉施加烧结多于铁的熔点以在碳基材料的表面上形成铁层。

3. 发明授权

US08022475B2 Semiconductor device optimized to increase withstand voltage and reduce on resistance 有权
标题翻译：半导体器件经过优化，可提高耐压并降低导通电阻
公开(公告)号：US08022475B2
公开(公告)日：2011-09-20
申请号：US12434128
申请日：2009-05-01
申请人： Yasuhiro Takeda , Seiji Otake , Kazunori Fujita
发明人： Yasuhiro Takeda , Seiji Otake , Kazunori Fujita
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L21/823456 , H01L21/2815 , H01L21/823412 , H01L21/823487 , H01L29/0653 , H01L29/0878 , H01L29/41766 , H01L29/4236 , H01L29/42376 , H01L29/66734 , H01L29/7809 , H01L29/7813
摘要： An ON resistance of a trench gate type transistor and a withstand voltage of a planar type transistor are optimized at the same time. Each of first and second regions of a semiconductor layer is formed by epitaxial growth on each of first and second regions of a semiconductor substrate, respectively. A first buried layer is formed between the first region of the semiconductor substrate and the first region of the semiconductor layer, while a second buried layer is formed between the second region of the semiconductor substrate and the second region of the semiconductor layer. The first buried layer is formed of an N+ type first impurity-doped layer and an N type second impurity-doped layer that extends beyond the fist impurity-doped layer. The second buried layer is formed of an N+ type impurity-doped layer only. In the first region of the semiconductor layer, an impurity is diffused from a surface of the semiconductor layer deep into the semiconductor layer to form an N type third impurity-doped layer. The trench gate type transistor is formed in the first region of the semiconductor layer and the planar type transistor is formed in the second region of the semiconductor layer.
摘要翻译：同时优化沟槽栅型晶体管的导通电阻和平面型晶体管的耐电压。半导体层的第一和第二区域中的每一个分别通过在半导体衬底的第一和第二区域中的每一个上外延生长而形成。在半导体衬底的第一区域和半导体层的第一区域之间形成第一掩埋层，而在半导体衬底的第二区域和半导体层的第二区域之间形成第二掩埋层。第一掩埋层由N +型第一杂质掺杂层和延伸超过第一杂质掺杂层的N型第二杂质掺杂层形成。第二掩埋层仅由N +型杂质掺杂层形成。在半导体层的第一区域中，杂质从半导体层的表面扩散到半导体层中以形成N型第三杂质掺杂层。沟槽栅型晶体管形成在半导体层的第一区域中，并且平面型晶体管形成在半导体层的第二区域中。

4. 发明申请

US20070272942A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070272942A1
公开(公告)日：2007-11-29
申请号：US11751162
申请日：2007-05-21
申请人： Seiji Otake
发明人： Seiji Otake
IPC分类号： H01L29/74
CPC分类号： H01L29/8611 , H01L29/7412
摘要： In a semiconductor device of the present invention, an N type epitaxial layer is divided into a plurality of element formation regions by an isolation region. In one of the element formation regions, a resistance is formed. Around the resistance, a protection element having a PN junction region is formed. The PN junction region has a junction breakdown voltage lower than that of a PN junction region of the resistance. By use of this structure, when negative ESD surge is applied to a pad for an electrode which applies a voltage to a P type diffusion layer, the PN junction region of the protection element breaks down. Accordingly, the resistance can be protected.
摘要翻译：在本发明的半导体器件中，N型外延层通过隔离区域分成多个元件形成区域。在元件形成区域之一中形成电阻。围绕电阻，形成具有PN结区域的保护元件。 PN结区域的结击穿电压低于电阻的PN结区域的结击穿电压。通过使用这种结构，当对用于向P型扩散层施加电压的电极的焊盘施加负的静电放电时，保护元件的PN结区域就会发生故障。因此，可以保护电阻。

5. 发明授权

US07291883B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07291883B2
公开(公告)日：2007-11-06
申请号：US11360286
申请日：2006-02-22
申请人： Ryo Kanda , Shuichi Kikuchi , Seiji Otake
发明人： Ryo Kanda , Shuichi Kikuchi , Seiji Otake
IPC分类号： H01L29/792
CPC分类号： H01L29/7816 , H01L29/0878 , H01L29/1083 , H01L29/1087 , H01L29/42368 , H01L29/456 , H01L29/66681
摘要： In a conventional semiconductor device, there is a problem that an N-type diffusion region provided for protecting an element from an overvoltage is narrow and a breakdown current is concentrated so that a PN junction region for protection is broken. In a semiconductor device of the present invention, an N-type buried diffusion layer is formed across a substrate and an epitaxial layer. A P-type buried diffusion layer is formed across a wider region on an upper surface of the N-type buried diffusion layer so that a PN junction region for overvoltage protection is formed. A P-type diffusion layer is formed so as to be connected to the P-type diffusion layer. A breakdown voltage of the PN junction region is lower than a breakdown voltage between a source and a drain. With this structure, the concentration of the breakdown current is prevented so that the semiconductor device can be protected from the overvoltage.
摘要翻译：在传统的半导体器件中，存在用于保护元件免于过电压的N型扩散区域窄并且击穿电流被集中以使得用于保护的PN结区域被破坏的问题。在本发明的半导体器件中，在衬底和外延层上形成N型掩埋扩散层。在N型掩埋扩散层的上表面上的较宽区域上形成P型埋入扩散层，从而形成用于过电压保护的PN结区域。 P型扩散层形成为与P型扩散层连接。 PN结区域的击穿电压低于源极和漏极之间的击穿电压。利用这种结构，防止了击穿电流的集中，从而可以防止半导体器件免受过电压。

6. 发明申请

US20070148892A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070148892A1
公开(公告)日：2007-06-28
申请号：US11614527
申请日：2006-12-21
申请人： Seiji Otake , Ryo Kanda , Shuichi Kikuchi
发明人： Seiji Otake , Ryo Kanda , Shuichi Kikuchi
IPC分类号： H01L21/331
CPC分类号： H01L29/735 , H01L29/0692 , H01L29/6625
摘要： In a semiconductor device of the present invention, an N type epitaxial layer is stacked on a P type single crystal silicon substrate. In the epitaxial layer, an N type diffusion layer as a base draw-out region, P type diffusion layers as an emitter region, and P type diffusion layers as a collector region are formed. The emitter region has a region having a larger diffusion width in a portion deeper than in a vicinity of a surface thereof. In a lateral PNP transistor, a smallest base width is formed in a deep portion of the epitaxial layer. By use of this structure, even in a case where the collector region is narrowed, a desired hfe value can be realized. Thus, the device size can be reduced.
摘要翻译：在本发明的半导体器件中，N型外延层层叠在P型单晶硅基板上。在外延层中，形成作为基极引出区域的N型扩散层，作为发射极区域的P型扩散层和作为集电极区域的P型扩散层。发射极区域具有比在其表面附近更深的部分具有较大扩散宽度的区域。在横向PNP晶体管中，在外延层的深部形成最小的基极宽度。通过使用该结构，即使在集电极区域变窄的情况下，也能够实现期望的hfe值。因此，可以减小设备尺寸。

7. 发明申请

US20070145529A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070145529A1
公开(公告)日：2007-06-28
申请号：US11614496
申请日：2006-12-21
申请人： Seiji Otake , Ryo Kanda , Shuichi Kikuchi
发明人： Seiji Otake , Ryo Kanda , Shuichi Kikuchi
IPC分类号： H01L27/082
CPC分类号： H01L29/735 , H01L29/1008 , H01L29/6625
摘要： In a semiconductor device of the present invention, an N type epitaxial layer is stacked on a P type single crystal silicon substrate. In the epitaxial layer, an N type diffusion layer as a base draw-out region, P type diffusion layers as an emitter region, and P type diffusion layers as a collector region are formed. The emitter region has a region having a larger diffusion width in a portion deeper than in a vicinity of a surface thereof. In a lateral PNP transistor, a smallest base width is formed in a deep portion of the epitaxial layer. By use of this structure, recombination of free carriers (positive holes) on the surface is prevented. Thus, a desired hfe value can be realized.
摘要翻译：在本发明的半导体器件中，N型外延层层叠在P型单晶硅基板上。在外延层中，形成作为基极引出区域的N型扩散层，作为发射极区域的P型扩散层和作为集电极区域的P型扩散层。发射极区域具有比在其表面附近更深的部分具有较大扩散宽度的区域。在横向PNP晶体管中，在外延层的深部形成最小的基极宽度。通过使用这种结构，可以防止表面上游离载体（正孔）的复合。因此，可以实现期望的hfe值。

8. 发明申请

US20070096261A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070096261A1
公开(公告)日：2007-05-03
申请号：US11512617
申请日：2006-08-29
申请人： Seiji Otake , Ryo Kanda , Shuichi Kikuchi
发明人： Seiji Otake , Ryo Kanda , Shuichi Kikuchi
IPC分类号： H01L29/861 , H01L31/107
CPC分类号： H01L29/866 , H01L29/66106
摘要： In a conventional semiconductor device, there is a problem that zener diode characteristics vary due to a crystal defect on a silicon surface, and the like. In a semiconductor device of the present invention, an N type epitaxial layer 4 is formed on a P type single crystal silicon substrate 2. In the epitaxial layer 4, P type diffusion layers 5, 6, 7 and 8 as anode regions and an N type diffusion layer 9 as a cathode region are formed. A PN junction region between the P type diffusion layer 8 and the N type diffusion layer 9 forms a zener diode 1. By use of this structure, a current path is located in a deep portion of the epitaxial layer 4. Thus, it is made possible to prevent a variation in a saturation voltage of the zener diode 1 due to a crystal defect on a surface of the epitaxial layer 4, and the like.
摘要翻译：在传统的半导体器件中，存在齐纳二极管特性由于硅表面上的晶体缺陷等而变化的问题。在本发明的半导体器件中，在P型单晶硅基板2上形成有N型外延层4.在外延层4中，作为阳极区域的P型扩散层5,6,7,8，N 形成作为阴极区域的扩散层9。 P型扩散层8和N型扩散层9之间的PN结区域形成齐纳二极管1.通过这种结构，电流路径位于外延层4的深部。因此，可能防止由于外延层4的表面上的晶体缺陷导致的齐纳二极管1的饱和电压的变化等。

9. 发明授权

US08916931B2 LDMOS semiconductor device with parasitic bipolar transistor for reduced surge current 有权
标题翻译： LDMOS半导体器件具有寄生双极晶体管，可减少浪涌电流
公开(公告)号：US08916931B2
公开(公告)日：2014-12-23
申请号：US13286832
申请日：2011-11-01
申请人： Yasuhiro Takeda , Seiji Otake
发明人： Yasuhiro Takeda , Seiji Otake
IPC分类号： H01L29/772 , H01L29/78 , H01L29/08 , H01L29/10
CPC分类号： H01L29/7816 , H01L29/0873 , H01L29/0878 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/7823 , H01L29/7835
摘要： An N type layer made of an N type epitaxial layer in which an N+ type drain layer etc are formed is surrounded by a P type drain isolation layer extending from the front surface of the N type epitaxial layer to an N+ type buried layer. A P type collector layer is formed in an N type layer made of the N type epitaxial layer surrounded by the P type drain isolation layer and a P type element isolation layer, extending from the front surface to the inside of the N type layer. A parasitic bipolar transistor that uses the first conductive type drain isolation layer as the emitter, the second conductive type N type layer as the base, and the collector layer as the collector is thus formed so as to flow a surge current into a ground line.
摘要翻译：由形成有N +型漏极层等的N型外延层构成的N型层由从N型外延层的前表面延伸到N +型掩埋层的P型漏极隔离层包围。在由P型漏极隔离层包围的N型外延层构成的N型层和从N型层的前表面延伸到内部的P型元件隔离层形成P型集电极层。因此，形成使用第一导电型漏极隔离层作为发射极，第二导电型N型层作为基极的集电极层作为集电极的寄生双极型晶体管，以将浪涌电流流入地线。

10. 发明申请

US20100193865A1 DMOS TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译： DMOS晶体管及其制造方法
公开(公告)号：US20100193865A1
公开(公告)日：2010-08-05
申请号：US12680012
申请日：2008-09-26
申请人： Yasuhiro Takeda , Seiji Otake , Shuichi Kikuchi
发明人： Yasuhiro Takeda , Seiji Otake , Shuichi Kikuchi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0696 , H01L21/26586 , H01L29/1095 , H01L29/42368 , H01L29/4238 , H01L29/66689 , H01L29/7816
摘要： The invention provides a DMOS transistor in which a leakage current is decreased and the source-drain breakdown voltage of the transistor in the off state is enhanced when a body layer is formed by oblique ion implantation. After a photoresist layer 18 is formed, using the photoresist layer 18 and a gate electrode 14 as a mask, first ion implantation is performed toward a first corner portion 14C1 on the inside of the gate electrode 14 in a first direction shown by an arrow A′. A first body layer 17A′ is formed by this first ion implantation. The first body layer 17A′ is formed so as to extend from the first corner portion 14C1 to under the gate electrode 14, and the P-type impurity concentration of the body layer 17A′ in the first corner portion 14C1 is higher than that of a conventional transistor.
摘要翻译：本发明提供了一种DMOS晶体管，其中当通过倾斜离子注入形成体层时，泄漏电流降低，并且处于断开状态的晶体管的源极 - 漏极击穿电压增强。在形成光致抗蚀剂层18之后，使用光致抗蚀剂层18和栅电极14作为掩模，在栅极电极14的内侧沿箭头A所示的第一方向进行第一离子注入 '。通过该第一离子注入形成第一体层17A'。第一主体层17A'形成为从第一角部14C1延伸到栅极14的下方，第一角部14C1中的主体层17A'的P型杂质浓度高于常规晶体管。

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