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1. 发明申请

US20060186477A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060186477A1
公开(公告)日：2006-08-24
申请号：US11360286
申请日：2006-02-22
申请人： Ryo Kanda , Shuichi Kikuchi , Seiji Otake
发明人： Ryo Kanda , Shuichi Kikuchi , Seiji Otake
IPC分类号： H01L29/76
CPC分类号： H01L29/7816 , H01L29/0878 , H01L29/1083 , H01L29/1087 , H01L29/42368 , H01L29/456 , H01L29/66681
摘要： In a conventional semiconductor device, there is a problem that an N-type diffusion region provided for protecting an element from an overvoltage is narrow and a breakdown current is concentrated so that a PN junction region for protection is broken. In a semiconductor device of the present invention, an N-type buried diffusion layer is formed across a substrate and an epitaxial layer. A P-type buried diffusion layer is formed across a wider region on an upper surface of the N-type buried diffusion layer so that a PN junction region for overvoltage protection is formed. A P-type diffusion layer is formed so as to be connected to the P-type diffusion layer. A breakdown voltage of the PN junction region is lower than a breakdown voltage between a source and a drain. With this structure, the concentration of the breakdown current is prevented so that the semiconductor device can be protected from the overvoltage.
摘要翻译：在传统的半导体器件中，存在用于保护元件免于过电压的N型扩散区域窄并且击穿电流被集中以使得用于保护的PN结区域被破坏的问题。在本发明的半导体器件中，在衬底和外延层上形成N型掩埋扩散层。在N型掩埋扩散层的上表面上的较宽区域上形成P型埋入扩散层，从而形成用于过电压保护的PN结区域。 P型扩散层形成为与P型扩散层连接。 PN结区域的击穿电压低于源极和漏极之间的击穿电压。利用这种结构，防止了击穿电流的集中，从而可以保护半导体器件免受过电压。

2. 发明授权

US07279768B2 Semiconductor device for overvoltage protection 有权
标题翻译：用于过电压保护的半导体器件
公开(公告)号：US07279768B2
公开(公告)日：2007-10-09
申请号：US11361173
申请日：2006-02-23
申请人： Ryo Kanda , Shuichi Kikuchi , Seiji Otake
发明人： Ryo Kanda , Shuichi Kikuchi , Seiji Otake
IPC分类号： H01L23/58
CPC分类号： H01L29/7835 , H01L29/1083 , H01L29/456 , H01L29/66659 , H01L29/7816
摘要： In a semiconductor device of the present invention, an N-type buried diffusion layer is formed across a substrate and an epitaxial layer. A P-type buried diffusion layer is formed across an upper surface of the N-type buried diffusion layer over a wide range to form a PN junction region for an overvoltage protection. A P-type diffusion region is formed so as to be connected to the P-type buried diffusion layer. A breakdown voltage of the PN junction region is lower than a breakdown voltage between a source and a drain. This structure makes it possible to prevent a concentration of a breakdown current and protect the semiconductor device from an overvoltage.
摘要翻译：在本发明的半导体器件中，在衬底和外延层上形成N型掩埋扩散层。在宽范围内在N型掩埋扩散层的上表面上形成P型掩埋扩散层，以形成用于过电压保护的PN结区域。 P型扩散区形成为与P型埋入扩散层连接。 PN结区域的击穿电压低于源极和漏极之间的击穿电压。这种结构使得可以防止击穿电流的集中并且保护半导体器件免于过电压。

3. 发明申请

US20070075363A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070075363A1
公开(公告)日：2007-04-05
申请号：US11526869
申请日：2006-09-26
申请人： Seiji Otake , Ryo Kanda , Shuichi Kikuchi
发明人： Seiji Otake , Ryo Kanda , Shuichi Kikuchi
IPC分类号： H01L29/76
CPC分类号： H01L21/761 , H01L21/823481 , H01L27/088 , H01L29/456 , H01L29/7816 , H01L29/7833
摘要： In a semiconductor device of the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. The substrate and the epitaxial layer are partitioned into a plurality of element formation regions by isolation regions. Each of the isolation regions is formed of a P type buried diffusion layer and a P type diffusion layer coupled thereto. The P type buried diffusion layer is joined to N type buried diffusion layers on both sides thereof to form PN junction regions. On the other hand, the P type diffusion layer is joined to N type diffusion layers on both sides thereof to form PN junction regions. This structure suppresses extension of widthwise diffusion of the P type buried diffusion layer and the P type diffusion layer, thus making it possible to reduce the device size.
摘要翻译：在本发明的半导体器件中，在P型单晶硅基板上形成N型外延层。衬底和外延层通过隔离区分隔成多个元件形成区域。每个隔离区域由P型掩埋扩散层和与其耦合的P型扩散层形成。 P型埋入扩散层在其两侧与N型埋入扩散层接合，形成PN结区域。另一方面，P型扩散层在其两侧与N型扩散层接合，形成PN结区域。这种结构抑制了P型掩埋扩散层和P型扩散层的宽度方向扩散的扩展，从而可以减小器件尺寸。

4. 发明申请

US20060186507A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060186507A1
公开(公告)日：2006-08-24
申请号：US11361173
申请日：2006-02-23
申请人： Ryo Kanda , Shuichi Kikuchi , Seiji Otake
发明人： Ryo Kanda , Shuichi Kikuchi , Seiji Otake
IPC分类号： H01L23/58
CPC分类号： H01L29/7835 , H01L29/1083 , H01L29/456 , H01L29/66659 , H01L29/7816
摘要： In a semiconductor device of the present invention, an N-type buried diffusion layer is formed across a substrate and an epitaxial layer. A P-type buried diffusion layer is formed across an upper surface of the N-type buried diffusion layer over a wide range to form a PN junction region for an overvoltage protection. A P-type diffusion region is formed so as to be connected to the P-type buried diffusion layer. A breakdown voltage of the PN junction region is lower than a breakdown voltage between a source and a drain. This structure makes it possible to prevent a concentration of a breakdown current and protect the semiconductor device from an overvoltage.
摘要翻译：在本发明的半导体器件中，在衬底和外延层上形成N型掩埋扩散层。在宽范围内在N型掩埋扩散层的上表面上形成P型掩埋扩散层，以形成用于过电压保护的PN结区域。 P型扩散区形成为与P型埋入扩散层连接。 PN结区域的击穿电压低于源极和漏极之间的击穿电压。这种结构使得可以防止击穿电流的集中并且保护半导体器件免于过电压。

5. 发明授权

US07485922B2 Isolation structure for semiconductor device including double diffusion isolation region forming PN junction with neighboring wells and isolation region beneath 有权
标题翻译：半导体器件的隔离结构包括双相扩散隔离区域，与相邻的阱和隔离区域形成PN结
公开(公告)号：US07485922B2
公开(公告)日：2009-02-03
申请号：US11526869
申请日：2006-09-26
申请人： Seiji Otake , Ryo Kanda , Shuichi Kikuchi
发明人： Seiji Otake , Ryo Kanda , Shuichi Kikuchi
IPC分类号： H01L29/06
CPC分类号： H01L21/761 , H01L21/823481 , H01L27/088 , H01L29/456 , H01L29/7816 , H01L29/7833
摘要： In a semiconductor device of the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. The substrate and the epitaxial layer are partitioned into a plurality of element formation regions by isolation regions. Each of the isolation regions is formed of a P type buried diffusion layer and a P type diffusion layer coupled thereto. The P type buried diffusion layer is joined to N type buried diffusion layers on both sides thereof to form PN junction regions. On the other hand, the P type diffusion layer is joined to N type diffusion layers on both sides thereof to form PN junction regions. This structure suppresses extension of widthwise diffusion of the P type buried diffusion layer and the P type diffusion layer, thus making it possible to reduce the device size.
摘要翻译：在本发明的半导体器件中，在P型单晶硅基板上形成N型外延层。衬底和外延层通过隔离区分隔成多个元件形成区域。每个隔离区域由P型掩埋扩散层和与其耦合的P型扩散层形成。 P型埋入扩散层在其两侧与N型埋入扩散层接合，形成PN结区域。另一方面，P型扩散层在其两侧与N型扩散层接合，形成PN结区域。这种结构抑制了P型掩埋扩散层和P型扩散层的宽度方向扩散的扩展，从而可以减小器件尺寸。

6. 发明授权

US07288816B2 Semiconductor device 有权
公开(公告)号：US07288816B2
公开(公告)日：2007-10-30
申请号：US11360287
申请日：2006-02-22
申请人： Ryo Kanda , Shuichi Kikuchi , Seiji Otake , Hirotsugu Hata
发明人： Ryo Kanda , Shuichi Kikuchi , Seiji Otake , Hirotsugu Hata
IPC分类号： H01L29/78
CPC分类号： H01L29/7322 , H01L21/761 , H01L21/8249 , H01L27/0623 , H01L29/0821 , H01L29/1008 , H01L29/1083 , H01L29/42368 , H01L29/6625 , H01L29/66272 , H01L29/66659 , H01L29/735 , H01L29/7835
摘要： According to a semiconductor device of an embodiment of the present invention, a P-type buried diffusion layer is formed across a substrate and an epitaxial layer. An N-type buried diffusion layer is formed in the P-type buried diffusion layer. An overvoltage protective PN junction region is formed below an element formation region. A breakdown voltage of the PN junction region is lower than a source-drain breakdown voltage. This structure prevents a breakdown current from concentratedly flowing into the PN junction region and protects the semiconductor device from overvoltage.

7. 发明申请

US20070063274A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070063274A1
公开(公告)日：2007-03-22
申请号：US11360287
申请日：2006-02-22
申请人： Ryo Kanda , Shuichi Kikuchi , Seiji Otake , Hirotsugu Hata
发明人： Ryo Kanda , Shuichi Kikuchi , Seiji Otake , Hirotsugu Hata
IPC分类号： H01L29/76
CPC分类号： H01L29/7322 , H01L21/761 , H01L21/8249 , H01L27/0623 , H01L29/0821 , H01L29/1008 , H01L29/1083 , H01L29/42368 , H01L29/6625 , H01L29/66272 , H01L29/66659 , H01L29/735 , H01L29/7835
摘要： According to a semiconductor device of an embodiment of the present invention, a P-type buried diffusion layer is formed across a substrate and an epitaxial layer. An N-type buried diffusion layer is formed in the P-type buried diffusion layer. An overvoltage protective PN junction region is formed below an element formation region. A breakdown voltage of the PN junction region is lower than a source-drain breakdown voltage. This structure prevents a breakdown current from concentratedly flowing into the PN junction region and protects the semiconductor device from overvoltage.
摘要翻译：根据本发明的实施例的半导体器件，在衬底和外延层之间形成P型掩埋扩散层。在P型掩埋扩散层中形成N型埋入扩散层。在元件形成区域的下方形成过电压保护PN结区域。 PN结区域的击穿电压低于源极 - 漏极击穿电压。这种结构防止击穿电流集中地流入PN结区域并保护半导体器件免受过电压。

8. 发明授权

US07291883B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07291883B2
公开(公告)日：2007-11-06
申请号：US11360286
申请日：2006-02-22
申请人： Ryo Kanda , Shuichi Kikuchi , Seiji Otake
发明人： Ryo Kanda , Shuichi Kikuchi , Seiji Otake
IPC分类号： H01L29/792
CPC分类号： H01L29/7816 , H01L29/0878 , H01L29/1083 , H01L29/1087 , H01L29/42368 , H01L29/456 , H01L29/66681
摘要： In a conventional semiconductor device, there is a problem that an N-type diffusion region provided for protecting an element from an overvoltage is narrow and a breakdown current is concentrated so that a PN junction region for protection is broken. In a semiconductor device of the present invention, an N-type buried diffusion layer is formed across a substrate and an epitaxial layer. A P-type buried diffusion layer is formed across a wider region on an upper surface of the N-type buried diffusion layer so that a PN junction region for overvoltage protection is formed. A P-type diffusion layer is formed so as to be connected to the P-type diffusion layer. A breakdown voltage of the PN junction region is lower than a breakdown voltage between a source and a drain. With this structure, the concentration of the breakdown current is prevented so that the semiconductor device can be protected from the overvoltage.
摘要翻译：在传统的半导体器件中，存在用于保护元件免于过电压的N型扩散区域窄并且击穿电流被集中以使得用于保护的PN结区域被破坏的问题。在本发明的半导体器件中，在衬底和外延层上形成N型掩埋扩散层。在N型掩埋扩散层的上表面上的较宽区域上形成P型埋入扩散层，从而形成用于过电压保护的PN结区域。 P型扩散层形成为与P型扩散层连接。 PN结区域的击穿电压低于源极和漏极之间的击穿电压。利用这种结构，防止了击穿电流的集中，从而可以防止半导体器件免受过电压。

9. 发明申请

US20070148892A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070148892A1
公开(公告)日：2007-06-28
申请号：US11614527
申请日：2006-12-21
申请人： Seiji Otake , Ryo Kanda , Shuichi Kikuchi
发明人： Seiji Otake , Ryo Kanda , Shuichi Kikuchi
IPC分类号： H01L21/331
CPC分类号： H01L29/735 , H01L29/0692 , H01L29/6625
摘要： In a semiconductor device of the present invention, an N type epitaxial layer is stacked on a P type single crystal silicon substrate. In the epitaxial layer, an N type diffusion layer as a base draw-out region, P type diffusion layers as an emitter region, and P type diffusion layers as a collector region are formed. The emitter region has a region having a larger diffusion width in a portion deeper than in a vicinity of a surface thereof. In a lateral PNP transistor, a smallest base width is formed in a deep portion of the epitaxial layer. By use of this structure, even in a case where the collector region is narrowed, a desired hfe value can be realized. Thus, the device size can be reduced.
摘要翻译：在本发明的半导体器件中，N型外延层层叠在P型单晶硅基板上。在外延层中，形成作为基极引出区域的N型扩散层，作为发射极区域的P型扩散层和作为集电极区域的P型扩散层。发射极区域具有比在其表面附近更深的部分具有较大扩散宽度的区域。在横向PNP晶体管中，在外延层的深部形成最小的基极宽度。通过使用该结构，即使在集电极区域变窄的情况下，也能够实现期望的hfe值。因此，可以减小设备尺寸。

10. 发明申请

US20070145529A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070145529A1
公开(公告)日：2007-06-28
申请号：US11614496
申请日：2006-12-21
申请人： Seiji Otake , Ryo Kanda , Shuichi Kikuchi
发明人： Seiji Otake , Ryo Kanda , Shuichi Kikuchi
IPC分类号： H01L27/082
CPC分类号： H01L29/735 , H01L29/1008 , H01L29/6625
摘要： In a semiconductor device of the present invention, an N type epitaxial layer is stacked on a P type single crystal silicon substrate. In the epitaxial layer, an N type diffusion layer as a base draw-out region, P type diffusion layers as an emitter region, and P type diffusion layers as a collector region are formed. The emitter region has a region having a larger diffusion width in a portion deeper than in a vicinity of a surface thereof. In a lateral PNP transistor, a smallest base width is formed in a deep portion of the epitaxial layer. By use of this structure, recombination of free carriers (positive holes) on the surface is prevented. Thus, a desired hfe value can be realized.
摘要翻译：在本发明的半导体器件中，N型外延层层叠在P型单晶硅基板上。在外延层中，形成作为基极引出区域的N型扩散层，作为发射极区域的P型扩散层和作为集电极区域的P型扩散层。发射极区域具有比在其表面附近更深的部分具有较大扩散宽度的区域。在横向PNP晶体管中，在外延层的深部形成最小的基极宽度。通过使用这种结构，可以防止表面上游离载体（正孔）的复合。因此，可以实现期望的hfe值。

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