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1. 发明申请

US20100193865A1 DMOS TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译： DMOS晶体管及其制造方法
公开(公告)号：US20100193865A1
公开(公告)日：2010-08-05
申请号：US12680012
申请日：2008-09-26
申请人： Yasuhiro Takeda , Seiji Otake , Shuichi Kikuchi
发明人： Yasuhiro Takeda , Seiji Otake , Shuichi Kikuchi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0696 , H01L21/26586 , H01L29/1095 , H01L29/42368 , H01L29/4238 , H01L29/66689 , H01L29/7816
摘要： The invention provides a DMOS transistor in which a leakage current is decreased and the source-drain breakdown voltage of the transistor in the off state is enhanced when a body layer is formed by oblique ion implantation. After a photoresist layer 18 is formed, using the photoresist layer 18 and a gate electrode 14 as a mask, first ion implantation is performed toward a first corner portion 14C1 on the inside of the gate electrode 14 in a first direction shown by an arrow A′. A first body layer 17A′ is formed by this first ion implantation. The first body layer 17A′ is formed so as to extend from the first corner portion 14C1 to under the gate electrode 14, and the P-type impurity concentration of the body layer 17A′ in the first corner portion 14C1 is higher than that of a conventional transistor.
摘要翻译：本发明提供了一种DMOS晶体管，其中当通过倾斜离子注入形成体层时，泄漏电流降低，并且处于断开状态的晶体管的源极 - 漏极击穿电压增强。在形成光致抗蚀剂层18之后，使用光致抗蚀剂层18和栅电极14作为掩模，在栅极电极14的内侧沿箭头A所示的第一方向进行第一离子注入 '。通过该第一离子注入形成第一体层17A'。第一主体层17A'形成为从第一角部14C1延伸到栅极14的下方，第一角部14C1中的主体层17A'的P型杂质浓度高于常规晶体管。

2. 发明授权

US07768067B2 DMOS transistor 有权
标题翻译： DMOS晶体管
公开(公告)号：US07768067B2
公开(公告)日：2010-08-03
申请号：US12425592
申请日：2009-04-17
申请人： Seiji Otake , Shuichi Kikuchi , Yasuhiro Takeda , Kenichi Maki
发明人： Seiji Otake , Shuichi Kikuchi , Yasuhiro Takeda , Kenichi Maki
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7816 , H01L29/0878 , H01L29/41758 , H01L29/41775 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66689
摘要： This invention provides a DMOS transistor that has a reduced ON resistance and is prevented from deterioration in strength against an electrostatic discharge. An edge portion of a source layer of the DMOS transistor is disposed so as to recede from an inner corner portion of a gate electrode. A silicide layer is structured so as not to extend out of the edge portion of the source layer. That is, although the silicide layer is formed on a surface of the source layer, the silicide layer is not formed on a surface of a portion of a body layer, which is exposed between the source layer and the inner corner portion of the gate electrode. As a result, the strength against the electrostatic discharge can be improved, because an electric current flows almost uniformly through whole of the DMOS transistor without converging.
摘要翻译：本发明提供一种DMOS晶体管，其具有降低的导通电阻并且防止其相对静电放电的强度劣化。 DMOS晶体管的源极层的边缘部分被设置为从栅电极的内角部分退出。硅化物层被构造为不从源极层的边缘部分延伸出来。也就是说，尽管在源极层的表面上形成硅化物层，但是在源极层和栅电极的内角部之间露出的体层的一部分的表面上不形成硅化物层。结果，由于电流几乎均匀地流过整个DMOS晶体管而没有会聚，所以可以提高抵抗静电放电的强度。

3. 发明授权

US08395210B2 DMOS transistor and method of manufacturing the same 有权
标题翻译： DMOS晶体管及其制造方法
公开(公告)号：US08395210B2
公开(公告)日：2013-03-12
申请号：US12680012
申请日：2008-09-26
申请人： Yasuhiro Takeda , Seiji Otake , Shuichi Kikuchi
发明人： Yasuhiro Takeda , Seiji Otake , Shuichi Kikuchi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0696 , H01L21/26586 , H01L29/1095 , H01L29/42368 , H01L29/4238 , H01L29/66689 , H01L29/7816
摘要： The invention provides a DMOS transistor in which a leakage current is decreased and the source-drain breakdown voltage of the transistor in the off state is enhanced when a body layer is formed by oblique ion implantation. After a photoresist layer 18 is formed, using the photoresist layer 18 and a gate electrode 14 as a mask, first ion implantation is performed toward a first corner portion 14C1 on the inside of the gate electrode 14 in a first direction shown by an arrow A′. A first body layer 17A′ is formed by this first ion implantation. The first body layer 17A′ is formed so as to extend from the first corner portion 14C1 to under the gate electrode 14, and the P-type impurity concentration of the body layer 17A′ in the first corner portion 14C1 is higher than that of a conventional transistor.
摘要翻译：本发明提供了一种DMOS晶体管，其中当通过倾斜离子注入形成体层时，泄漏电流降低，并且处于断开状态的晶体管的源极 - 漏极击穿电压增强。在形成光致抗蚀剂层18之后，使用光致抗蚀剂层18和栅电极14作为掩模，在栅极电极14的内侧沿箭头A所示的第一方向进行第一离子注入 '。通过该第一离子注入形成第一体层17A'。第一主体层17A'形成为从第一角部14C1延伸到栅极14的下方，第一角部14C1中的主体层17A'的P型杂质浓度高于常规晶体管。

4. 发明申请

US20070166925A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20070166925A1
公开(公告)日：2007-07-19
申请号：US11617517
申请日：2006-12-28
申请人： Yasuhiro Takeda , Mitsuaki Morigami , Satoru Shimada , Kazuhiro Yoshitake , Shuichi Kikuchi , Seiji Otake , Toshiyuki Ohkoda
发明人： Yasuhiro Takeda , Mitsuaki Morigami , Satoru Shimada , Kazuhiro Yoshitake , Shuichi Kikuchi , Seiji Otake , Toshiyuki Ohkoda
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/7809 , H01L21/743 , H01L21/823487 , H01L27/088 , H01L29/0653 , H01L29/0696 , H01L29/41766 , H01L29/4236 , H01L29/66734 , H01L29/781
摘要： A semiconductor device includes a trench formed in a surface of a semiconductor substrate. A conductor is embedded in the trench. A conductive layer is arranged adjacent to the trench on the surface of the semiconductor substrate. Semiconductor elements, which include sources provided by one of the conductor and the conductive layer and drains provided by the other one of the conductor and the conductive layer, are formed in a semiconductor element formation region. A planar wiring layer is embedded in the semiconductor substrate under the entire semiconductor element formation region and connected to the conductor.
摘要翻译：半导体器件包括在半导体衬底的表面中形成的沟槽。导体嵌入在沟槽中。导电层被布置成与半导体衬底的表面上的沟槽相邻。包括由导体和导电层之一提供的源和由导体和导电层中的另一个提供的漏极的半导体元件形成在半导体元件形成区域中。在整个半导体元件形成区域的半导体衬底内嵌有平面布线层，并与导体连接。

5. 发明授权

US07439578B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07439578B2
公开(公告)日：2008-10-21
申请号：US11617517
申请日：2006-12-28
申请人： Yasuhiro Takeda , Mitsuaki Morigami , Satoru Shimada , Kazuhiro Yoshitake , Shuichi Kikuchi , Seiji Otake , Toshiyuki Ohkoda
发明人： Yasuhiro Takeda , Mitsuaki Morigami , Satoru Shimada , Kazuhiro Yoshitake , Shuichi Kikuchi , Seiji Otake , Toshiyuki Ohkoda
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/06
CPC分类号： H01L29/7809 , H01L21/743 , H01L21/823487 , H01L27/088 , H01L29/0653 , H01L29/0696 , H01L29/41766 , H01L29/4236 , H01L29/66734 , H01L29/781
摘要： A semiconductor device includes a trench formed in a surface of a semiconductor substrate. A conductor is embedded in the trench. A conductive layer is arranged adjacent to the trench on the surface of the semiconductor substrate. Semiconductor elements, which include sources provided by one of the conductor and the conductive layer and drains provided by the other one of the conductor and the conductive layer, are formed in a semiconductor element formation region. A planar wiring layer is embedded in the semiconductor substrate under the entire semiconductor element formation region and connected to the conductor.
摘要翻译：半导体器件包括形成在半导体衬底的表面中的沟槽。导体嵌入在沟槽中。导电层被布置成与半导体衬底的表面上的沟槽相邻。包括由导体和导电层之一提供的源和由导体和导电层中的另一个提供的漏极的半导体元件形成在半导体元件形成区中。在整个半导体元件形成区域的半导体衬底内嵌有平面布线层，并与导体连接。

6. 发明授权

US07291883B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07291883B2
公开(公告)日：2007-11-06
申请号：US11360286
申请日：2006-02-22
申请人： Ryo Kanda , Shuichi Kikuchi , Seiji Otake
发明人： Ryo Kanda , Shuichi Kikuchi , Seiji Otake
IPC分类号： H01L29/792
CPC分类号： H01L29/7816 , H01L29/0878 , H01L29/1083 , H01L29/1087 , H01L29/42368 , H01L29/456 , H01L29/66681
摘要： In a conventional semiconductor device, there is a problem that an N-type diffusion region provided for protecting an element from an overvoltage is narrow and a breakdown current is concentrated so that a PN junction region for protection is broken. In a semiconductor device of the present invention, an N-type buried diffusion layer is formed across a substrate and an epitaxial layer. A P-type buried diffusion layer is formed across a wider region on an upper surface of the N-type buried diffusion layer so that a PN junction region for overvoltage protection is formed. A P-type diffusion layer is formed so as to be connected to the P-type diffusion layer. A breakdown voltage of the PN junction region is lower than a breakdown voltage between a source and a drain. With this structure, the concentration of the breakdown current is prevented so that the semiconductor device can be protected from the overvoltage.
摘要翻译：在传统的半导体器件中，存在用于保护元件免于过电压的N型扩散区域窄并且击穿电流被集中以使得用于保护的PN结区域被破坏的问题。在本发明的半导体器件中，在衬底和外延层上形成N型掩埋扩散层。在N型掩埋扩散层的上表面上的较宽区域上形成P型埋入扩散层，从而形成用于过电压保护的PN结区域。 P型扩散层形成为与P型扩散层连接。 PN结区域的击穿电压低于源极和漏极之间的击穿电压。利用这种结构，防止了击穿电流的集中，从而可以防止半导体器件免受过电压。

7. 发明申请

US20070148892A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070148892A1
公开(公告)日：2007-06-28
申请号：US11614527
申请日：2006-12-21
申请人： Seiji Otake , Ryo Kanda , Shuichi Kikuchi
发明人： Seiji Otake , Ryo Kanda , Shuichi Kikuchi
IPC分类号： H01L21/331
CPC分类号： H01L29/735 , H01L29/0692 , H01L29/6625
摘要： In a semiconductor device of the present invention, an N type epitaxial layer is stacked on a P type single crystal silicon substrate. In the epitaxial layer, an N type diffusion layer as a base draw-out region, P type diffusion layers as an emitter region, and P type diffusion layers as a collector region are formed. The emitter region has a region having a larger diffusion width in a portion deeper than in a vicinity of a surface thereof. In a lateral PNP transistor, a smallest base width is formed in a deep portion of the epitaxial layer. By use of this structure, even in a case where the collector region is narrowed, a desired hfe value can be realized. Thus, the device size can be reduced.
摘要翻译：在本发明的半导体器件中，N型外延层层叠在P型单晶硅基板上。在外延层中，形成作为基极引出区域的N型扩散层，作为发射极区域的P型扩散层和作为集电极区域的P型扩散层。发射极区域具有比在其表面附近更深的部分具有较大扩散宽度的区域。在横向PNP晶体管中，在外延层的深部形成最小的基极宽度。通过使用该结构，即使在集电极区域变窄的情况下，也能够实现期望的hfe值。因此，可以减小设备尺寸。

8. 发明申请

US20070145529A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070145529A1
公开(公告)日：2007-06-28
申请号：US11614496
申请日：2006-12-21
申请人： Seiji Otake , Ryo Kanda , Shuichi Kikuchi
发明人： Seiji Otake , Ryo Kanda , Shuichi Kikuchi
IPC分类号： H01L27/082
CPC分类号： H01L29/735 , H01L29/1008 , H01L29/6625
摘要： In a semiconductor device of the present invention, an N type epitaxial layer is stacked on a P type single crystal silicon substrate. In the epitaxial layer, an N type diffusion layer as a base draw-out region, P type diffusion layers as an emitter region, and P type diffusion layers as a collector region are formed. The emitter region has a region having a larger diffusion width in a portion deeper than in a vicinity of a surface thereof. In a lateral PNP transistor, a smallest base width is formed in a deep portion of the epitaxial layer. By use of this structure, recombination of free carriers (positive holes) on the surface is prevented. Thus, a desired hfe value can be realized.
摘要翻译：在本发明的半导体器件中，N型外延层层叠在P型单晶硅基板上。在外延层中，形成作为基极引出区域的N型扩散层，作为发射极区域的P型扩散层和作为集电极区域的P型扩散层。发射极区域具有比在其表面附近更深的部分具有较大扩散宽度的区域。在横向PNP晶体管中，在外延层的深部形成最小的基极宽度。通过使用这种结构，可以防止表面上游离载体（正孔）的复合。因此，可以实现期望的hfe值。

9. 发明申请

US20070096261A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070096261A1
公开(公告)日：2007-05-03
申请号：US11512617
申请日：2006-08-29
申请人： Seiji Otake , Ryo Kanda , Shuichi Kikuchi
发明人： Seiji Otake , Ryo Kanda , Shuichi Kikuchi
IPC分类号： H01L29/861 , H01L31/107
CPC分类号： H01L29/866 , H01L29/66106
摘要： In a conventional semiconductor device, there is a problem that zener diode characteristics vary due to a crystal defect on a silicon surface, and the like. In a semiconductor device of the present invention, an N type epitaxial layer 4 is formed on a P type single crystal silicon substrate 2. In the epitaxial layer 4, P type diffusion layers 5, 6, 7 and 8 as anode regions and an N type diffusion layer 9 as a cathode region are formed. A PN junction region between the P type diffusion layer 8 and the N type diffusion layer 9 forms a zener diode 1. By use of this structure, a current path is located in a deep portion of the epitaxial layer 4. Thus, it is made possible to prevent a variation in a saturation voltage of the zener diode 1 due to a crystal defect on a surface of the epitaxial layer 4, and the like.
摘要翻译：在传统的半导体器件中，存在齐纳二极管特性由于硅表面上的晶体缺陷等而变化的问题。在本发明的半导体器件中，在P型单晶硅基板2上形成有N型外延层4.在外延层4中，作为阳极区域的P型扩散层5,6,7,8，N 形成作为阴极区域的扩散层9。 P型扩散层8和N型扩散层9之间的PN结区域形成齐纳二极管1.通过这种结构，电流路径位于外延层4的深部。因此，可能防止由于外延层4的表面上的晶体缺陷导致的齐纳二极管1的饱和电压的变化等。

10. 发明授权

US07579651B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07579651B2
公开(公告)日：2009-08-25
申请号：US11393530
申请日：2006-03-29
申请人： Seiji Otake , Shuichi Kikuchi
发明人： Seiji Otake , Shuichi Kikuchi
IPC分类号： H01L29/94 , H01L29/78
CPC分类号： H01L29/0847 , H01L29/1083 , H01L29/456 , H01L29/7833
摘要： In a semiconductor device of the present invention, a thin gate oxide film is formed on a P-type diffusion layer. On the gate oxide film, a gate electrode is formed. N-type diffusion layers are formed in the P-type diffusion layer, and the N-type diffusion layer is used as a drain region. The N-type diffusion layer is diffused in a γ shape at least below the gate electrode. With the structure described above, a diffusion region of the N-type diffusion layer expands and comes to be a low-concentration region in the vicinity of a surface of an epitaxial layer. Thus, it is possible to reduce an electric field from the gate electrode and an electric field between a source and a drain.
摘要翻译：在本发明的半导体器件中，在P型扩散层上形成薄的栅氧化膜。在栅极氧化膜上形成栅电极。在P型扩散层中形成N型扩散层，N型扩散层用作漏极区域。 N型扩散层至少在栅电极下方以γ形扩散。利用上述结构，N型扩散层的扩散区域在外延层的表面附近膨胀并成为低浓度区域。因此，可以减少来自栅电极的电场和源极与漏极之间的电场。

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