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1. 发明授权

US3956637A Intercept valve controlling method and system for use in a heat power plant 失效
标题翻译：拦截阀控制方法和用于发电厂的系统
公开(公告)号：US3956637A
公开(公告)日：1976-05-11
申请号：US425838
申请日：1973-12-18
申请人： Hiroaki Aotsu , Akira Isono , Yoshihiro Uchiyama
发明人： Hiroaki Aotsu , Akira Isono , Yoshihiro Uchiyama
IPC分类号： F01D17/04 , F01D21/02 , F01D21/14 , F01K7/24 , H02P9/04 , H02J1/10
CPC分类号： F01K7/24 , F01D21/02
摘要： An intermediate intercept valve controlling method and system for use in a heat power plant wherein the occurrence of a fault in a transmission system is detected by an abrupt decrease in generator output, and the intercept valve is closed to a certain opening depending upon the magnitude of an output variation and is then opened when a rotor angle between the internal voltage and terminal voltage of the generator reaches the first peak value.
摘要翻译：一种用于热电厂的中间截流阀控制方法和系统，其中通过发电机输出的突然减小来检测传动系统中的故障的发生，并且截流阀根据输出变化，然后当发电机的内部电压和端子电压之间的转子角度达到第一峰值时打开。

2. 发明授权

US4326159A Method and apparatus for controlling excitation of a generator 失效
标题翻译：用于控制发电机的激励的方法和装置
公开(公告)号：US4326159A
公开(公告)日：1982-04-20
申请号：US71403
申请日：1979-08-30
申请人： Hiroaki Aotsu , Akira Isono , Tsutomu Inayama , Mamoru Fukushima
发明人： Hiroaki Aotsu , Akira Isono , Tsutomu Inayama , Mamoru Fukushima
IPC分类号： H02P9/10 , H02P9/14
CPC分类号： H02P9/10
摘要： Voltage, current and field voltage of a generator connected to an electric power system are sampled at a predetermined period for analog-digital conversion and then led to a digital computer. In addition to computation for AVR, the computer computes from its input the generator output power, and also monitors the occurrence of a fault, the removal of the fault and variation in the generator output in the system. After the occurrence of a fault, the field excitation of the generator is intensified until the generator output power reaches substantially a peak value, but after the peak value is substantially passed by, the excitation is conversely depressed to a value below the level which is present before the fault occurs. When the generator output power recovers the value which is present before the fault occurs, the computer returns to deliver the AVR output.
摘要翻译：连接到电力系统的发电机的电压，电流和电场电压以预定的时间被采样以进行模数转换，然后被引导到数字计算机。除了计算AVR之外，计算机还可以从输入端计算发电机的输出功率，同时监测故障的发生，故障的消除和系统发电机输出的变化。在故障发生之后，发电机的场激励增强，直到发电机输出功率达到基本上的峰值，但是在峰值基本上过去之后，激励被反而下降到低于存在的水平的值在故障发生之前。当发电机输出功率恢复故障发生之前存在的值时，计算机返回以传送AVR输出。

3. 发明授权

US4245182A Excitation control apparatus for a generator 失效
标题翻译：发电机励磁控制装置
公开(公告)号：US4245182A
公开(公告)日：1981-01-13
申请号：US891001
申请日：1978-03-28
申请人： Hiroaki Aotsu , Akira Isono , Masuo Goto , Koichi Kimura , Yasushi Momochi , Takaaki Kai , Satoshi Kitamura , Akihisa Kaihara , Hirosi Okada
发明人： Hiroaki Aotsu , Akira Isono , Masuo Goto , Koichi Kimura , Yasushi Momochi , Takaaki Kai , Satoshi Kitamura , Akihisa Kaihara , Hirosi Okada
IPC分类号： H02J3/50 , H02P9/10 , H02P9/14 , H02P9/30
CPC分类号： H02P9/10 , H02P9/30 , Y10S174/15 , Y10T307/718
摘要： A field control apparatus for a generator having a field winding comprises a terminal voltage control unit for controlling a field current of the generator in accordance with a difference between a terminal voltage signal of the generator and a reference voltage signal, which control unit has at least one of a line drop compensation function, an under-excitation limitation function, an over-excitation limitation function, a power factor regulation function, an armature winding over-current compensation function and a cross-current compensation function. The field control apparatus includes a detector as a common signal source for detecting active power and reactive power components at an output terminal of the generator and means responsive to the output of the detector for performing scalar operation in accordance with a function of the added compensation/control function described above. An output of the operating means is added to the differential signal as an added function signal to control the field current for excitation of the field winding.
摘要翻译：一种具有励磁绕组的发电机的现场控制装置，包括端子电压控制单元，用于根据发电机的端子电压信号与参考电压信号之间的差值控制发电机的励磁电流，该控制单元至少具有线路补偿功能，励磁限制功能，过励磁限制功能，功率因数调节功能，电枢绕组过电流补偿功能和交叉电流补偿功能之一。现场控制装置包括作为公共信号源的检测器，用于在发生器的输出端子处检测有功功率和无功功率分量，并且响应于检测器的输出，根据附加补偿/补偿的函数进行标量运算的装置，上述控制功能。操作装置的输出作为附加功能信号加到差分信号上，以控制用于励磁绕组的励磁电流。

4. 发明授权

US5838337A Graphic system including a plurality of one chip semiconductor integrated circuit devices for displaying pixel data on a graphic display 失效
标题翻译：图形系统包括用于在图形显示器上显示像素数据的多个单芯片半导体集成电路器件
公开(公告)号：US5838337A
公开(公告)日：1998-11-17
申请号：US294406
申请日：1994-08-23
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
IPC分类号： G06F7/575 , G06T1/20 , G06T1/60 , G09G5/393 , G06F15/76
CPC分类号： G06F7/575 , G06T1/20 , G06T1/60 , G09G5/393 , G09G2340/10
摘要： A graphic system which includes a display device having a graphic display area which includes a plurality of display portions and a plurality of one-chip semiconductor integrated circuit devices. Each one-chip semiconductor integrated circuit includes memory for storing a plurality of pixel data, each pixel data includes a plurality of bits and color data, and a logic circuit for carrying out logic operation on a unit of one pixel data read out from the memory based on a function signal supplied to the one-chip semiconductor integrated circuit device. The function signal indicates a relation between the unit of one pixel data read out from the memory and pixel data output by the logic circuit. The invention further includes an external device for supplying the function signal to the one-chip semiconductor integrated circuit device. The logic circuits, of the plurality of one-chip semiconductor integrated circuit devices, each carry out the same logic operation in accordance with the function signal. Further the logic circuit of the one-chip semiconductor integrated circuit device outputs pixel data based on the logic operation carried out by the logic circuit so as to display the pixel data from the logic circuit on one of the display portions of the graphic display area of the display device.
摘要翻译：一种包括具有包括多个显示部分和多个单芯片半导体集成电路装置的图形显示区域的显示装置的图形系统。每个单芯片半导体集成电路包括用于存储多个像素数据的存储器，每个像素数据包括多个位和颜色数据，以及用于对从存储器读出的一个像素数据的单元执行逻辑运算的逻辑电路基于提供给单芯片半导体集成电路器件的功能信号。功能信号表示从存储器读出的一个像素数据的单位与由逻辑电路输出的像素数据之间的关系。本发明还包括用于将功能信号提供给单芯片半导体集成电路器件的外部器件。多个单芯片半导体集成电路装置的逻辑电路各自根据功能信号执行相同的逻辑运算。此外，单芯片半导体集成电路器件的逻辑电路基于由逻辑电路执行的逻辑运算输出像素数据，以便在逻辑电路的图形显示区域的显示部分之一上显示来自逻辑电路的像素数据显示设备。

5. 发明授权

US5592649A RAM control method and apparatus for presetting RAM access modes 失效
标题翻译：用于预置RAM访问模式的RAM控制方法和装置
公开(公告)号：US5592649A
公开(公告)日：1997-01-07
申请号：US279843
申请日：1994-07-26
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara
IPC分类号： G06F7/575 , G06T1/20 , G06T1/60 , G09G5/393 , G06F9/00 , G06F9/302
CPC分类号： G06F7/575 , G06T1/20 , G06T1/60 , G09G5/393 , G09G2340/10
摘要： A memory circuit including memory elements on which the data read, write, and store operations can be arbitrarily performed, the memory elements having a dyadic/arithmetic operation function. utilizing presetting in a read/modify/write mode to be executed during a memory cycle and in an interval in which data from the memory elements and data from external devices exist, an operation is executed between the external data and the data in the memory elements and the operation result is stored during a write cycle, thereby achieving a higher-speed operation.
摘要翻译：包括可以任意执行数据读取，写入和存储操作的存储器元件的存储器电路，存储元件具有二进制/算术运算功能。利用在读/写/写模式下的预置在存储器周期中执行，并且在来自存储器元件的数据和来自外部设备的数据存在的间隔中，在外部数据和存储元件中的数据之间执行操作并且在写入周期期间存储操作结果，从而实现更高速的操作。

6. 发明授权

US5347643A Bus system for coordinating internal and external direct memory access controllers 失效
标题翻译：用于协调内部和外部直接存储器访问控制器的总线系统
公开(公告)号：US5347643A
公开(公告)日：1994-09-13
申请号：US656676
申请日：1991-02-19
申请人： Nobukazu Kondo , Takashi Maruyama , Keiichi Isamu , Hiroaki Aotsu
发明人： Nobukazu Kondo , Takashi Maruyama , Keiichi Isamu , Hiroaki Aotsu
IPC分类号： G06F12/08 , G06F12/10 , G06F13/28 , G06F13/368
CPC分类号： G06F13/28 , G06F12/1045 , G06F12/0879
摘要： A one-chip microprocessor including an instruction execution unit, a DMA controller, and a memory management unit. The instruction execution unit has a logical address for storing an address to be accessed. The DMA controller has a DMA register for storing an address given when direct memory access is performed. The memory execution unit further includes an address converting means for converting a logical address stored in the logical address register of the instruction execution unit into a physical address to be accessed, a hit determining means for determining whether or not the cache memory connected as an external unit is hit on the basis of the physical address, and a burst transfer circuit for performing burst transfer of the cache memory. The one-chip microprocessor is connected by a bus to a system having a cache memory, a memory controller and a main memory.
摘要翻译：包括指令执行单元，DMA控制器和存储器管理单元的单片微处理器。指令执行单元具有用于存储要访问的地址的逻辑地址。 DMA控制器具有用于存储执行直接存储器访问时给定的地址的DMA寄存器。存储器执行单元还包括地址转换装置，用于将存储在指令执行单元的逻辑地址寄存器中的逻辑地址转换为要访问的物理地址;命中确定装置，用于确定作为外部连接的高速缓冲存储器基于物理地址命中单元，以及用于执行高速缓冲存储器的突发传送的突发传送电路。单片微处理器通过总线连接到具有高速缓冲存储器，存储器控制器和主存储器的系统。

7. 发明授权

US5175816A Method and apparatus for bit operational process 失效
标题翻译：位操作过程的方法和装置
公开(公告)号：US5175816A
公开(公告)日：1992-12-29
申请号：US641064
申请日：1991-01-14
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Kiichiro Urabe
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Kiichiro Urabe
IPC分类号： G06F9/308
CPC分类号： G06F9/30018
摘要： A bit operation processor having a first address operation unit for updating the address of data in units of a byte or multiple bytes for performing operation in units of a byte or multiple bytes, a second address operation unit for updating the address of data in units of a bit or multiple bits, an address control means operating on the first address operation unit to advance the address in response to the result of address advancement by the second address operation unit, and means for fetching byte-wide data for operation as addressed by the first address operation unit, whereby operation between data of any number of bits at any positions in byte blocks is controlled simply and fast.
摘要翻译：一种位操作处理器，具有第一地址操作单元，用于以字节或多字节为单位更新数据单元的地址，以单字节或多字节为单位执行操作;第二地址操作单元，用于以位或多位，地址控制装置，用于响应于由第二地址操作单元的地址提前结果而在第一地址操作单元上操作以提前地址;以及装置，用于获取用于操作的字节宽数据，第一地址操作单元，从而简单且快速地控制字节块中任何位置处的任何位数的数据之间的操作。

8. 发明授权

US4849907A Draw processing method and apparatus 失效
标题翻译：绘制处理方法和装置
公开(公告)号：US4849907A
公开(公告)日：1989-07-18
申请号：US848459
申请日：1986-04-07
申请人： Hiroaki Aotsu , Toshihiko Ogura , Koichi Kimura , Tadashi Kuwabara , Yuuichi Makaya
发明人： Hiroaki Aotsu , Toshihiko Ogura , Koichi Kimura , Tadashi Kuwabara , Yuuichi Makaya
IPC分类号： G06F3/153 , G06F3/14 , G06T11/00 , G06T11/20 , G09G5/393
CPC分类号： G09G5/393 , G06T11/203
摘要： In a draw processing apparatus for drawing a character, pattern or image; a segment element of a horizontal or vertical continuous run length, a coordinate of a start point of the segment and a direction coefficient of the segment are calculated, a boundary coordinate of a draw area in which a data is to be drawn is calculated in accordance with a position and a size of the draw area, a valid portion and an invalid portion of the segment are calculated for each segment element for the result first calculation result in accordance with the second calculation result, and the valid segment portion is drawn in accordance with the first calculation result.
摘要翻译：在用于绘制字符，图案或图像的绘制处理装置中; 计算水平或垂直连续行程长度的段元素，段的开始点的坐标和段的方向系数，根据其中绘制数据的绘制区域的边界坐标根据第二计算结果，针对结果第一计算结果针对每个段元素计算绘制区域的位置和大小，对于段的有效部分和无效部分，并根据第二计算结果绘制有效段部分具有第一个计算结果。

9. 发明授权

US5767864A One chip semiconductor integrated circuit device for displaying pixel data on a graphic display 失效
标题翻译：一种用于在图形显示器上显示像素数据的芯片半导体集成电路器件
公开(公告)号：US5767864A
公开(公告)日：1998-06-16
申请号：US294405
申请日：1994-08-23
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
IPC分类号： G06F7/575 , G06T1/20 , G06T1/60 , G09G5/393 , G06F15/76
CPC分类号： G06F7/575 , G06T1/20 , G06T1/60 , G09G5/393 , G09G2340/10
摘要： A device for displaying pixel data on a graphic display area of a display device. The graphic display area includes a plurality of display portions. The invention includes a memory for storing a plurality of pixel data, each pixel data includes a plurality of bits and color data, and a logic circuit for carrying out a logic operation on a combination of a unit of one pixel data read out from the memory and external data supplied to the device. The logic circuit outputs pixel data based on the logic operation so as to display the pixel data on one of the display portions of the graphic display area of the display device.
摘要翻译：一种用于在显示装置的图形显示区域上显示像素数据的装置。图形显示区域包括多个显示部分。本发明包括用于存储多个像素数据的存储器，每个像素数据包括多个位和颜色数据，以及逻辑电路，用于对从存储器读出的一个像素数据的单位的组合进行逻辑运算并提供给设备的外部数据。逻辑电路基于逻辑运算输出像素数据，以便在显示装置的图形显示区域的一个显示部分上显示像素数据。

10. 发明授权

US5617360A Memory device 失效
标题翻译：内存设备
公开(公告)号：US5617360A
公开(公告)日：1997-04-01
申请号：US588232
申请日：1996-01-18
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
IPC分类号： G06F7/575 , G06T1/20 , G06T1/60 , G09G5/393 , G11C13/00
CPC分类号： G06T1/20 , G06F7/575 , G06T1/60 , G09G5/393 , G09G2340/10
摘要： A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.
摘要翻译：形成在IC芯片上的存储器件包括用于进行数据读取和写入操作的动态随机存取存储器，用于从IC芯片的外部侧接收数据的第一和第二数据端子以及具有连接到IC芯片的第一数据输入端的控制器用于接收第一数据的数据终端，连接以接收第二数据读取的第二输入，连接到第二数据终端以接收功能模式信号的第三数据输入，以及用于执行从第一数据输入提供的第一数据之间的操作的操作单元以及从第二输入提供的第二数据。操作单元包括功能设置单元，其响应于在接收到第一数据之前设置由功能模式信号指示的功能的功能模式信号。从存储位置的选定部分读出第二数据。对于第一和第二数据执行与由功能设置单元设置的功能相对应的操作。在一个存储器周期期间，通过动态随机存取存储器的输入将执行的结果写入存储位置的所选部分。

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