专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120250399A1 MEMORY CIRCUIT USING SPIN MOSFETS, PATH TRANSISTOR CIRCUIT WITH MEMORY FUNCTION, SWITCHING BOX CIRCUIT, SWITCHING BLOCK CIRCUIT, AND FIELD PROGRAMMABLE GATE ARRAY 有权
标题翻译：使用旋转MOSFET的存储器电路，具有存储器功能的路径晶体管电路，开关盒电路，开关块电路和现场可编程门阵列
公开(公告)号：US20120250399A1
公开(公告)日：2012-10-04
申请号：US13403308
申请日：2012-02-23
申请人： Hideyuki SUGIYAMA , Masato ODA , Shinobu FUJITA , Tetsufumi TANAMOTO , Mizue ISHIKAWA , Takao MARUKAME , Tomoaki INOKUCHI , Yoshiaki SAITO
发明人： Hideyuki SUGIYAMA , Masato ODA , Shinobu FUJITA , Tetsufumi TANAMOTO , Mizue ISHIKAWA , Takao MARUKAME , Tomoaki INOKUCHI , Yoshiaki SAITO
IPC分类号： G11C11/16 , H03K19/177
CPC分类号： G11C5/148 , G11C11/161 , G11C11/1673 , G11C11/1675
摘要： A memory circuit according to an embodiment includes: a first transistor including a first source/drain electrode, a second source/drain electrode, and a first gate electrode; a second transistor including a third source/drain electrode connected to the second source/drain electrode, a fourth source/drain electrode, and a second gate electrode; a third transistor and a fourth transistor forming an inverter circuit, the third transistor including a fifth source/drain electrode, a sixth source/drain electrode, and a third gate electrode connected to the second source/drain electrode, the fourth transistor including a seventh source/drain electrode connected to the sixth source/drain electrode, an eighth source/drain electrode, and a fourth gate electrode connected to the second source/drain electrode; and an output terminal connected to the sixth source/drain electrode. At least one of the third transistor and the fourth transistor is a spin MOSFET, and an output of the inverter circuit is sent from the output terminal.
摘要翻译：根据实施例的存储器电路包括：第一晶体管，包括第一源极/漏极，第二源极/漏极和第一栅电极; 第二晶体管，包括连接到第二源极/漏极的第三源极/漏极，第四源极/漏极和第二栅极; 第三晶体管和形成逆变器电路的第四晶体管，所述第三晶体管包括第五源极/漏极，第六源极/漏极和连接到所述第二源极/漏极的第三栅电极，所述第四晶体管包括第七连接到第六源极/漏极的源极/漏极电极，连接到第二源极/漏极的第八源极/漏极电极和第四栅极电极; 以及连接到第六源极/漏极的输出端子。第三晶体管和第四晶体管中的至少一个是自旋MOSFET，并且从输出端子发送反相器电路的输出。

2. 发明申请

US20120074984A1 LOOK-UP TABLE CIRCUITS AND FIELD PROGRAMMABLE GATE ARRAY 有权
标题翻译：查看表电路和现场可编程门阵列
公开(公告)号：US20120074984A1
公开(公告)日：2012-03-29
申请号：US13238020
申请日：2011-09-21
申请人： Hideyuki SUGIYAMA , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
发明人： Hideyuki SUGIYAMA , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
IPC分类号： H03K19/177 , H03K5/00
CPC分类号： H03K19/177
摘要： A look-up table circuit according to an embodiment includes: a variable resistance circuit including variable resistance devices and selecting a variable resistance device from the variable resistance devices based on an input signal; a reference circuit having a resistance value between the largest resistance value and the smallest resistance value of the variable resistance circuit; a first n-channel MOSFET including a source connected to a terminal of the variable resistance circuit and a gate connected to a drain; a second n-channel MOSFET including a source connected to a terminal of the reference circuit and a gate connected to the gate of the first n-channel MOSFET; a first current supply circuit to supply a current to the variable resistance circuit; a second current supply circuit to supply a current to the reference circuit; and a comparator comparing voltages at a first input terminal and a second input terminal.
摘要翻译：根据实施例的查找表电路包括：可变电阻电路，包括可变电阻器件，并且基于输入信号从可变电阻器件中选择可变电阻器件; 参考电路，其具有可变电阻电路的最大电阻值和最小电阻值之间的电阻值; 第一n沟道MOSFET，其包括连接到可变电阻电路的端子的源极和连接到漏极的栅极; 第二n沟道MOSFET，其包括连接到参考电路的端子的源极和连接到第一n沟道MOSFET的栅极的栅极; 用于向可变电阻电路提供电流的第一电流供应电路; 第二电流供应电路，用于向参考电路提供电流; 以及比较器，用于比较第一输入端和第二输入端的电压。

3. 发明申请

US20110194342A1 NONVOLATILE MEMORY CIRCUIT USING SPIN MOS TRANSISTORS 有权
标题翻译：使用旋转MOS晶体管的非易失性存储器电路
公开(公告)号：US20110194342A1
公开(公告)日：2011-08-11
申请号：US12889881
申请日：2010-09-24
申请人： Hideyuki SUGIYAMA , Tetsufumi TANAMOTO , Takao MARUKAME , Mizue ISHIKAWA , Tomoaki INOKUCHI , Yoshiaki SAITO
发明人： Hideyuki SUGIYAMA , Tetsufumi TANAMOTO , Takao MARUKAME , Mizue ISHIKAWA , Tomoaki INOKUCHI , Yoshiaki SAITO
IPC分类号： G11C11/14
CPC分类号： G11C14/0081
摘要： Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.
摘要翻译：某些实施例提供了其中第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管串联连接的非易失性存储器电路，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管串联连接第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管的栅极连接，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管的栅极连接，第一n沟道晶体管包括连接到第一p沟道晶体管的漏极和第二p沟道晶体管的栅极的漏极，第二n沟道晶体管包括连接到第二p沟道晶体管的漏极和第一p沟道晶体管的栅极的漏极 p沟道晶体管，第一和第二n沟道晶体管的栅极连接。

4. 发明申请

US20090179667A1 RECONFIGURABLE LOGIC CIRCUIT 有权
标题翻译：可重新配置的逻辑电路
公开(公告)号：US20090179667A1
公开(公告)日：2009-07-16
申请号：US12339638
申请日：2008-12-19
申请人： Hideyuki SUGIYAMA , Mizue ISHIKAWA , Tomoaki INOKUCHI , Yoshiaki SAITO , Tetsufumi TANAMOTO
发明人： Hideyuki SUGIYAMA , Mizue ISHIKAWA , Tomoaki INOKUCHI , Yoshiaki SAITO , Tetsufumi TANAMOTO
IPC分类号： H03K19/094 , H03K19/173
CPC分类号： H03K19/1733 , G11C11/161 , G11C11/1675 , G11C11/1697
摘要： It is made possible to provide a reconfigurable logic circuit with which high integration can be achieved. A reconfigurable logic circuit includes: a multiplexer which includes a plurality of spin MOSFETs each having a source and drain containing a magnetic material, and a selecting portion including a plurality of MOSFETs and selecting a spin MOSFET from the plurality of spin MOSFETs, based on control data transmitted from control lines; a determining circuit which determines whether magnetization of the magnetic material of the source and drain of a selected spin MOSFET, which is selected by the selecting portion, is in a first state or in a second state; and a first and second write circuits which put the magnetization of the magnetic material of the source and drain of the selected spin MOSFET into the second and first states respectively by supplying a write current flowing between the source and drain of the selected spin MOSFET.
摘要翻译：可以提供可实现高集成度的可重构逻辑电路。可重配置逻辑电路包括：多路复用器，其包括多个自旋MOSFET，每个具有包含磁性材料的源极和漏极，以及包括多个MOSFET的选择部分，并且基于控制从多个自旋MOSFET中选择自旋MOSFET 从控制线传输的数据; 确定电路，其确定由选择部分选择的所选择的自旋MOSFET的源极和漏极的磁性材料的磁化是处于第一状态还是处于第二状态; 以及第一和第二写入电路，其通过提供在选定的自旋MOSFET的源极和漏极之间流动的写入电流，将所选自旋MOSFET的源极和漏极的磁性材料的磁化分别置于第二和第一状态。

5. 发明申请

US20100072529A1 STACK HAVING HEUSLER ALLOY, MAGNETORESISTIVE ELEMENT AND SPIN TRANSISTOR USING THE STACK, AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有合金的堆叠，使用堆叠的磁体元件和旋转晶体管及其制造方法
公开(公告)号：US20100072529A1
公开(公告)日：2010-03-25
申请号：US12565303
申请日：2009-09-23
申请人： Takao MARUKAME , Mizue ISHIKAWA , Tomoaki INOKUCHI , Hideyuki SUGIYAMA , Yoshiaki SAITO
发明人： Takao MARUKAME , Mizue ISHIKAWA , Tomoaki INOKUCHI , Hideyuki SUGIYAMA , Yoshiaki SAITO
IPC分类号： H01L29/82 , B05D3/02 , B32B15/04
CPC分类号： H01L29/66984 , H01F10/1936 , H01F10/265 , H01L27/228 , H01L43/10 , H01L43/12 , Y10T428/12611
摘要： A stack includes a crystalline MgO layer, crystalline Heusler alloy layer, and amorphous Heusler alloy layer. The crystalline Heusler alloy layer is provided on the MgO layer. The amorphous Heusler alloy layer is provided on the crystalline Heusler alloy layer.
摘要翻译：堆叠包括结晶MgO层，结晶Heusler合金层和非晶Heusler合金层。结晶Heusler合金层设置在MgO层上。非晶Heusler合金层设置在结晶Heusler合金层上。

6. 发明申请

US20120218802A1 CONTENT ADDRESSABLE MEMORY 失效
标题翻译：内容可寻址内存
公开(公告)号：US20120218802A1
公开(公告)日：2012-08-30
申请号：US13403398
申请日：2012-02-23
申请人： Takao MARUKAME , Tomoaki INOKUCHI , Hideyuki SUGIYAMA , Mizue ISHIKAWA , Yoshiaki SAITO , Atsuhiro KINOSHITA , Kosuke TATSUMURA
发明人： Takao MARUKAME , Tomoaki INOKUCHI , Hideyuki SUGIYAMA , Mizue ISHIKAWA , Yoshiaki SAITO , Atsuhiro KINOSHITA , Kosuke TATSUMURA
IPC分类号： G11C15/02
CPC分类号： G11C15/02 , G11C11/161 , G11C15/046 , H01L27/228
摘要： One embodiment provides a content addressable memory, including: a pair of spin MOSFETs including: a first spin MOSFET whose magnetization state is set in accordance with stored data; and a second spin MOSFET whose magnetization state is set in accordance with the stored data, the second spin MOSFET being connected in parallel with the first spin MOSFET; a first wiring configured to apply a gate voltage so that any one of the first spin MOSFET and the second spin MOSFET becomes electrically conductive in accordance with search data; and a second wiring configured to apply a current to both of the first spin MOSFET and the second spin MOSFET.
摘要翻译：一个实施例提供一种内容可寻址存储器，包括：一对自旋MOSFET，其包括：第一自旋MOSFET，其磁化状态根据存储的数据设置; 以及第二自旋MOSFET，其磁化状态根据存储的数据设定，第二自旋MOSFET与第一自旋MOSFET并联连接; 第一布线，被配置为施加栅极电压，使得第一自旋MOSFET和第二自旋MOSFET中的任何一个根据搜索数据变为导电; 以及配置为向第一自旋MOSFET和第二自旋MOSFET两者施加电流的第二布线。

7. 发明申请

US20100073025A1 PROGRAMMABLE LOGIC CIRCUIT 有权
标题翻译：可编程逻辑电路
公开(公告)号：US20100073025A1
公开(公告)日：2010-03-25
申请号：US12404606
申请日：2009-03-16
申请人： Tetsufumi TANAMOTO , Hideyuki SUGIYAMA , Kazutaka IKEGAMI , Yoshiaki SAITO
发明人： Tetsufumi TANAMOTO , Hideyuki SUGIYAMA , Kazutaka IKEGAMI , Yoshiaki SAITO
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , G11C13/0002 , H03K19/17764 , H03K19/1778 , H03K19/17784 , H03K19/18
摘要： A programmable logic circuit includes: an input circuit configured to receive a plurality of input signals; and a programmable cell array including a plurality of unit programmable cells arranged in a matrix form, each of the unit programmable cells including a first memory circuit of resistance change type including a first transistor and a second memory circuit of resistance change type including a second transistor, the first and second memory circuits connected in parallel, each gate of the first transistors on same row respectively receiving one input signal, each gate of the second transistors on same row receiving an inverted signal of the one input signal, output terminals of the first and second memory circuits on same column being connected to a common output line.
摘要翻译：可编程逻辑电路包括：输入电路，被配置为接收多个输入信号; 以及包括以矩阵形式布置的多个单元可编程单元的可编程单元阵列，每个单元可编程单元包括电阻改变型的第一存储器电路，包括第一晶体管和包括第二晶体管的电阻变化型的第二存储器电路并联连接的第一和第二存储器电路，同一行上的第一晶体管的每个栅极分别接收一个输入信号，同一行上的第二晶体管的每个栅极接收一个输入信号的反相信号，第一个输出端的输出端并且同一列上的第二存储器电路连接到公共输出线。

8. 发明申请

US20080239930A1 SPIN FET, MAGNETORESISTIVE ELEMENT AND SPIN MEMORY 失效
标题翻译：旋转FET，磁电元件和旋转存储器
公开(公告)号：US20080239930A1
公开(公告)日：2008-10-02
申请号：US12029117
申请日：2008-02-11
申请人： Yoshiaki SAITO , Hideyuki SUGIYAMA , Tomoaki INOKUCHI
发明人： Yoshiaki SAITO , Hideyuki SUGIYAMA , Tomoaki INOKUCHI
IPC分类号： G11B9/00
CPC分类号： G01R33/093 , B82Y10/00 , B82Y25/00 , G11C11/16 , H01L27/228 , H01L29/66984 , H01L29/7881 , H01L43/08
摘要： A spin FET includes a first ferromagnetic film disposed on a first source/drain area, a direction of magnetization thereof being fixed in an upward direction or a downward direction perpendicular to a film surface, a second ferromagnetic film disposed on a second source/drain area, a direction of magnetization thereof being changed in the upward direction or the downward direction, an anti-ferromagnetic ferroelectric film disposed on the second ferromagnetic film, and a tunnel barrier film disposed at least between the first source/drain area and the first ferromagnetic film or between the second source/drain and the second ferromagnetic film. Resistance of the anti-ferromagnetic ferroelectric film is larger than ON resistance when the first and second source/drain areas conduct electricity through the channel area.
摘要翻译：自旋FET包括设置在第一源/漏区上的第一铁磁膜，其磁化方向沿垂直于膜表面的向上方向或向下方向固定，第二铁磁膜设置在第二源/漏区其磁化方向在向上方向或向下方向上变化，设置在第二铁磁性膜上的反铁磁性铁电体膜和至少设置在第一源极/漏极区域与第一铁磁性膜之间的隧道势垒膜或者在第二源极/漏极和第二铁磁膜之间。当第一和第二源极/漏极区域通过沟道区域导电时，反铁磁铁电体膜的电阻大于导通电阻。

9. 发明申请

US20080283888A1 SPIN TRANSISTOR, PROGRAMMABLE LOGIC CIRCUIT, AND MAGNETIC MEMORY 有权
标题翻译：旋转晶体管，可编程逻辑电路和磁记忆
公开(公告)号：US20080283888A1
公开(公告)日：2008-11-20
申请号：US12169423
申请日：2008-07-08
申请人： Yoshiaki SAITO , Hideyuki SUGIYAMA
发明人： Yoshiaki SAITO , Hideyuki SUGIYAMA
IPC分类号： H01L29/94 , H01L29/82
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/161 , H01L29/66984 , Y10S977/932 , Y10S977/933 , Y10S977/936
摘要： A spin transistor includes a non-magnetic semiconductor substrate having a channel region, a first area, and a second area. The channel region is between the first and the second areas. The spin transistor also includes a first conductive layer located above the first area and made of a ferromagnetic material magnetized in a first direction; and a second conductive layer located above the second area and made of a ferromagnetic material magnetized in one of the first direction and a second direction that is antiparallel with respect to the first direction. The channel region introduces electron spin between the conductive layers. The spin transistor also includes a gate electrode located between the conductive layers and above the channel region; and a tunnel barrier film located between the non-magnetic semiconductor substrate and at least one of the conductive layers.
摘要翻译：自旋晶体管包括具有沟道区，第一区和第二区的非磁性半导体衬底。通道区域在第一和第二区域之间。自旋晶体管还包括位于第一区域上方并由沿第一方向磁化的铁磁材料制成的第一导电层; 以及第二导电层，其位于第二区域上方并由在相对于第一方向反平行的第一方向和第二方向中的一个中被磁化的铁磁材料制成。沟道区域在导电层之间引入电子自旋。自旋晶体管还包括位于导电层之间并位于沟道区之上的栅电极; 以及位于非磁性半导体衬底和至少一个导电层之间的隧道阻挡膜。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式