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1. 发明授权

US5157478A Tape automated bonding packaged semiconductor device incorporating a heat sink 失效
标题翻译：带有自动键合封装的半导体器件，包含散热片
公开(公告)号：US5157478A
公开(公告)日：1992-10-20
申请号：US810354
申请日：1991-12-18
申请人： Tetsuya Ueda , Haruo Shimamoto , Yasuhiro Teraoka , Hideya Yagoura , Hiroshi Seki
发明人： Tetsuya Ueda , Haruo Shimamoto , Yasuhiro Teraoka , Hideya Yagoura , Hiroshi Seki
IPC分类号： H01L21/56 , H01L23/16 , H01L23/433 , H01L23/495
CPC分类号： H01L24/50 , H01L21/565 , H01L23/16 , H01L23/4334 , H01L23/49572 , H01L2224/50 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01082 , H01L2924/07802 , H01L2924/16152 , H01L2924/3511
摘要： A packaged semiconductor device includes an insulating film having an opening, a semiconductor chip disposed in the opening of the insulating film and having a plurality of electrodes, a plurality of leads, each having one end connected to a corresponding electrode, the plurality of leads being supported on the insulating film, a heat radiator disposed opposite and spaced from the semiconductor chip, and a resin package body encapsulating the semiconductor chip and part of the heat radiator, leaving a surface of the heat radiator externally exposed and the second ends of the plurality of leads extending outwardly from the package.
摘要翻译：封装半导体器件包括具有开口的绝缘膜，设置在绝缘膜的开口中并具有多个电极的半导体芯片，多个引线，每个引线的一端连接到相应的电极，多个引线为支撑在绝缘膜上，与半导体芯片相对且间隔开的散热器，以及封装半导体芯片和散热器的一部分的树脂封装体，使散热器的外表面露出，并且多个第二端的引线从封装向外延伸。

2. 发明授权

US5359203A Laser OLB apparatus and method of mounting semiconductor device 失效
标题翻译：激光OLB装置和半导体装置的安装方法
公开(公告)号：US5359203A
公开(公告)日：1994-10-25
申请号：US70242
申请日：1993-06-02
申请人： Mitsuya Hashii , Haruo Shimamoto , Hideya Yagoura
发明人： Mitsuya Hashii , Haruo Shimamoto , Hideya Yagoura
IPC分类号： H05K3/34 , B23K26/03 , B23K26/04 , G01N21/88 , H05K13/08 , G01N21/86
CPC分类号： B23K26/032 , B23K26/04 , G01N21/88 , H05K13/08 , H05K3/3421 , H05K3/3494
摘要： A laser OLB apparatus includes an XY table; a bonding laser source for irradiating bonding parts between bonding lands of a substrate and leads of a semiconductor device located on the substrate thereby bonding the bonding parts; a recognition device for recognizing whether the leads of the semiconductor device are free of flexure and deviation; and a control unit for controlling the XY table and the laser source so that bonding is conducted only when the recognition device has recognized that the leads are free of flexure and deviation.
摘要翻译：激光OLB装置包括XY台; 用于照射基板的接合台面和位于基板上的半导体器件的引线之间的接合部分的接合激光源，从而结合接合部分; 用于识别半导体器件的引线是否没有挠曲和偏差的识别装置; 以及用于控制XY工作台和激光源的控制单元，使得仅当识别装置已经认识到引线没有挠曲和偏移时才进行接合。

3. 发明授权

US4826068A Outer lead bonding device utilizing tape carriers 失效
标题翻译：使用带载体的外引线接合装置
公开(公告)号：US4826068A
公开(公告)日：1989-05-02
申请号：US210083
申请日：1988-06-22
申请人： Hideya Yagoura , Haruo Shimamoto
发明人： Hideya Yagoura , Haruo Shimamoto
IPC分类号： H05K3/32 , H01L21/60 , H05K3/30 , H05K3/34 , H05K13/04 , B23K1/20
CPC分类号： H01L24/50 , H01L24/32 , H01L24/86 , H05K13/0465 , H05K3/303 , H01L2224/4899 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01057 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H05K2201/10681 , H05K2201/2036 , H05K2203/0195 , H05K3/3421 , H05K3/3494 , Y02P70/613 , Y10T29/49135
摘要： A bonding device for effecting outer lead bonding is disclosed which comprises a bonding stage, a pair of bonding tools, and lead supporting means. The lead supporting means may take the form of a pair of projections formed on the upper surface of the bonding stage at horizontal locations thereof which are situated below the lead supporting portion of the tape carrier. Alternatively, the lead supporting means may take the form of a pair of horizontally extending rectangular columns which are retractably inserted into the above specified horizontal locations of the upper surface of the bonding stage. Thus, leads can be formed simultaneously with the outer lead bonding. The bonding stage may be divided into upper and lower stages, and the projections may be formed on the upper surface of the lower stage to extend through holes formed in the upper stage. This structure makes the projections retractable.
摘要翻译：公开了一种用于实现外引线接合的接合装置，其包括接合台，一对接合工具和引线支撑装置。引线支撑装置可以采取形成在接合台的上表面上的水平位置处的一对突起的形式，其位于带状物的引线支撑部分的下方。或者，引线支撑装置可以采取一对水平延伸的矩形柱的形式，其可伸缩地插入到结合台的上表面的上述指定的水平位置中。因此，可以与外引线接合同时形成引线。接合台可以分为上段和下段，并且突起可以形成在下级的上表面上，以延伸通过形成在上段中的孔。这种结构使得突起可伸缩。

4. 发明授权

US5412157A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5412157A
公开(公告)日：1995-05-02
申请号：US91929
申请日：1993-07-16
申请人： Hideya Yagoura , Noriaki Higuchi , Haruo Shimamoto
发明人： Hideya Yagoura , Noriaki Higuchi , Haruo Shimamoto
IPC分类号： H01L23/50 , H01L21/48 , H01L23/495 , H05K1/18 , H05K3/34 , H01L23/02
CPC分类号： H01L21/4842 , H01L23/49558 , H05K3/3426 , H01L2924/0002 , H05K2201/10424 , H05K2201/10689 , H05K3/3489 , Y02P70/613 , Y10T29/4922
摘要： A semiconductor device includes a molded resin encapsulating a semiconductor chip, outer leads extending from the molded resin and having free ends, and a resin layer connecting and supporting the outer leads along the entire length of the outer leads. The resin layer may have an activating ability for soldering. A method for manufacturing a semiconductor device includes preparing a semiconductor device having a molded resin and a plurality of outer lead portions extending from the molded resin and connected to a lead frame, forming a resin film on and between the outer lead portions; cutting the lead portions to provide cantilevered outer leads having free ends; lead-forming the outer leads with lead-forming dies while heating the resin film to form a resin layer connecting and supporting the outer leads along the entire lengths of the outer leads, and taking the semiconductor device out of the lead-forming dies after the resin layer has been cured.
摘要翻译：半导体器件包括封装半导体芯片的模制树脂，从模制树脂延伸并具有自由端的外部引线以及沿外部引线的整个长度连接和支撑外部引线的树脂层。树脂层可以具有用于焊接的活化能力。一种制造半导体器件的方法包括制备具有模制树脂的半导体器件和从模制树脂延伸并连接到引线框架的多个外引线部分，在外引线部分之间和之间形成树脂膜; 切割引线部分以提供具有自由端的悬臂式外引线; 在加热树脂膜的同时对引线形成外引线，以形成沿着外引线的整个长度连接和支撑外引线的树脂层，并且将半导体器件从引线成形模具中取出树脂层已经固化。

5. 发明授权

US5064706A Carrier tape including molten resin flow path element for resin packaged semiconductor devices 失效
标题翻译：载带，包括树脂封装半导体器件的熔融树脂流路元件
公开(公告)号：US5064706A
公开(公告)日：1991-11-12
申请号：US281401
申请日：1988-12-08
申请人： Tetsuya Ueda , Haruo Shimamoto , Hideya Yagoura , Hiroshi Seki , Yasuhiro Teraoka
发明人： Tetsuya Ueda , Haruo Shimamoto , Hideya Yagoura , Hiroshi Seki , Yasuhiro Teraoka
IPC分类号： H01L21/60 , H01L21/56 , H01L23/495
CPC分类号： H01L24/50 , H01L21/565 , H01L23/49524 , H01L23/49572 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , Y10S428/901 , Y10S428/906 , Y10T29/49121 , Y10T428/24273 , Y10T428/24298 , Y10T428/24322
摘要： A carrier tape includes a film having an opening for receiving a semiconductor chip to be resin-molded by a pair of mold halves and outer lead holes formed around the periphery of the opening, a plurality of leads for mounting the semiconductor chip on the film, and a resin running portion cooperating, when the mold halves are closed with the film held between the mold halves, with a gate formed on a parting surface of one of the mold halves to define a resin running path which extends from a portion of the film outside the outer lead holes to the opening for guiding a molten resin into the mold halves while preventing the resin from entering the outer lead holes.
摘要翻译：载带包括具有用于接收半导体芯片的开口的膜，该半导体芯片由一对半模形成，并且形成在开口周围的外部引线孔;多个用于将半导体芯片安装在膜上的引线，以及当所述半模被所述半模保持在所述半模之间的所述半模封闭时，与所述半模中的一个的分离面上形成的门形成一个树脂运行路径，从而形成从所述膜的一部分延伸的树脂行进路径，在外部引线孔外面到开口，用于将熔融树脂引导到半模中，同时防止树脂进入外部引线孔。

6. 发明授权

US4839713A Package structure for semiconductor device 失效
标题翻译：半导体器件的封装结构
公开(公告)号：US4839713A
公开(公告)日：1989-06-13
申请号：US156571
申请日：1988-02-17
申请人： Yasuhiro Teraoka , Tetsuya Ueda , Hideya Yagoura , Haruo Shimamoto , Shigeyuki Nango , Toshinobu Banjo , Hiroshi Seki
发明人： Yasuhiro Teraoka , Tetsuya Ueda , Hideya Yagoura , Haruo Shimamoto , Shigeyuki Nango , Toshinobu Banjo , Hiroshi Seki
IPC分类号： H01L23/057 , H01L23/24 , H01L23/31 , H01L23/495
CPC分类号： H01L24/50 , H01L23/057 , H01L23/24 , H01L23/3121 , H01L23/49572 , H01L2924/01005 , H01L2924/01033 , H01L2924/01068 , H01L2924/01079 , H01L2924/01082
摘要： A package structure comprising a metallic cap having a bottom wall to which the bottom surface of the semiconductor chip is electrically and mechanically connected, a side wall extending from said bottom wall and surrounding the semiconductor chip, and a flange extending outwardly from said side wall substantially parallel to said bottom wall, said flange supporting the lead conductors thereon through an electrically insulating material. The electrical connection means is disposed between the metallic cap flange and the lead conductor for establishing an electrical connection therebetween. The electrical connection means may comprise an electrically conductive projection formed on the flange of the metal cap, extending through a notch in the insulating material and electrically connected to the lead conductor. The electrical connection means may be an electrically conductive bonding material filled within a cavity defined by an opening in the flange of the metal cap, a through hole in the insulating material and a connecting pad of the lead conductor.
摘要翻译：一种包装结构，包括具有底壁的金属盖，半导体芯片的底表面电气和机械连接到该底壁，从所述底壁延伸并围绕半导体芯片的侧壁，以及从所述侧壁向外延伸的凸缘，平行于所述底壁，所述凸缘通过电绝缘材料在其上支撑引线导体。电连接装置设置在金属帽凸缘和引线导体之间，用于在它们之间建立电连接。电连接装置可以包括形成在金属帽的凸缘上的导电突起，延伸穿过绝缘材料中的凹口并电连接到引线导体。电连接装置可以是填充在由金属盖的凸缘中的开口，绝缘材料中的通孔和引线导体的连接焊盘限定的空腔内的导电接合材料。

7. 发明授权

US5166099A Manufacturing method for semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US5166099A
公开(公告)日：1992-11-24
申请号：US759912
申请日：1991-09-13
申请人： Tetsuya Ueda , Osami Nakagawa , Haruo Shimamoto , Yasuhiro Teraoka , Seiji Takemura
发明人： Tetsuya Ueda , Osami Nakagawa , Haruo Shimamoto , Yasuhiro Teraoka , Seiji Takemura
IPC分类号： H01L21/56 , H01L21/60 , H01L23/495
CPC分类号： H01L24/86 , H01L21/56 , H01L21/565 , H01L23/49572 , H01L2224/16245 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2224/7965 , H01L2924/01005 , H01L2924/01006 , H01L2924/0101 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01052 , H01L2924/01058 , H01L2924/01061 , H01L2924/01075 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , Y10T29/49121
摘要： A manufacturing method for a semiconductor device in which an electrode of a semiconductor chip is electrically connected to an inner lead of a carrier tape. The electrodes of the semiconductor chip are brought into contact with the inner lead of the carrier tape. Bonding is performed with inner lead droop controlled to no more than 80 .mu.m.
摘要翻译：一种半导体器件的制造方法，其中半导体芯片的电极电连接到载带的内引线。使半导体芯片的电极与载带的内引线接触。内部引线下垂控制在不超过80m的情况下进行接合。

8. 发明授权

US6046071A Plastic molded semiconductor package and method of manufacturing the same 失效
标题翻译：塑料模制半导体封装及其制造方法
公开(公告)号：US6046071A
公开(公告)日：2000-04-04
申请号：US976603
申请日：1997-11-24
申请人： Akiyoshi Sawai , Haruo Shimamoto , Toru Tachikawa , Jun Shibata
发明人： Akiyoshi Sawai , Haruo Shimamoto , Toru Tachikawa , Jun Shibata
IPC分类号： H01L21/56 , H01L21/58 , H01L21/60 , H01L21/68 , H01L23/12 , H01L23/28 , H01L23/31 , H01L23/367 , H01L23/485 , H01L23/498 , H05K3/30 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L21/568 , H01L21/563 , H01L21/565 , H01L23/3114 , H01L23/3121 , H01L23/3677 , H01L23/49816 , H01L23/49827 , H01L24/11 , H01L24/13 , H01L24/28 , H01L24/83 , H01L2224/11 , H01L2224/11003 , H01L2224/1147 , H01L2224/13 , H01L2224/13099 , H01L2224/13111 , H01L2224/1403 , H01L2224/16 , H01L2224/17051 , H01L2224/29111 , H01L2224/2919 , H01L2224/73203 , H01L2224/81207 , H01L2224/83102 , H01L2224/83104 , H01L2224/8319 , H01L2224/8385 , H01L2224/92125 , H01L2924/01004 , H01L2924/01005 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/1579 , H01L2924/181 , Y10T29/49169
摘要： A pad electrode is formed on a main surface of a semiconductor chip. A passivation film, which covers a surface portion of the pad electrode, is formed on the main surface of the semiconductor chip. An internal connection conductor is formed on a surface portion of the pad electrode. The semiconductor chip is covered with a molding resin which exposes only a top surface of the internal connection conductor. An external connection conductor is formed on a top surface of the internal connection conductor. The external connection conductor has a substantially flat top surface. Thereby, a plastic molded semiconductor package can be easily mounted on a printed board, and can have improved reliability after being joined on the printed board.
摘要翻译：在半导体芯片的主表面上形成焊盘电极。在半导体芯片的主表面上形成覆盖焊盘电极的表面部分的钝化膜。在焊盘电极的表面部分上形成内部连接导体。半导体芯片被仅暴露内部连接导体顶表面的模制树脂覆盖。外部连接导体形成在内部连接导体的顶表面上。外部连接导体具有基本平坦的顶表面。因此，塑料成型半导体封装可以容易地安装在印刷电路板上，并且可以在印刷电路板上接合之后具有改进的可靠性。

9. 发明申请

US20120184068A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120184068A1
公开(公告)日：2012-07-19
申请号：US13346716
申请日：2012-01-09
申请人： Yoshiyuki ABE , Chuichi Miyazaki , Toshihide Uematsu , Haruo Shimamoto
发明人： Yoshiyuki ABE , Chuichi Miyazaki , Toshihide Uematsu , Haruo Shimamoto
IPC分类号： H01L21/50
CPC分类号： H01L21/561 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L23/3121 , H01L23/544 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/78 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05124 , H01L2224/05554 , H01L2224/0557 , H01L2224/05582 , H01L2224/05644 , H01L2224/05655 , H01L2224/06181 , H01L2224/13022 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/48247 , H01L2224/48644 , H01L2224/48655 , H01L2224/49171 , H01L2224/73204 , H01L2224/73265 , H01L2224/78301 , H01L2224/85181 , H01L2224/85203 , H01L2224/85205 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06565 , H01L2225/06568 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2924/01032 , H01L2924/3512
摘要： A method includes the steps of: (a) fixing a front surface of a wafer (semiconductor wafer) having the front surface, a plurality of chip regions formed on the front surface, a dicing region formed between the chip regions, and a rear surface opposite to the front surface to the supporting member; (b) in a state of having the wafer fixed to the supporting member, grinding the rear surface of the wafer to expose the rear surface; (c) in a state of having the wafer fixed to the supporting member, dividing the wafer into the chip regions; (d) etching side surfaces of the chip regions to remove crushed layers formed in the step (c) on the side surfaces and obtain a plurality of semiconductor chips. After the steps (e) and (d), the plurality of divided chip regions are peeled off from the supporting member to obtain a plurality of semiconductor chips.
摘要翻译：一种方法包括以下步骤：（a）固定具有前表面的晶片（半导体晶片）的前表面，形成在前表面上的多个芯片区域，形成在芯片区域之间的切割区域和后表面与支撑构件的前表面相对; （b）在将晶片固定在支撑构件上的状态下，研磨晶片的后表面以暴露后表面; （c）在将晶片固定在支撑部件上的状态下，将晶片分割成芯片区域; （d）蚀刻芯片区域的侧表面以去除侧表面上的步骤（c）中形成的破碎层，并获得多个半导体芯片。在步骤（e）和（d）之后，将多个分割的芯片区域从支撑构件剥离以获得多个半导体芯片。

10. 发明授权

US06475829B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06475829B2
公开(公告)日：2002-11-05
申请号：US09929046
申请日：2001-08-15
申请人： Kazushi Hatauchi , Haruo Shimamoto
发明人： Kazushi Hatauchi , Haruo Shimamoto
IPC分类号： H01L2144
CPC分类号： H01L21/6835 , H01L2224/05573 , H01L2224/16 , H01L2224/73204 , H01L2224/83191 , H01L2924/00014 , H01L2924/01079 , H01L2924/15311 , H01L2224/05599
摘要： A semiconductor device of the present invention includes a semiconductor chip with bumps on a surface, and an adhesion sheet on the surface of semiconductor chip. The adhesion sheet has a film base material layer and a film adhesion layer for adhering the film base material layer to the semiconductor chip, and a part of the sheet melts upon heating and tears in response to pressure applied during flip chip bonding. Therefore, it is possible to obtain a semiconductor device which enables good flip chip bonding without any gaps between a device and a substrate in a simple manufacturing process, and to manufacture the semiconductor device.
摘要翻译：本发明的半导体器件包括在表面具有凸起的半导体芯片和在半导体芯片的表面上的粘合片。粘合片具有膜基材层和用于将膜基材层粘附到半导体芯片的膜粘合层，并且片的一部分在加热时熔化并且响应于在倒装芯片接合期间施加的压力而发生撕裂。因此，可以在简单的制造工艺中获得能够在器件和衬底之间没有任何间隙的良好的倒装芯片接合的半导体器件，并制造半导体器件。

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