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1. 发明授权

US07652503B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07652503B2
公开(公告)日：2010-01-26
申请号：US11644827
申请日：2006-12-26
申请人： Hidenari Nagata , Masanori Ishizuka , Tatsushi Otsuka
发明人： Hidenari Nagata , Masanori Ishizuka , Tatsushi Otsuka
IPC分类号： H03K19/0175 , G06F9/06
CPC分类号： H03K19/1733
摘要： A semiconductor device includes an external pin, a control parameter decision circuit, and a register update circuit. The control parameter decision circuit includes a register and an output selector. The register is initialized in accordance with resetting of the semiconductor device. The output selector, according to a level value of an external input signal supplied via the external pin, selects one of a signal whose level value is set equal to a register value of the register and a signal whose level value is set opposite to the register value of the register, and outputs the selected signal as a control parameter signal. The register update circuit updates the register value of the register when a level value of the control parameter signal need be changed.
摘要翻译：半导体器件包括外部引脚，控制参数判定电路和寄存器更新电路。控制参数判定电路包括寄存器和输出选择器。根据半导体器件的复位来初始化寄存器。输出选择器根据通过外部引脚提供的外部输入信号的电平值，选择其电平值设置为等于寄存器的寄存器值的信号和其电平值设置为与寄存器相反的信号并输出所选择的信号作为控制参数信号。当控制参数信号的电平值需要改变时，寄存器更新电路更新寄存器的寄存器值。

2. 发明申请

US20080122485A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20080122485A1
公开(公告)日：2008-05-29
申请号：US11644827
申请日：2006-12-26
申请人： Hidenari Nagata , Masanori Ishizuka , Tatsushi Otsuka
发明人： Hidenari Nagata , Masanori Ishizuka , Tatsushi Otsuka
IPC分类号： H03K19/0175
CPC分类号： H03K19/1733
摘要： A semiconductor device includes an external pin, a control parameter decision circuit, and a register update circuit. The control parameter decision circuit includes a register and an output selector. The register is initialized in accordance with resetting of the semiconductor device. The output selector, according to a level value of an external input signal supplied via the external pin, selects one of a signal whose level value is set equal to a register value of the register and a signal whose level value is set opposite to the register value of the register, and outputs the selected signal as a control parameter signal. The register update circuit updates the register value of the register when a level value of the control parameter signal need be changed.
摘要翻译：半导体器件包括外部引脚，控制参数判定电路和寄存器更新电路。控制参数判定电路包括寄存器和输出选择器。根据半导体器件的复位来初始化寄存器。输出选择器根据通过外部引脚提供的外部输入信号的电平值，选择其电平值设置为等于寄存器的寄存器值的信号和其电平值设置为与寄存器相反的信号并输出所选择的信号作为控制参数信号。当控制参数信号的电平值需要改变时，寄存器更新电路更新寄存器的寄存器值。

3. 发明申请

US20060023954A1 Image processing system 有权
标题翻译：图像处理系统
公开(公告)号：US20060023954A1
公开(公告)日：2006-02-02
申请号：US11010322
申请日：2004-12-14
申请人： Masanori Ishizuka , Tatsushi Otsuka , Takahiko Tahira
发明人： Masanori Ishizuka , Tatsushi Otsuka , Takahiko Tahira
IPC分类号： G06K9/36
CPC分类号： H04N19/423 , H04N19/16 , H04N19/17 , H04N19/186 , H04N19/33 , H04N19/503
摘要： In an image processing system, an image-input-processing unit divides an original image into portions so as to generate divided original images, and writes the divided original images in an encoder-side memory so that luminance data and chrominance data of each of the divided original images are stored in different storage areas. When predictive coding is performed, the encoding unit divides a reference image into portions so as to generate divided reference images which include information necessary for predictive coding of the divided original images, stores the divided reference images. The decoding unit divides and decodes an inputted encoded image so as to generate divided decoded-data sets, and writes the divided decoded-data sets in a decoder-side memory so that luminance data and chrominance data in each of the divided decoded-data sets are stored in different storage areas
摘要翻译：在图像处理系统中，图像输入处理单元将原始图像分割成部分，以便产生分割的原始图像，并将分割的原始图像写入编码器侧存储器中，使得每个的图像输入处理单元的亮度数据和色度数据分割的原始图像存储在不同的存储区域。当执行预测编码时，编码单元将参考图像分割成部分，以便生成包括分割原始图像的预测编码所需的信息的分割参考图像，存储划分的参考图像。解码单元对输入的编码图像进行分割和解码，生成分割后的解码数据组，并将分割后的解码数据组写入译码器侧的存储器，使每个分割的解码数据组中的亮度数据和色度数据存储在不同的存储区域

4. 发明授权

US07336834B2 Image processing system 有权
标题翻译：图像处理系统
公开(公告)号：US07336834B2
公开(公告)日：2008-02-26
申请号：US11010322
申请日：2004-12-14
申请人： Masanori Ishizuka , Tatsushi Otsuka , Takahiko Tahira
发明人： Masanori Ishizuka , Tatsushi Otsuka , Takahiko Tahira
IPC分类号： G06K9/36
CPC分类号： H04N19/423 , H04N19/16 , H04N19/17 , H04N19/186 , H04N19/33 , H04N19/503
摘要： In an image processing system, an image-input-processing unit divides an original image into portions so as to generate divided original images, and writes the divided original images in an encoder-side memory so that luminance data and chrominance data of each of the divided original images are stored in different storage areas. When predictive coding is performed, the encoding unit divides a reference image into portions so as to generate divided reference images which include information necessary for predictive coding of the divided original images, stores the divided reference images. The decoding unit divides and decodes an inputted encoded image so as to generate divided decoded-data sets, and writes the divided decoded-data sets in a decoder-side memory so that luminance data and chrominance data in each of the divided decoded-data sets are stored in different storage areas.
摘要翻译：在图像处理系统中，图像输入处理单元将原始图像划分为部分，以便产生分割的原始图像，并将分割的原始图像写入编码器侧存储器，使得每个的图像的亮度数据和色度数据分割的原始图像存储在不同的存储区域。当执行预测编码时，编码单元将参考图像分割成部分，以便生成包括分割原始图像的预测编码所需的信息的分割参考图像，存储划分的参考图像。解码单元对输入的编码图像进行分割和解码，生成分割后的解码数据组，并将分割后的解码数据组写入译码器侧的存储器，使每个分割的解码数据组中的亮度数据和色度数据存储在不同的存储区域。

5. 发明授权

US08015389B2 Memory device, memory controller and memory system 有权
标题翻译：内存设备，内存控制器和内存系统
公开(公告)号：US08015389B2
公开(公告)日：2011-09-06
申请号：US12000953
申请日：2007-12-19
申请人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G06F12/06
CPC分类号： G11C11/4087 , G09G5/393 , G09G5/395 , G11C8/12
摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.
摘要翻译：提供能够有效地访问二维排列数据的矩形区域的图像存储器，图像存储器系统和存储器控制器。存储装置具有：具有多个存储单元区域的存储单元阵列，每个存储单元区域由地址选择; 多个输入/输出端子; 以及设置在存储单元阵列和多个输入/输出端子之间的输入/输出单元。每个存储单元区域分别存储与多个输入/输出端子相对应的多个字节或位的数据，并且存储单元阵列和输入/输出单元访问存储在第一存储器中的多个字节或位基于与第一操作码相对应的字节或比特的输入地址和组合信息，与第一存储器单元相邻的第二存储器单元区域中的对应于输入地址的单位区域和与第一存储器单元相邻的第二存储单元区域中，在所访问的第一和第二存储器单元区域内的字节或比特，基于组合信息将多个字节或比特的组合与多个输入/输出终端相关联。

6. 发明授权

US07774577B2 Memory device, memory controller and memory system 有权
公开(公告)号：US07774577B2
公开(公告)日：2010-08-10
申请号：US12000952
申请日：2007-12-19
申请人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C8/12 , G06F12/04
CPC分类号： G11C11/4087 , G09G5/393 , G09G5/395 , G11C8/12
摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.

7. 发明申请

US20080043552A1 Integrated circuit 有权
标题翻译：集成电路
公开(公告)号：US20080043552A1
公开(公告)日：2008-02-21
申请号：US11785630
申请日：2007-04-19
申请人： Katsuya Ishikawa , Tatsushi Otsuka
发明人： Katsuya Ishikawa , Tatsushi Otsuka
IPC分类号： G11C7/00
CPC分类号： G11C29/14
摘要： An integrated circuit that enables a reduction in chip size and test time. This integrated circuit comprises an internal circuit; an external memory control circuit for inputting read data from an LSI tester by the use of a read command and for outputting write data to the LSI tester by the use of a write command; a test RAM including a read data storage section for storing the read data inputted from the LSI tester at a low speed and a write data storage section for storing the write data outputted from the control circuit; a test circuit for interpreting the read command and the write command issued by the external memory control circuit, for supplying, at the time of determining that the read data must be inputted to the external memory control circuit, the read data from the test RAM to the external memory control circuit at a high speed, and for supplying, at the time of determining that the write data is outputted from the external memory control circuit, the write data outputted from the external memory control circuit to the test RAM at a high speed; and a test circuit for outputting the write data stored in the test RAM to the LSI tester at a low speed.
摘要翻译：一种能够减少芯片尺寸和测试时间的集成电路。该集成电路包括内部电路; 外部存储器控制电路，用于通过使用读取命令从LSI测试器输入读取数据，并通过使用写入命令向LSI测试器输出写入数据; 测试RAM，包括用于存储从LSI测试仪输入的低速读取数据的读取数据存储部分和用于存储从控制电路输出的写入数据的写入数据存储部分; 用于解释由外部存储器控制电路发出的读取命令和写入命令的测试电路，用于在将读取的数据必须输入到外部存储器控制电路时将读取的数据从测试RAM提供给高速外部存储器控制电路，并且在确定从外部存储器控制电路输出写入数据时，将从外部存储器控制电路输出的写入数据高速地提供给测试RAM ; 以及用于以低速将存储在测试RAM中的写入数据输出到LSI测试器的测试电路。

8. 发明申请

US20060023788A1 Motion estimation and compensation device with motion vector correction based on vertical component values 审中-公开
标题翻译：基于垂直分量值的运动矢量校正运动估计和补偿装置
公开(公告)号：US20060023788A1
公开(公告)日：2006-02-02
申请号：US11000460
申请日：2004-12-01
申请人： Tatsushi Otsuka , Takahiko Tahira , Akihiro Yamori
发明人： Tatsushi Otsuka , Takahiko Tahira , Akihiro Yamori
IPC分类号： H04N11/02 , H04N11/04 , H04N7/12 , H04B1/66
CPC分类号： H04N19/186 , H04N19/112 , H04N19/51 , H04N19/56
摘要： A motion estimation and compensation device that avoids discrepancies in chrominance components which could be introduced in the process of motion vector estimation. The device has a motion vector estimator for finding motion vectors in given interlace-scanning chrominance-subsampled video signals. The estimator compares each candidate block in a reference picture with a target block in an original picture by using a sum of absolute differences (SAD) in luminance as similarity metric, chooses a best matching candidate block that minimizes the SAD, and determines its displacement relative to the target block. In this process, the estimator gives the SAD of each candidate block an offset determined from the vertical component of a corresponding motion vector, so as to avoid chrominance discrepancies. A motion compensator then produces a predicted picture using such motion vectors and calculates prediction error by subtracting the predicted picture from the original picture.
摘要翻译：一种运动估计和补偿装置，可以避免运动矢量估计过程中可能引入的色度分量差异。该装置具有运动矢量估计器，用于在给定的交错扫描色度子采样视频信号中找到运动矢量。估计器通过使用亮度中的绝对差（SAD）作为相似性度量，将参考图像中的每个候选块与原始图像中的目标块进行比较，选择使SAD最小化的最佳匹配候选块，并且确定其位移相对到目标块。在该处理中，估计器给出每个候选块的SAD从相应运动矢量的垂直分量确定的偏移量，以避免色度差异。然后，运动补偿器使用这种运动矢量产生预测图像，并通过从原始图像中减去预测图像来计算预测误差。

9. 发明授权

US06388671B1 Information processing apparatus and method for processing three-dimensional graphics using a second information processing unit for processing processed-related information 失效
标题翻译：用于处理处理相关信息的第二信息处理单元来处理三维图形的信息处理装置和方法
公开(公告)号：US06388671B1
公开(公告)日：2002-05-14
申请号：US08999759
申请日：1997-11-25
申请人： Hideki Yoshizawa , Tatsushi Otsuka , Shigeru Sasaki , Ritsuko Tatematsu
发明人： Hideki Yoshizawa , Tatsushi Otsuka , Shigeru Sasaki , Ritsuko Tatematsu
IPC分类号： G06F1580
CPC分类号： G06T1/20
摘要： An information processing apparatus includes a dedicated graphic hardware part dedicated to execution of a specific process function under a pipeline process scheme, and a microprogram execution part executing a process using a microprogram. When three-dimensional graphic information is processed, a process for determining endpoints is executed by the microprogram execution part, and an interpolation process started from an endpoint is executed by the dedicated graphic hardware part for each endpoint process. While the dedicated graphic hardware part is executing the interpolation process, the microprogram execution part is operated in parallel so as to execute the endpoint process for a next endpoint.
摘要翻译：信息处理装置包括专用于在流水线处理方案下执行特定处理功能的专用图形硬件部分，以及执行使用微程序的处理的微程序执行部。当处理三维图形信息时，由微程序执行部分执行确定端点的处理，并且由端点处理开始的插值处理由用于每个端点处理的专用图形硬件部件执行。当专用图形硬件部分正在执行插值处理时，微程序执行部分被并行操作，以对下一个端点执行端点处理。

10. 发明授权

US5715471A Parallel computer 失效
标题翻译：并行电脑
公开(公告)号：US5715471A
公开(公告)日：1998-02-03
申请号：US381399
申请日：1995-01-31
申请人： Tatsushi Otsuka , Hideki Yoshizawa , Katsuhito Fujimoto
发明人： Tatsushi Otsuka , Hideki Yoshizawa , Katsuhito Fujimoto
IPC分类号： G06F15/16 , G06F15/173 , G06F15/80 , G06F17/10 , G06F17/12 , G06F17/16
CPC分类号： G06F17/12
摘要： A parallel computer includes a sequence of adjacent nodes, with each node including at least first and second processing elements and each processing element including a memory. The nodes are sequentially added or replaced in a node order and the processing elements are sequentially connected to form a single ring data path. First matrix data elements are sequentially assigned to adjacent processing elements along the single ring data path and second matrix data element groups are sequentially assigned to processing elements in the node order. The first matrix data elements are then accumulated with the second matrix data element groups as the first matrix data elements are rotated along the single ring data path. Accordingly, accumulation results are maintained within the memories of the lowest order nodes such that the nodes may added or replaced without relocation of data.
摘要翻译：并行计算机包括相邻节点序列，每个节点至少包括第一和第二处理元件，每个处理元件包括存储器。以节点顺序顺序添加或替换节点，并且处理元件被顺序连接以形成单个环形数据路径。第一矩阵数据元素沿着单环数据路径顺序分配给相邻的处理元件，并且第二矩阵数据元素组被顺序地分配给节点顺序中的处理元件。随着第一矩阵数据元素沿着单环数据路径旋转，第一矩阵数据元素然后与第二矩阵数据元素组一起被累积。因此，积累结果保持在最低阶节点的存储器内，使得可以在不重新定位数据的情况下添加或替换节点。

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