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1. 发明授权

US06815259B2 Method of supporting a flexible substrate and method of manufacturing a semiconductor device 有权
标题翻译：支撑柔性基板的方法和制造半导体器件的方法
公开(公告)号：US06815259B2
公开(公告)日：2004-11-09
申请号：US09931717
申请日：2001-08-20
申请人： Hideaki Ninomiya , Hisao Morooka , Yoshihito Yamamoto , Kazuo Nishi
发明人： Hideaki Ninomiya , Hisao Morooka , Yoshihito Yamamoto , Kazuo Nishi
IPC分类号： H01L2150
CPC分类号： H01L21/6835 , H01L31/0392 , H01L31/03926 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A frame-shaped holding frame which has a small thermal expansion coefficient is used. When a complex member in which a metal material is impregnated in a ceramic material, which has a smaller thermal expansion coefficient than 10 ppm/° C., is used, a warp and a wrinkle are greatly decreased. In particular, in the case of a material with a thermal expansion coefficient of 6.5 ppm/° C. or smaller, the warp and the wrinkle are not caused. When the flexible substrate is adhered to the holding frame by an adhesive, an adhesion area may be obtained so that a sufficient strength is kept. Also, since the flexible substrate is adhered onto the upper surface of the holding frame, the thickness of the holding frame is independent on fixing of the substrate. The thickness may be set so that a mechanical strength is kept and the substrate is smoothly transferred.

2. 发明授权

US07845071B2 Method of manufacturing electronic part 有权
标题翻译：制造电子零件的方法
公开(公告)号：US07845071B2
公开(公告)日：2010-12-07
申请号：US11072989
申请日：2005-03-07
申请人： Hisao Morooka , Hideaki Ninomiya , Junichi Shimamura , Kazuo Nishi
发明人： Hisao Morooka , Hideaki Ninomiya , Junichi Shimamura , Kazuo Nishi
IPC分类号： H05K3/30
CPC分类号： H01L31/18 , H01L21/67132 , H05K1/0393 , H05K3/0058 , Y10T29/49117 , Y10T29/4913 , Y10T29/49131 , Y10T29/49144 , Y10T29/5193 , Y10T29/53174
摘要： The present invention provides a substrate holding method capable of contributing to improvement in performance of an electronic part. A plastic film is adhered to a holding frame by using an adhesive tape having a proper gas releasing characteristic such that total quantity of gas detected when analysis using gas chromatograph mass spectrometry (dynamic HS-GC-MS) is conducted under test conditions of 180° C. and 10 minutes is 100.5 μg/g or less in n-tetradecane. In the case where the plastic film held by the holding frame is subjected to a process of manufacturing an electronic part (for example, a solar battery), even when a process accompanying generation of heat during the manufacturing process (for example, a film forming process such as plasma CVD) is performed on the plastic film, a release amount of unnecessary gas released from the adhesive tape due to the influence of the heat is suppressed, so that deterioration in the performance of the electronic part caused by the unnecessary gas is suppressed.
摘要翻译：本发明提供能够有助于提高电子部件的性能的基板保持方法。通过使用具有适当的气体释放特性的粘合带将塑料膜粘附到保持框架上，使得在使用气相色谱质谱（动态HS-GC-MS）进行分析时检测到的气体总量在180°的测试条件下进行 C.正十四烷中10分钟为100.5μg/ g以下。在由保持框架保持的塑料膜经受制造电子部件（例如，太阳能电池）的处理的情况下，即使在制造过程中伴随发热的处理（例如，成膜在塑料膜上进行等离子体CVD等工序），能够抑制由于热量的影响而从粘合带释放的不需要的气体的释放量，不利气体导致的电子部件的性能下降被压制

3. 发明申请

US20050210666A1 Substrate holding method and method of manufacturing electronic part 有权
标题翻译：基板保持方法及其制造方法
公开(公告)号：US20050210666A1
公开(公告)日：2005-09-29
申请号：US11072989
申请日：2005-03-07
申请人： Hisao Morooka , Hideaki Ninomiya , Junichi Shimamura , Kazuo Nishi
发明人： Hisao Morooka , Hideaki Ninomiya , Junichi Shimamura , Kazuo Nishi
IPC分类号： C09J5/06 , B23P19/00 , C09J9/00 , C09J133/08 , H01L21/00 , H01L21/02 , H01L31/02 , H01L31/0236 , H01L31/04 , H01L31/18 , H05K1/00 , H05K3/00 , H05K13/00
CPC分类号： H01L31/18 , H01L21/67132 , H05K1/0393 , H05K3/0058 , Y10T29/49117 , Y10T29/4913 , Y10T29/49131 , Y10T29/49144 , Y10T29/5193 , Y10T29/53174
摘要： The present invention provides a substrate holding method capable of contributing to improvement in performance of an electronic part. A plastic film is adhered to a holding frame by using an adhesive tape having a proper gas releasing characteristic such that total quantity of gas detected when analysis using gas chromatograph mass spectrometry (dynamic HS-GC-MS) is conducted under test conditions of 180° C. and 10 minutes is 100.5 μg/g or less in n-tetradecane. In the case where the plastic film held by the holding frame is subjected to a process of manufacturing an electronic part (for example, a solar battery), even when a process accompanying generation of heat during the manufacturing process (for example, a film forming process such as plasma CVD) is performed on the plastic film, a release amount of unnecessary gas released from the adhesive tape due to the influence of the heat is suppressed, so that deterioration in the performance of the electronic part caused by the unnecessary gas is suppressed.
摘要翻译：本发明提供能够有助于提高电子部件的性能的基板保持方法。通过使用具有适当的气体释放特性的粘合带将塑料膜粘附到保持框架上，使得在使用气相色谱质谱（动态HS-GC-MS）进行分析时检测到的气体总量在180°的测试条件下进行 C.正十四烷中10分钟为100.5马克/克以下。在由保持框架保持的塑料膜经受制造电子部件（例如，太阳能电池）的处理的情况下，即使在制造过程中伴随发热的处理（例如，成膜在塑料膜上进行等离子体CVD等工序），能够抑制由于热量的影响而从粘合带释放的不需要的气体的释放量，不利气体导致的电子部件的性能下降被压制

4. 发明授权

US06225552B1 Planar solar cell array and production method of the same 失效
标题翻译：平面太阳能电池阵列及其制作方法相同
公开(公告)号：US06225552B1
公开(公告)日：2001-05-01
申请号：US09029611
申请日：1998-03-11
申请人： Kazuo Nishi , Makoto Hosokawa , Yukihiro Isobe , Hideaki Ninomiya
发明人： Kazuo Nishi , Makoto Hosokawa , Yukihiro Isobe , Hideaki Ninomiya
IPC分类号： H01L3100
CPC分类号： H01L31/046 , G04C10/02 , H01L31/0463 , H01L31/0465 , Y02E10/50
摘要： The invention relates to a desired shaped plane type solar cell. The solar cell includes a plurality of photoelectric conversion devices formed by dividing the plane, a plurality of conductive paths for connecting each of the photoelectric conversion devices to each other in series, the conductive path being provided adjacent to the plurality of photoelectric conversion devices, and two drawing electrodes exposed on an opposite surface to a light irradiated surface, the electrodes being connected to two photoelectric conversion devices on both ends of the photoelectric conversion device connected in series.
摘要翻译：本发明涉及一种所需的成形平面型太阳能电池。太阳能电池包括多个光电转换装置，其通过将平面划分成多个导电路径，用于将每个光电转换装置彼此串联连接，导电路径设置成与多个光电转换装置相邻，以及两个绘制电极在与光照射表面相反的表面上暴露，电极连接到串联连接的光电转换装置两端的两个光电转换装置。

5. 发明授权

US07800168B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US07800168B2
公开(公告)日：2010-09-21
申请号：US11833401
申请日：2007-08-03
申请人： Tsuneo Ogura , Tomoki Inoue , Hideaki Ninomiya , Koichi Sugiyama
发明人： Tsuneo Ogura , Tomoki Inoue , Hideaki Ninomiya , Koichi Sugiyama
IPC分类号： H01L29/76
CPC分类号： H01L29/1095 , H01L29/0619 , H01L29/0692 , H01L29/0696 , H01L29/083 , H01L29/0834 , H01L29/7394 , H01L29/7397
摘要： A semiconductor device includes a base layer of a first conductivity type, a barrier layer of a first conductivity type formed on the base layer, a trench formed from the surface of the barrier layer to such a depth as to reach a region in the vicinity of an interface between the barrier layer and the base layer, a gate electrode formed in the trench via a gate insulating film, a contact layer of a second conductivity type selectively formed in a surface portion of the barrier layer, a source layer of the first conductivity type selectively formed in the surface portion of the barrier layer so as to contact the contact layer and a side wall of the gate insulating film in the trench, and a first main electrode formed so as to contact the contact layer and the source layer.
摘要翻译：半导体器件包括第一导电类型的基底层，形成在基底层上的第一导电类型的阻挡层，从阻挡层的表面形成的沟槽到达达到阻挡层和基底层之间的界面，通过栅极绝缘膜形成在沟槽中的栅极电极，选择性地形成在阻挡层的表面部分中的第二导电类型的接触层，第一导电性的源极层形成在所述阻挡层的表面部分中以与所述沟槽中的所述接触层和所述栅极绝缘膜的侧壁接触的第一主电极以及与所述接触层和所述源极层接触的第一主电极。

6. 发明授权

US07319257B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US07319257B2
公开(公告)日：2008-01-15
申请号：US11626141
申请日：2007-01-23
申请人： Masakazu Yamaguchi , Hideaki Ninomiya , Ichiro Omura , Tomoki Inoue
发明人： Masakazu Yamaguchi , Hideaki Ninomiya , Ichiro Omura , Tomoki Inoue
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/0696 , H01L29/0619 , H01L29/0839 , H01L29/407 , H01L29/4236 , H01L29/66348 , H01L29/7394 , H01L29/7395 , H01L29/7397
摘要： A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.
摘要翻译：功率半导体器件包括在距离第二导电类型的集电极层的位置处间隔设置在第一导电类型的第一基极层中的沟槽，以分隔主单元和虚设单元。在主电池中，设置第二导电类型的第二基极层和第一导电类型的发射极层。在虚拟电池中设置第二导电类型的缓冲层。栅电极通过栅极绝缘膜设置在与主电池相邻的沟槽中。具有无限大电阻值的缓冲电阻器插入在缓冲层和发射极之间。虚设电池具有抑制结构，以减少第二导电类型的载流子从集电极层流入和积聚在缓冲层中。

7. 发明申请

US20070114570A1 POWER SEMICONDUCTOR DEVICE 有权
标题翻译：功率半导体器件
公开(公告)号：US20070114570A1
公开(公告)日：2007-05-24
申请号：US11626141
申请日：2007-01-23
申请人： Masakazu Yamaguchi , Hideaki Ninomiya , Ichiro Omura , Tomoki Inoue
发明人： Masakazu Yamaguchi , Hideaki Ninomiya , Ichiro Omura , Tomoki Inoue
IPC分类号： H01L31/00
CPC分类号： H01L29/0696 , H01L29/0619 , H01L29/0839 , H01L29/407 , H01L29/4236 , H01L29/66348 , H01L29/7394 , H01L29/7395 , H01L29/7397
摘要： A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.
摘要翻译：功率半导体器件包括在距离第二导电类型的集电极层的位置处间隔设置在第一导电类型的第一基极层中的沟槽，以分隔主单元和虚设单元。在主电池中，设置第二导电类型的第二基极层和第一导电类型的发射极层。在虚拟电池中设置第二导电类型的缓冲层。栅电极通过栅极绝缘膜设置在与主电池相邻的沟槽中。具有无限大电阻值的缓冲电阻器插入在缓冲层和发射极之间。虚设电池具有抑制结构，以减少第二导电类型的载流子从集电极层流入和积聚在缓冲层中。

8. 发明申请

US20060113613A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20060113613A1
公开(公告)日：2006-06-01
申请号：US11331160
申请日：2006-01-13
申请人： Hideaki Ninomiya , Tomoki Inoue
发明人： Hideaki Ninomiya , Tomoki Inoue
IPC分类号： H01L29/76
CPC分类号： H01L29/404 , H01L29/0619 , H01L29/0692 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device disclosed herein comprises: a first base region which is of a first conductivity type; a second base region which is of a second conductivity type and which is selectively formed on a major surface of the first base region; a stopper region which is of a first conductivity type and which is formed on the major surface of the first base region, the stopper region being a predetermined distance away from the second base region and surrounding the second base region; and a ring region which is of a second conductivity type which is formed on the major surface of the first base region between the second base region and the stopper region, the ring region being spirally around the second base region and electrically connected to the second base region and the stopper region.
摘要翻译：本文公开的半导体器件包括：第一导电类型的第一基极区; 第二基极区域，其具有第二导电类型并且选择性地形成在所述第一基极区域的主表面上; 阻挡区域，其具有第一导电类型并且形成在第一基底区域的主表面上，止挡区域距第二基底区域预定距离并且围绕第二基底区域; 以及形成在所述第二基极区域和所述阻挡区域之间的所述第一基底区域的主表面上的第二导电类型的环形区域，所述环形区域围绕所述第二基极区域螺旋地且与所述第二基底区域电连接区域和止挡区域。

9. 发明申请

US20050189137A1 Multilayer ceramic substrate and its production method 失效
标题翻译：多层陶瓷基板及其制作方法
公开(公告)号：US20050189137A1
公开(公告)日：2005-09-01
申请号：US11059585
申请日：2005-02-17
申请人： Kiyoshi Hatanaka , Haruo Nishino , Hideaki Ninomiya
发明人： Kiyoshi Hatanaka , Haruo Nishino , Hideaki Ninomiya
IPC分类号： C04B35/622 , C04B35/00 , C04B35/495 , H01G4/06 , H01G4/20 , H05K1/03 , H05K1/09 , H05K1/16 , H05K3/00 , H05K3/46
CPC分类号： H05K1/162 , H05K1/0306 , H05K3/005 , H05K3/4611 , H05K3/4629 , H05K2201/0187 , Y10T29/49155 , Y10T29/49162 , Y10T29/49163 , Y10T29/49165 , Y10T156/1056 , Y10T156/1057 , Y10T428/24322
摘要： An object of the invention is to connect different dielectrics electrically to each other in the direction of main surface of a sheet in a multilayer ceramic substrate and to increase the degree of flexibility in design and make the multilayer ceramic substrate compact in size. A multilayer ceramic substrate in accordance with the invention is formed of a plurality of laminated ceramic substrates including such a composite ceramic substrate of different materials that is made by inserting the second ceramic substrate in a pounched-out portion made in the first ceramic substrate and by planarizing its top and bottom surfaces, wherein a conductive layer is formed in a portion across a boundary between the first ceramic substrate and the second ceramic substrate of the interface of the composite ceramic substrate of different materials.
摘要翻译：本发明的目的是在多层陶瓷基板中的片材的主表面的方向上彼此电连接不同的电介质，并且增加设计的柔性程度，并使多层陶瓷基板的尺寸更小。根据本发明的多层陶瓷基板由多个层叠陶瓷基板形成，该多个层叠陶瓷基板包括这样的不同材料的复合陶瓷基板，该复合陶瓷基板是通过将第二陶瓷基板插入在第一陶瓷基板中形成的突出部分而形成的，平面化其顶表面和底表面，其中导电层形成在穿过不同材料的复合陶瓷衬底的界面的第一陶瓷衬底和第二陶瓷衬底之间的边界的部分中。

10. 发明申请

US20050161768A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050161768A1
公开(公告)日：2005-07-28
申请号：US11016810
申请日：2004-12-21
申请人： Koichi Sugiyama , Tomoki Inoue , Hideaki Ninomiya , Masakazu Yamaguchi
发明人： Koichi Sugiyama , Tomoki Inoue , Hideaki Ninomiya , Masakazu Yamaguchi
IPC分类号： H01L29/78 , H01L27/04 , H01L27/088 , H01L29/423 , H01L29/739 , H01L31/113
CPC分类号： H01L29/7397 , H01L29/4232 , H01L29/42372 , H01L29/7395
摘要： A semiconductor device comprises a first base layer of a first conductive type which has a first surface and a second surface; a second base layer of a second conductive type which is formed on the first surface; first and second gate electrodes which are formed by embedding an electrically conductive material into a plurality of trenches via gate insulating films, the plurality of trenches being formed such that bottoms of the trenches reach the first base layer; source layers of the first conductive type which are formed on a surface area of the second base layer so as to be adjacent to both side walls of the trench provided with the first gate electrode and one side wall of the trench provided with the second gate electrode, respectively; an emitter layer of the second conductive type which is formed on the second surface; emitter electrodes which are formed on the second base layer and the source layers; a collector electrode which is formed on the emitter layer; and first and second terminals which are electrically connected to the first and second gate electrodes, respectively.
摘要翻译：半导体器件包括具有第一表面和第二表面的第一导电类型的第一基底层; 形成在第一表面上的第二导电类型的第二基层; 通过经由栅极绝缘膜将导电材料嵌入多个沟槽而形成的第一和第二栅电极，所述多个沟槽形成为使得沟槽的底部到达第一基底层; 源极层，其形成在第二基极层的表面区域上，以与设置有第一栅电极的沟槽的两个侧壁相邻，并且设置有第二栅电极的沟槽的一个侧壁，分别; 形成在第二表面上的第二导电类型的发射极层; 在第二基极层和源极层上形成的发射极; 在发射极层上形成的集电极; 以及分别电连接到第一和第二栅电极的第一和第二端子。

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