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1. 发明授权

US06211530B1 Sparse-carrier devices and method of fabrication 失效
标题翻译：稀疏载波器件及其制造方法
公开(公告)号：US06211530B1
公开(公告)日：2001-04-03
申请号：US09097026
申请日：1998-06-12
申请人： Herbert Goronkin , Raymond K. Tsui , Ruth Y. Zhang , Kumar Shiralagi
发明人： Herbert Goronkin , Raymond K. Tsui , Ruth Y. Zhang , Kumar Shiralagi
IPC分类号： H01L2906
CPC分类号： B82Y10/00 , H01L21/02395 , H01L21/02463 , H01L21/02494 , H01L21/02546 , H01L21/02601 , H01L21/0262 , H01L21/02642 , H01L29/045 , H01L29/127 , H01L29/7613
摘要： A sparse-carrier device includes a crystal structure with a crystallographic facet having contacts at opposite ends. Quantum dots are formed in first and second rows on the facet approximately one quantum dot wide and a plurality of quantum dots long, the quantum dots in the first row being separated from each other by a first distance smaller than a second distance between the quantum dots in the first row and adjacent quantum dots in a second row. The first distance is small enough to allow carrier tunneling between adjacent quantum dots and the second distance is large enough to substantially prevent tunneling between adjacent quantum dots and small enough to allow Coulombic interaction between adjacent quantum dots. Electrical contacts are formed at opposite ends of the rows to allow tunneling of carriers into and out of quantum dots in the first and second rows.
摘要翻译：稀疏载体器件包括晶体结构，其晶体结构在相对端具有接触。量子点形成在小平面上的第一和第二行中，大约一个量子点宽，并且多个量子点长，第一行中的量子点彼此间隔开小于量子点之间的第二距离的第一距离在第二行中的第一行和相邻的量子点。第一距离足够小以允许相邻量子点之间的载流子隧穿，并且第二距离足够大以基本上防止相邻量子点之间的隧道，并且足够小以允许相邻量子点之间的库仑相互作用。电触点形成在行的相对端处，以允许载流子在第一行和第二行中将量子点隧穿。

2. 发明授权

US5591666A Semiconductor device and method of fabrication 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US5591666A
公开(公告)日：1997-01-07
申请号：US511776
申请日：1995-08-07
申请人： Kumar Shiralagi , Raymond K. Tsui , Herbert Goronkin
发明人： Kumar Shiralagi , Raymond K. Tsui , Herbert Goronkin
IPC分类号： H01L21/205 , H01L21/20 , H01L29/88
CPC分类号： H01L21/02395 , H01L21/02546 , H01L21/0262 , H01L21/02639 , Y10S117/902 , Y10S117/913 , Y10S438/973
摘要： A method of fabricating semiconductor devices including defining an area on the surface of a substrate, selectively growing, on the area, a crystalline material with at least one defined crystallographic facet, and selectively growing a semiconductor device on the crystallographic facet. In a second embodiment, an area is defined on the surface of a substrate and chemical beam epitaxy is used to selectively grow, on the area, a layer of indium arsenide with at least one defined crystallographic facet.
摘要翻译：一种制造半导体器件的方法，包括限定衬底的表面上的区域，在该区域上选择性地生长具有至少一个限定的结晶小面的晶体材料，以及在晶面上选择性地生长半导体器件。在第二实施例中，在衬底的表面上限定一个区域，并且使用化学束外延在该区域上选择性地在至少一个限定的晶面上生长砷化铟层。

3. 发明授权

US06452205B2 Sparse-carrier devices and method of fabrication 失效
标题翻译：稀疏载波器件及其制造方法
公开(公告)号：US06452205B2
公开(公告)日：2002-09-17
申请号：US09819438
申请日：2001-03-29
申请人： Raymond K. Tsui , Kumar Shiralagi , Herbert Goronkin
发明人： Raymond K. Tsui , Kumar Shiralagi , Herbert Goronkin
IPC分类号： H01L2906
CPC分类号： B82Y10/00 , H01L29/045 , H01L29/127
摘要： A sparse-carrier device including a crystal structure (10) formed of a first material and having a crystallographic facet (26) with a width (w) and a length and quantum dots (30) formed of a second material and positioned in at least one row on the crystallographic facet (26). The at least one row of quantum dots (30) extends along the length of the crystallographic facet (26) and is at least one quantum dot (30) wide (w) and a plurality of quantum dots long. The number of quantum dot rows determined by the width (w) of the crystallographic facet (26). The row of quantum dots (30) form a building block for circuits based on sparse or single electron devices.
摘要翻译：一种稀疏载体器件，包括由第一材料形成并具有宽度（w）和长度的晶体结构（26）和由第二材料形成并且至少位于第二材料的量子点（30）的晶体结构（10）在晶面上有一排（26）。至少一行量子点（30）沿着结晶小面（26）的长度延伸，并且是至少一个量子点（30）宽（w）和多个量子点长。由晶面（26）的宽度（w）确定的量子点行数。量子点行（30）形成基于稀疏或单电子器件的电路的构建块。

4. 发明授权

US5943574A Method of fabricating 3D multilayer semiconductor circuits 失效
标题翻译：制造3D多层半导体电路的方法
公开(公告)号：US5943574A
公开(公告)日：1999-08-24
申请号：US27915
申请日：1998-02-23
申请人： Saied N. Tehrani , Kumar Shiralagi , Herbert Goronkin
发明人： Saied N. Tehrani , Kumar Shiralagi , Herbert Goronkin
IPC分类号： H01L21/336 , H01L21/768 , H01L27/06 , H01L27/092 , H01L29/786
CPC分类号： H01L29/6675 , H01L21/76838 , H01L27/0688 , H01L27/0922 , H01L29/78642
摘要： A method of fabricating 3D semiconductor circuits including providing a conductive layer with doped polysilicon thereon patterned and annealed to form first single grain polysilicon terminals of semiconductor devices. Insulated gate contacts are spaced vertically from the terminals so as to define vertical vias and polysilicon is deposited in the vias to form conduction channels. An upper portion of the polysilicon in the vias is doped to form second terminals for the semiconductor devices, and the polysilicon is annealed to convert it to single grain polysilicon. A second electrically conductive layer is deposited and patterned on the second terminal to define second terminal contacts of the semiconductor devices.
摘要翻译：一种制造3D半导体电路的方法，包括向其上形成有导电层的掺杂多晶硅进行图案化和退火，以形成半导体器件的第一单晶多晶硅端子。绝缘栅极触点与端子垂直间隔开，以便限定垂直通孔，并且多孔沉积在通孔中以形成传导通道。通孔中的多晶硅的上部被掺杂以形成用于半导体器件的第二端子，并且将多晶硅退火以将其转换成单晶粒多晶硅。在第二端子上沉积和图案化第二导电层以限定半导体器件的第二端子触点。

5. 发明授权

US5629215A Method of fabricating and contacting ultra-small three terminal semiconductor devices 失效
标题翻译：制造和接触超小型三端子半导体器件的方法
公开(公告)号：US5629215A
公开(公告)日：1997-05-13
申请号：US609706
申请日：1996-03-01
申请人： Herbert Goronkin , Martin Walther , Raymond K. Tsui
发明人： Herbert Goronkin , Martin Walther , Raymond K. Tsui
IPC分类号： H01L21/334 , H01L29/737 , H01L49/00
CPC分类号： H01L29/66939 , H01L29/7376 , Y10S438/979
摘要： Ultra-small three terminal semiconductor devices and a method of fabrication including patterning the planar surface of a substrate and a control layer to form a first and second pattern edge and consecutively forming a plurality of layers of semiconductor material in overlying relationship to the pattern edges so that a discontinuity is produced in the layers and a first layer on one side of the pattern edge is aligned with and in electrical contact with a different layer on the other side of the pattern edge.
摘要翻译：超小型三端子半导体器件及其制造方法，包括对衬底和控制层的平坦表面进行图案化以形成第一和第二图案边缘，并以与图案边缘重叠的关系连续地形成多层半导体材料。在层中产生不连续性，并且图案边缘的一侧上的第一层与图案边缘的另一侧上的不同层对准并与其接触。

6. 发明授权

US5280180A Interconnect structure for coupling semiconductor regions and method for making 失效
标题翻译：用于耦合半导体区域的互连结构和制造方法
公开(公告)号：US5280180A
公开(公告)日：1994-01-18
申请号：US932116
申请日：1992-08-19
申请人： Herbert Goronkin , Jun Shen , Saied Tehrani , Raymond K. Tsui , X. Theodore Zhu
发明人： Herbert Goronkin , Jun Shen , Saied Tehrani , Raymond K. Tsui , X. Theodore Zhu
IPC分类号： H01L21/20 , H01L23/535 , H01L29/06 , H01L29/80 , H01L29/161 , H01L29/205
CPC分类号： H01L23/535 , H01L2924/0002
摘要： A semiconductor device having a lateral interconnect or via formed by quantum well comprising a semiconductor material is provided. The lateral interconnect (17, 18, 19) formed by a quantum well comprising a first semiconductor material composition. A first semiconductor region (11, 12, 13) comprising a second material type is formed adjacent to the lateral interconnect (17, 18, 19). A second semiconductor region (23, 24, 26) comprising the second material type is adjacent to the lateral interconnect (17, 18, 19) so that the lateral interconnect (17, 18, 19) separates the first (11, 12, 13) and second (23, 24, 26) semiconductor regions. The first (17, 18, 19) and second (23, 24, 26) semiconductor regions have a first quantized energy level that is substantially equal. The lateral interconnect (17, 18, 19) has a first quantized energy level capable of alignment with the quantized energy levels of the first (11, 12, 13) and second (23, 24, 26) semiconductor regions.
摘要翻译：提供了具有由包括半导体材料的量子阱形成的横向互连或通孔的半导体器件。由包括第一半导体材料组合物的量子阱形成的横向互连（17,18,19）。包括第二材料类型的第一半导体区域（11,12,13）形成为与横向互连（17,18,19）相邻。包括第二材料类型的第二半导体区域（23,24,26）与横向互连（17,18,19）相邻，使得横向互连（17,18,19）将第一（11,12,13））和第二（23,24,26）个半导体区域。第一（17,18,19）和第二（23,24,26）半导体区域具有基本相等的第一量化能级。横向互连（17,18,19）具有能够与第一（11,12,13）和第二（23,24,26）半导体区域的量化能级对准的第一量化能级。

7. 发明授权

US5942952A VCO with multiple negative differential resistance devices 失效
标题翻译： VCO具有多个负差分电阻器件
公开(公告)号：US5942952A
公开(公告)日：1999-08-24
申请号：US903081
申请日：1997-07-30
申请人： Vijay K. Nair , Nada El-Zein , Kumar Shiralagi , George N. Maracas , Herbert Goronkin
发明人： Vijay K. Nair , Nada El-Zein , Kumar Shiralagi , George N. Maracas , Herbert Goronkin
IPC分类号： H01L27/06 , H01L29/88 , H03B1/00 , H03B7/06 , H03B7/14
CPC分类号： H03B7/06 , H01L27/0605 , H01L29/882 , H03B2200/0062 , H03B2201/02 , H03B7/143
摘要： A VCO includes a transistor having a plurality of negative differential resistance devices coupled in series to the source terminal of the transistor, with each of the devices having a negative differential resistance operating region. Biasing circuits are coupled to the drain and gate terminals along with operating voltages which set the oscillator to operating in a negative differential resistance region of at least one of the negative differential resistance devices so that oscillations of a selected frequency are produced at an output terminal. The transistor, the plurality of N devices, the DC biasing circuits, and the operating voltages are connected so that the oscillator negative differential resistance operating region is greater than N times as wide as each of the device negative differential operating regions individually.
摘要翻译： VCO包括具有与晶体管的源极端子串联耦合的多个负差分电阻器件的晶体管，其中每个器件具有负的差分电阻工作区域。偏置电路耦合到漏极和栅极端子以及操作电压，其工作电压将振荡器设置为在负差分电阻器件中的至少一个的负差分电阻区域中工作，使得在输出端子处产生选定频率的振荡。连接晶体管，多个N器件，DC偏置电路和工作电压，使得振荡器负差分电阻工作区域分别大于每个器件负差分工作区域的N倍。

8. 发明授权

US5756154A Masking methods during semiconductor device fabrication 失效
标题翻译：半导体器件制造期间的掩模方法
公开(公告)号：US5756154A
公开(公告)日：1998-05-26
申请号：US583329
申请日：1996-01-05
申请人： Kumar Shiralagi , Raymond Tsui , Herbert Goronkin
发明人： Kumar Shiralagi , Raymond Tsui , Herbert Goronkin
IPC分类号： H01L21/316 , H01L21/20 , B05D1/32 , B05D3/00 , C08J7/18
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02639
摘要： A method of masking surfaces during fabrication of semiconductor devices is disclosed, which includes providing a substrate, and in a preferred embodiment a silicon substrate. The surface is hydrogen terminated (or hydrogenated) and a metal mask is positioned on the surface so as to define a growth area and an unmasked portion on the surface. Ozone is generated at the surface, at least in the unmasked area, by exposing the surface to a light having a wavelength approximately 185 nm (an oxygen absorbing peak), so as to grow an oxide film on the unmasked portion of the surface. The metal mask is removed and the oxide film then serves as a mask for further operations and can be easily removed in situ by heating.
摘要翻译：公开了一种在制造半导体器件期间掩蔽表面的方法，其包括提供衬底，并且在优选实施例中为硅衬底。表面是氢封端（或氢化），并且金属掩模位于表面上，以便在表面上限定生长区域和未掩模部分。通过将表面暴露于波长约185nm的光（氧吸收峰），至少在未掩模的区域中，在表面产生臭氧，以便在表面的未掩模部分上生长氧化膜。除去金属掩模，然后氧化膜用作进一步操作的掩模，并且可以通过加热容易地原位除去。

9. 发明授权

US5748519A Method of selecting a memory cell in a magnetic random access memory device 失效
标题翻译：选择磁性随机存取存储器件中的存储单元的方法
公开(公告)号：US5748519A
公开(公告)日：1998-05-05
申请号：US766637
申请日：1996-12-13
申请人： Saied N. Tehrani , Herbert Goronkin
发明人： Saied N. Tehrani , Herbert Goronkin
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L21/78
CPC分类号： G11C11/15
摘要： Improved methods for selecting memory cells in magnetic random access memory (MRAM) are provided. Whenever a state in a memory cell is sensed, a MRAM requires to adjust an output of comparator to a zero voltage (auto-zeroing step) before the content of memory cell is detected. This invention sequentially accesses memory cells 29-30 once sense line 25 is selected and auto-zeroed. Accordingly, a higher speed operation is attained because the invention does not require an auto-zeroing step every sensing a memory cell.
摘要翻译：提供了用于选择磁随机存取存储器（MRAM）中的存储单元的改进方法。每当检测到存储单元中的状态时，MRAM需要在检测到存储器单元的内容之前将比较器的输出调整为零电压（自动调零步骤）。一旦感测线25被选择并自动归零，本发明顺序地访问存储器单元29-30。因此，由于本发明不需要每次感测存储单元的自动归零步骤，所以实现了更高的速度操作。

10. 发明授权

US5659179A Ultra-small semiconductor devices having patterned edge planar surfaces 失效
标题翻译：具有图案化边缘平坦表面的超小型半导体器件
公开(公告)号：US5659179A
公开(公告)日：1997-08-19
申请号：US399809
申请日：1995-03-07
申请人： Herbert Goronkin , Saied N. Tehrani , Martin Walther , Raymond Tsui
发明人： Herbert Goronkin , Saied N. Tehrani , Martin Walther , Raymond Tsui
IPC分类号： H01L29/06 , H01L21/329 , H01L27/06 , H01L29/88
CPC分类号： H01L29/66219 , H01L27/0605 , H01L29/882
摘要： Ultra-small semiconductor devices and a method of fabrication including patterning the planar surface of a substrate to form a pattern edge (e.g. a mesa) and consecutively forming a plurality of layers of semiconductor material in overlying relationship to the pattern edge so that a discontinuity is produced in the layers and a first layer on one side of the pattern edge is aligned with and in electrical contact with a different layer on the other side of the pattern edge.
摘要翻译：超小型半导体器件和制造方法包括图案化衬底的平坦表面以形成图案边缘（例如台面）并且以与图案边缘重叠的关系连续地形成多个半导体材料层，使得不连续性为在图案边缘的一侧上产生的层和第一层与图案边缘的另一侧上的不同层对准并与之接触。

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