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1. 发明授权

US06265329B1 Quantum deposition distribution control 失效
标题翻译：量子沉积分布控制
公开(公告)号：US06265329B1
公开(公告)日：2001-07-24
申请号：US09036947
申请日：1998-03-09
申请人： Kumar Shiralagi , Raymond K. Tsui
发明人： Kumar Shiralagi , Raymond K. Tsui
IPC分类号： H01L21203
CPC分类号： B82Y10/00 , H01L21/02395 , H01L21/02546 , H01L21/02603 , H01L21/02639 , H01L29/127 , Y10S438/962
摘要： A sparse-carrier device comprising a crystal structure formed of a first material and including a crystallographic facet having a length, a first width and a second width, and quantum dots formed of a second material and positioned on the crystallographic facet, the quantum dots extending along the length of the crystallographic facet in a first distribution pattern along the first width and a second distribution pattern along the second width.
摘要翻译：一种稀疏载体器件，包括由第一材料形成并包括具有长度，第一宽度和第二宽度的晶面的晶体结构以及由第二材料形成并位于晶面上的量子点，所述量子点延伸沿着沿第一宽度的第一分布图案中的结晶小面的长度和沿着第二宽度的第二分布图案。

2. 发明授权

US5759880A Resistless methods of fabricating FETs 失效
标题翻译：无阻抗制造FET的方法
公开(公告)号：US5759880A
公开(公告)日：1998-06-02
申请号：US775908
申请日：1997-01-02
申请人： Kumar Shiralagi , Raymond K. Tsui
发明人： Kumar Shiralagi , Raymond K. Tsui
IPC分类号： H01L21/033 , H01L21/335 , H01L21/338
CPC分类号： H01L29/66462 , H01L21/0335
摘要： A method of fabricating semiconductor devices including forming a plurality of layers of semiconductor material on the surface of a substrate, forming a mask without using a resist on the layers which can be disassociated in-situ, removing an unmasked portion of the layers to form a semiconductor device with a gate region and opposed exposed source and drain surfaces, selectively growing source and drain contact regions on the exposed source and drain surfaces respectively, the contact regions defining opposed sidewalls adjacent the gate region, disassociating the mask, forming sidewall spacers on the sidewalls, forming a metal contact on the source, drain and gate regions with the spacers preventing intercontact therebetween, and depositing a passivating layer over the semiconductor device, with all of the previous steps being performed in-situ in a modular equipment cluster.
摘要翻译：一种制造半导体器件的方法，包括在衬底的表面上形成多个半导体材料层，形成掩模，而不在可以原位解离的层上使用抗蚀剂，除去层的未掩模部分以形成具有栅极区域和相对的暴露的源极和漏极表面的半导体器件，分别在暴露的源极和漏极表面上选择性地增长源极和漏极接触区域，接触区域限定与栅极区域相邻的相对侧壁，使掩模分离，在其上形成侧壁间隔物侧壁，在源极，漏极和栅极区域上形成金属接触，其中间隔物防止它们之间的相互接触，并且在半导体器件上沉积钝化层，其中所有先前的步骤在模块化设备集群中原位执行。

3. 发明授权

US5629215A Method of fabricating and contacting ultra-small three terminal semiconductor devices 失效
标题翻译：制造和接触超小型三端子半导体器件的方法
公开(公告)号：US5629215A
公开(公告)日：1997-05-13
申请号：US609706
申请日：1996-03-01
申请人： Herbert Goronkin , Martin Walther , Raymond K. Tsui
发明人： Herbert Goronkin , Martin Walther , Raymond K. Tsui
IPC分类号： H01L21/334 , H01L29/737 , H01L49/00
CPC分类号： H01L29/66939 , H01L29/7376 , Y10S438/979
摘要： Ultra-small three terminal semiconductor devices and a method of fabrication including patterning the planar surface of a substrate and a control layer to form a first and second pattern edge and consecutively forming a plurality of layers of semiconductor material in overlying relationship to the pattern edges so that a discontinuity is produced in the layers and a first layer on one side of the pattern edge is aligned with and in electrical contact with a different layer on the other side of the pattern edge.
摘要翻译：超小型三端子半导体器件及其制造方法，包括对衬底和控制层的平坦表面进行图案化以形成第一和第二图案边缘，并以与图案边缘重叠的关系连续地形成多层半导体材料。在层中产生不连续性，并且图案边缘的一侧上的第一层与图案边缘的另一侧上的不同层对准并与其接触。

4. 发明授权

US5371038A Method of forming a quantum multi-function semiconductor device 失效
标题翻译：形成量子多功能半导体器件的方法
公开(公告)号：US5371038A
公开(公告)日：1994-12-06
申请号：US139180
申请日：1993-10-21
申请人： Raymond K. Tsui
发明人： Raymond K. Tsui
IPC分类号： H01L29/06 , H01L21/20 , H01L21/334 , H01L29/66 , H01L29/76
CPC分类号： H01L29/66931 , H01L21/02392 , H01L21/02395 , H01L21/02463 , H01L21/02466 , H01L21/02546 , H01L21/02549 , H01L21/02639 , H01L21/02647 , H01L29/7606 , Y10S438/908
摘要： The present invention is a method of forming a quantum multi-function semiconductor device. In the method of the present invention, an insulating layer (12) is formed on a semiconductor substrate (11). An opening (14) is formed in the insulating layer (12), and a channel region (15) is formed in the opening (14). A channel layer (21) is formed over the channel region (15). An opening (23) is formed through the channel layer (21) such that a portion of the opening is over a portion of the channel region (15). A source electrode (28) is formed to contact a channel layer (17) of the channel region (15), a drain electrode (29) is formed to contact the channel layer (21), and a gate electrode (31) is formed to contact the second barrier layer (27).
摘要翻译：本发明是形成量子多功能半导体器件的方法。在本发明的方法中，在半导体衬底（11）上形成绝缘层（12）。在所述绝缘层（12）中形成开口（14），并且在所述开口（14）中形成沟道区域（15）。沟道层（21）形成在沟道区域（15）上。通过通道层（21）形成开口（23），使得开口的一部分在通道区域（15）的一部分之上。源电极（28）形成为与沟道区（15）的沟道层（17）接触，形成漏电极（29）与沟道层（21）接触，形成栅电极以接触第二阻挡层（27）。

5. 发明授权

US5075744A GaAs heterostructure having a GaAs.sub.y P.sub.1-y stress-compensating layer 失效
标题翻译： GaAs异质结构具有GaAsyP1-y应力补偿层
公开(公告)号：US5075744A
公开(公告)日：1991-12-24
申请号：US620819
申请日：1990-12-03
申请人： Raymond K. Tsui
发明人： Raymond K. Tsui
IPC分类号： C30B23/08 , C30B29/40 , H01L21/20 , H01L21/338 , H01L29/778 , H01L29/812
CPC分类号： H01L29/7783
摘要： A GaAs heterostructure is formed with a GaAs.sub.y P.sub.1-y stress-compensating layer. The heterostructure is comprised of a GaAs substrate and GaAs.sub.y P.sub.1-y stress-compensating layer formed on the GaAs substrate. The stress-compensating layer has a lattice constant less than the lattice constant of the GaAs substrate. A channel layer formed on the stress-compensating layer, has a lattice constant greater than the lattice constant of the GaAs substrate. Thus, a pseudomorphic heterostructure may be formed, with the optimum thickness and doping in the channel layer to provide for improved electrical characteristics.
摘要翻译：用GaAsyP1-y应力补偿层形成GaAs异质结构。异质结构由在GaAs衬底上形成的GaAs衬底和GaAsyP1-y应力补偿层组成。应力补偿层的晶格常数小于GaAs衬底的晶格常数。形成在应力补偿层上的沟道层的晶格常数大于GaAs衬底的晶格常数。因此，可以形成假型异质结构，具有最佳厚度和掺杂在沟道层中以提供改善的电特性。

6. 发明授权

US5591666A Semiconductor device and method of fabrication 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US5591666A
公开(公告)日：1997-01-07
申请号：US511776
申请日：1995-08-07
申请人： Kumar Shiralagi , Raymond K. Tsui , Herbert Goronkin
发明人： Kumar Shiralagi , Raymond K. Tsui , Herbert Goronkin
IPC分类号： H01L21/205 , H01L21/20 , H01L29/88
CPC分类号： H01L21/02395 , H01L21/02546 , H01L21/0262 , H01L21/02639 , Y10S117/902 , Y10S117/913 , Y10S438/973
摘要： A method of fabricating semiconductor devices including defining an area on the surface of a substrate, selectively growing, on the area, a crystalline material with at least one defined crystallographic facet, and selectively growing a semiconductor device on the crystallographic facet. In a second embodiment, an area is defined on the surface of a substrate and chemical beam epitaxy is used to selectively grow, on the area, a layer of indium arsenide with at least one defined crystallographic facet.
摘要翻译：一种制造半导体器件的方法，包括限定衬底的表面上的区域，在该区域上选择性地生长具有至少一个限定的结晶小面的晶体材料，以及在晶面上选择性地生长半导体器件。在第二实施例中，在衬底的表面上限定一个区域，并且使用化学束外延在该区域上选择性地在至少一个限定的晶面上生长砷化铟层。

7. 发明授权

US06211530B1 Sparse-carrier devices and method of fabrication 失效
标题翻译：稀疏载波器件及其制造方法
公开(公告)号：US06211530B1
公开(公告)日：2001-04-03
申请号：US09097026
申请日：1998-06-12
申请人： Herbert Goronkin , Raymond K. Tsui , Ruth Y. Zhang , Kumar Shiralagi
发明人： Herbert Goronkin , Raymond K. Tsui , Ruth Y. Zhang , Kumar Shiralagi
IPC分类号： H01L2906
CPC分类号： B82Y10/00 , H01L21/02395 , H01L21/02463 , H01L21/02494 , H01L21/02546 , H01L21/02601 , H01L21/0262 , H01L21/02642 , H01L29/045 , H01L29/127 , H01L29/7613
摘要： A sparse-carrier device includes a crystal structure with a crystallographic facet having contacts at opposite ends. Quantum dots are formed in first and second rows on the facet approximately one quantum dot wide and a plurality of quantum dots long, the quantum dots in the first row being separated from each other by a first distance smaller than a second distance between the quantum dots in the first row and adjacent quantum dots in a second row. The first distance is small enough to allow carrier tunneling between adjacent quantum dots and the second distance is large enough to substantially prevent tunneling between adjacent quantum dots and small enough to allow Coulombic interaction between adjacent quantum dots. Electrical contacts are formed at opposite ends of the rows to allow tunneling of carriers into and out of quantum dots in the first and second rows.
摘要翻译：稀疏载体器件包括晶体结构，其晶体结构在相对端具有接触。量子点形成在小平面上的第一和第二行中，大约一个量子点宽，并且多个量子点长，第一行中的量子点彼此间隔开小于量子点之间的第二距离的第一距离在第二行中的第一行和相邻的量子点。第一距离足够小以允许相邻量子点之间的载流子隧穿，并且第二距离足够大以基本上防止相邻量子点之间的隧道，并且足够小以允许相邻量子点之间的库仑相互作用。电触点形成在行的相对端处，以允许载流子在第一行和第二行中将量子点隧穿。

8. 发明授权

US07074699B2 Method for selective chemical vapor deposition of nanotubes 失效
公开(公告)号：US07074699B2
公开(公告)日：2006-07-11
申请号：US10740295
申请日：2003-12-18
申请人： Ruth Yu-Ai Zhang , Raymond K. Tsui , John Tresek, Jr. , Adam M. Rawlett
发明人： Ruth Yu-Ai Zhang , Raymond K. Tsui , John Tresek, Jr. , Adam M. Rawlett
IPC分类号： H01L21/20
CPC分类号： H01L51/0545 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/162 , C23C16/04 , C23C16/26 , H01L51/0048 , H01L51/0052 , Y10S977/847 , Y10S977/891 , Y10T428/249956 , Y10T428/2975
摘要： A method of fabricating a nanotube structure which includes providing a substrate, providing a mask region positioned on the substrate, patterning and etching through the mask region to form at least one trench, depositing a conductive material layer within the at least one trench, depositing a solvent based nanoparticle catalyst onto the conductive material layer within the at least one trench, removing the mask region and subsequent layers grown thereon using a lift-off process, and forming at least one nanotube electrically connected to the conductive material layer using chemical vapor deposition with a methane precursor.

9. 发明授权

US06689674B2 Method for selective chemical vapor deposition of nanotubes 失效
标题翻译：纳米管选择性化学气相沉积方法
公开(公告)号：US06689674B2
公开(公告)日：2004-02-10
申请号：US10140548
申请日：2002-05-07
申请人： Ruth Yu-ai Zhang , Raymond K. Tsui , John Tresek, Jr. , Adam M. Rawlett
发明人： Ruth Yu-ai Zhang , Raymond K. Tsui , John Tresek, Jr. , Adam M. Rawlett
IPC分类号： H01L2120
CPC分类号： H01L51/0545 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/162 , C23C16/04 , C23C16/26 , H01L51/0048 , H01L51/0052 , Y10S977/847 , Y10S977/891 , Y10T428/249956 , Y10T428/2975
摘要： A method of fabricating a nanotube structure which includes providing a substrate, providing a mask region positioned on the substrate, patterning and etching through the mask region to form at least one trench, depositing a conductive material layer within the at least one trench, depositing a solvent based nanoparticle catalyst onto the conductive material layer within the at least one trench, removing the mask region and subsequent layers grown thereon using a lift-off process, and forming at least one nanotube electrically connected to the conductive material layer using chemical vapor deposition with a methane precursor.
摘要翻译：一种制造纳米管结构的方法，其包括提供基板，提供位于所述基板上的掩模区域，通过所述掩模区域图案化和蚀刻以形成至少一个沟槽，在所述至少一个沟槽内沉积导电材料层，溶剂基纳米颗粒催化剂涂覆到至少一个沟槽内的导电材料层上，使用剥离工艺除去掩模区域和随后的其上生长的层，以及使用化学气相沉积法形成至少一个与导电材料层电连接的纳米管，甲烷前体。

10. 发明授权

US06452205B2 Sparse-carrier devices and method of fabrication 失效
标题翻译：稀疏载波器件及其制造方法
公开(公告)号：US06452205B2
公开(公告)日：2002-09-17
申请号：US09819438
申请日：2001-03-29
申请人： Raymond K. Tsui , Kumar Shiralagi , Herbert Goronkin
发明人： Raymond K. Tsui , Kumar Shiralagi , Herbert Goronkin
IPC分类号： H01L2906
CPC分类号： B82Y10/00 , H01L29/045 , H01L29/127
摘要： A sparse-carrier device including a crystal structure (10) formed of a first material and having a crystallographic facet (26) with a width (w) and a length and quantum dots (30) formed of a second material and positioned in at least one row on the crystallographic facet (26). The at least one row of quantum dots (30) extends along the length of the crystallographic facet (26) and is at least one quantum dot (30) wide (w) and a plurality of quantum dots long. The number of quantum dot rows determined by the width (w) of the crystallographic facet (26). The row of quantum dots (30) form a building block for circuits based on sparse or single electron devices.
摘要翻译：一种稀疏载体器件，包括由第一材料形成并具有宽度（w）和长度的晶体结构（26）和由第二材料形成并且至少位于第二材料的量子点（30）的晶体结构（10）在晶面上有一排（26）。至少一行量子点（30）沿着结晶小面（26）的长度延伸，并且是至少一个量子点（30）宽（w）和多个量子点长。由晶面（26）的宽度（w）确定的量子点行数。量子点行（30）形成基于稀疏或单电子器件的电路的构建块。

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