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1. 发明授权

US5943574A Method of fabricating 3D multilayer semiconductor circuits 失效
标题翻译：制造3D多层半导体电路的方法
公开(公告)号：US5943574A
公开(公告)日：1999-08-24
申请号：US27915
申请日：1998-02-23
申请人： Saied N. Tehrani , Kumar Shiralagi , Herbert Goronkin
发明人： Saied N. Tehrani , Kumar Shiralagi , Herbert Goronkin
IPC分类号： H01L21/336 , H01L21/768 , H01L27/06 , H01L27/092 , H01L29/786
CPC分类号： H01L29/6675 , H01L21/76838 , H01L27/0688 , H01L27/0922 , H01L29/78642
摘要： A method of fabricating 3D semiconductor circuits including providing a conductive layer with doped polysilicon thereon patterned and annealed to form first single grain polysilicon terminals of semiconductor devices. Insulated gate contacts are spaced vertically from the terminals so as to define vertical vias and polysilicon is deposited in the vias to form conduction channels. An upper portion of the polysilicon in the vias is doped to form second terminals for the semiconductor devices, and the polysilicon is annealed to convert it to single grain polysilicon. A second electrically conductive layer is deposited and patterned on the second terminal to define second terminal contacts of the semiconductor devices.
摘要翻译：一种制造3D半导体电路的方法，包括向其上形成有导电层的掺杂多晶硅进行图案化和退火，以形成半导体器件的第一单晶多晶硅端子。绝缘栅极触点与端子垂直间隔开，以便限定垂直通孔，并且多孔沉积在通孔中以形成传导通道。通孔中的多晶硅的上部被掺杂以形成用于半导体器件的第二端子，并且将多晶硅退火以将其转换成单晶粒多晶硅。在第二端子上沉积和图案化第二导电层以限定半导体器件的第二端子触点。

2. 发明授权

US5897366A Method of resistless gate metal etch for fets 失效
标题翻译：用于花边的无阻栅极金属蚀刻方法
公开(公告)号：US5897366A
公开(公告)日：1999-04-27
申请号：US813400
申请日：1997-03-10
申请人： Kumar Shiralagi , Saied N. Tehrani
发明人： Kumar Shiralagi , Saied N. Tehrani
IPC分类号： H01L21/308 , H01L21/335 , H01L21/20
CPC分类号： H01L29/66462 , H01L21/3086
摘要： A method of resistless gate metal etch in the formation of a field effect transistor is disclosed, which includes providing a first layer of a first semiconductor material having a surface. A second layer of a second semiconductor material is formed on the surface and resistlessly patterned to define a masked and an unmasked portions. The unmasked portion of the second layer is etched away to the first layer to enable gate formation.
摘要翻译：公开了在场效应晶体管的形成中的抗电镀栅极金属蚀刻的方法，其包括提供具有表面的第一半导体材料的第一层。在表面上形成第二层第二半导体材料，并且无阻地构图以限定掩模和未掩模部分。第二层的未掩模部分被蚀刻掉到第一层以实现栅极形成。

3. 发明授权

US5748519A Method of selecting a memory cell in a magnetic random access memory device 失效
标题翻译：选择磁性随机存取存储器件中的存储单元的方法
公开(公告)号：US5748519A
公开(公告)日：1998-05-05
申请号：US766637
申请日：1996-12-13
申请人： Saied N. Tehrani , Herbert Goronkin
发明人： Saied N. Tehrani , Herbert Goronkin
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L21/78
CPC分类号： G11C11/15
摘要： Improved methods for selecting memory cells in magnetic random access memory (MRAM) are provided. Whenever a state in a memory cell is sensed, a MRAM requires to adjust an output of comparator to a zero voltage (auto-zeroing step) before the content of memory cell is detected. This invention sequentially accesses memory cells 29-30 once sense line 25 is selected and auto-zeroed. Accordingly, a higher speed operation is attained because the invention does not require an auto-zeroing step every sensing a memory cell.
摘要翻译：提供了用于选择磁随机存取存储器（MRAM）中的存储单元的改进方法。每当检测到存储单元中的状态时，MRAM需要在检测到存储器单元的内容之前将比较器的输出调整为零电压（自动调零步骤）。一旦感测线25被选择并自动归零，本发明顺序地访问存储器单元29-30。因此，由于本发明不需要每次感测存储单元的自动归零步骤，所以实现了更高的速度操作。

4. 发明授权

US5659179A Ultra-small semiconductor devices having patterned edge planar surfaces 失效
标题翻译：具有图案化边缘平坦表面的超小型半导体器件
公开(公告)号：US5659179A
公开(公告)日：1997-08-19
申请号：US399809
申请日：1995-03-07
申请人： Herbert Goronkin , Saied N. Tehrani , Martin Walther , Raymond Tsui
发明人： Herbert Goronkin , Saied N. Tehrani , Martin Walther , Raymond Tsui
IPC分类号： H01L29/06 , H01L21/329 , H01L27/06 , H01L29/88
CPC分类号： H01L29/66219 , H01L27/0605 , H01L29/882
摘要： Ultra-small semiconductor devices and a method of fabrication including patterning the planar surface of a substrate to form a pattern edge (e.g. a mesa) and consecutively forming a plurality of layers of semiconductor material in overlying relationship to the pattern edge so that a discontinuity is produced in the layers and a first layer on one side of the pattern edge is aligned with and in electrical contact with a different layer on the other side of the pattern edge.
摘要翻译：超小型半导体器件和制造方法包括图案化衬底的平坦表面以形成图案边缘（例如台面）并且以与图案边缘重叠的关系连续地形成多个半导体材料层，使得不连续性为在图案边缘的一侧上产生的层和第一层与图案边缘的另一侧上的不同层对准并与之接触。

5. 发明授权

US5326985A Bipolar doped semiconductor structure and method for making 失效
标题翻译：双极掺杂半导体结构及其制造方法
公开(公告)号：US5326985A
公开(公告)日：1994-07-05
申请号：US951994
申请日：1992-09-28
申请人： Herbert Goronkin , Jun Shen , Saied N. Tehrani
发明人： Herbert Goronkin , Jun Shen , Saied N. Tehrani
IPC分类号： H01L29/778 , H01L29/161 , H01L29/205
CPC分类号： H01L29/7783
摘要： A semiconductor structure that provides both N-type and P-type doping from a single dopant source is provided. A first doping region (13) comprising a first material composition includes holes and electrons in a doping energy level (E.sub.D)- A first undoped spacer region (12) comprising the first material composition covers the doping region (13). An undoped channel (11,14) comprising a second material composition covers the first spacer region (12) and a second undoped spacer region (12) comprising the first material composition covers the undoped channel (11,14). The first material composition has a wider bandgap than the second material composition and the doping energy level (E.sub.D) is selected to provide electrons to the undoped channel (11,14) when the second material composition has a conduction band minimum less than the doping energy level (E.sub.D) and to provide holes to the first undoped channel (11,14) when the second material composition has a valence band maximum greater than the doping energy level (E.sub.D).
摘要翻译：提供了从单个掺杂剂源提供N型和P型掺杂的半导体结构。包括第一材料组合物的第一掺杂区域（13）包括掺杂能级（ED）的空穴和电子 - 包含第一材料组合物的第一未掺杂间隔区域（12）覆盖掺杂区域（13）。包括第二材料组合物的未掺杂通道（11,14）覆盖第一间隔区域（12），并且包括第一材料组合物的第二未掺杂间隔区域（12）覆盖未掺杂沟道（11,14）。第一材料组合物具有比第二材料组成更宽的带隙，并且当第二材料组合物具有小于掺杂能量的导带最小值时，选择掺杂能级（ED）以向未掺杂沟道（11,14）提供电子（ED），并且当第二材料组合物具有大于掺杂能级（ED）的价带最大值时，向第一未掺杂通道（11,14）提供孔。

6. 发明授权

US5081511A Heterojunction field effect transistor with monolayers in channel region 失效
标题翻译：通道区域中具有单层的异质结场效应晶体管
公开(公告)号：US5081511A
公开(公告)日：1992-01-14
申请号：US578167
申请日：1990-09-06
申请人： Saied N. Tehrani , Herbert Goronkin
发明人： Saied N. Tehrani , Herbert Goronkin
IPC分类号： H01L29/812 , H01L21/335 , H01L21/338 , H01L29/12 , H01L29/36 , H01L29/43 , H01L29/778
CPC分类号： B82Y10/00 , H01L29/122 , H01L29/432 , H01L29/66462 , H01L29/7783 , H01L29/365
摘要： A heterojunction field effect transistor (HFET) having a source, drain, and channel, wherein the channel comprises a quantum well and at least one mono-atomic well or barrier layer is provided. The mono-atomic well or barrier layer has a different bandgap than the channel region and serves to modify electron wave function and conduction band energy in the channel region. Preferably, an indium arsenide well monolayer is formed in an InGaAs channel region and functions to move a first quantized energy level E.sub.0 closer to the bottom of the channel region quantum well thereby increasing electron concentration by increasing effective band offset potential. Another embodiment uses an aluminum arsenide monolayer as a barrier monolayer in the InGaAs channel. By varying location of the monolayers, confinement of electrons in the channel can be improved.

7. 发明授权

US5920500A Magnetic random access memory having stacked memory cells and fabrication method therefor 失效
标题翻译：具有堆叠存储单元的磁性随机存取存储器及其制造方法
公开(公告)号：US5920500A
公开(公告)日：1999-07-06
申请号：US702781
申请日：1996-08-23
申请人： Saied N. Tehrani , Xiaodong T. Zhu , Eugene Chen , Herbert Goronkin
发明人： Saied N. Tehrani , Xiaodong T. Zhu , Eugene Chen , Herbert Goronkin
IPC分类号： G11C11/15 , G11C11/14 , H01L21/8246 , H01L27/105 , H01L27/22 , H01L43/08
CPC分类号： G11C11/14 , H01L27/222
摘要： A magnetic random access memory (10) has a plurality of stacked memory cells on semiconductor substrate (11), each cell basically having a portion of magnetic material (12), a word line (13), and sense line (14). Upper sense line (22) is electrically coupled to lower sense line (12) via conductor line (23) with ohmic contacts. In order to read and store states in the memory cell, lower and upper word lines (13, 18) are activated, thereby total magnetic field is applied to portion of magnetic material (11). This stacked memory structure allows magnetic random access memory (10) to integrate more memory cells on semiconductor substrate (11).
摘要翻译：磁性随机存取存储器（10）在半导体衬底（11）上具有多个堆叠的存储单元，每个单元基本上具有一部分磁性材料（12），字线（13）和感测线（14）。上感测线（22）经由导体线（23）与欧姆接触电耦合到下感测线（12）。为了读取和存储存储单元中的状态，上下文字线（13,18）被激活，从而将总磁场施加到磁性材料（11）的一部分。这种堆叠式存储器结构允许磁性随机存取存储器（10）将更多的存储器单元集成在半导体衬底（11）上。

8. 发明授权

US5745408A Multi-layer magnetic memory cell with low switching current 失效
标题翻译：具有低开关电流的多层磁存储单元
公开(公告)号：US5745408A
公开(公告)日：1998-04-28
申请号：US709589
申请日：1996-09-09
申请人： Eugene Chen , Saied N. Tehrani , Herbert Goronkin
发明人： Eugene Chen , Saied N. Tehrani , Herbert Goronkin
IPC分类号： G11C11/15 , G11C11/16 , G11C11/56
CPC分类号： G11C11/5607 , G11C11/15 , G11C11/16 , G11C2211/5615 , G11C2211/5616
摘要： A multi-layer magnetic memory cell including two similar layers of magnetic material stacked in parallel, overlying relationship and separated by a layer of non-magnetic material. Each of the two similar layers have a width that is less than a width of magnetic domain walls within the layer of magnetic material so that magnetic vectors in the two similar layers point along the length thereof. The two similar layers define a central plane parallel with the two similar layers symmetrically formed and positioned thereabout. Magnetic vectors in the two similar layers are switched simultaneously and the two similar layers are positioned close enough together to allow mutual cancellation of pole effects during simultaneous switching of the magnetic vectors.
摘要翻译：一层多层磁性存储单元，包括两层相似的磁性材料层，平行层叠，并由一层非磁性材料分开。两个相似层中的每一个具有小于磁性材料层内的磁畴壁的宽度的宽度，使得两个相似层中的磁矢量沿其长度指向。两个相似的层限定了与对称地形成并定位在其周围的两个相似层平行的中心平面。两个相似层中的磁矢量被同时切换，并且两个相似的层被放置得足够靠近在一起，以允许在磁矢量的同时切换期间相互抵消极效应。

9. 发明授权

US5693955A Tunnel transistor 失效
标题翻译：隧道晶体管
公开(公告)号：US5693955A
公开(公告)日：1997-12-02
申请号：US625666
申请日：1996-03-29
申请人： Herbert Goronkin , Saied N. Tehrani
发明人： Herbert Goronkin , Saied N. Tehrani
IPC分类号： H01L29/06 , H01L29/772 , H01L29/78 , H01L49/02 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/772
摘要： A tunnel transistor including source and drain and a silicon oxide tunneling layer overlying the source. A polysilicon quantum well layer positioned on the tunneling layer and in contact with the drain. The quantum well layer having a thickness which places the ground state above the Fermi level. A silicon oxide insulating layer positioned on the quantum well layer and a gate electrode positioned on the insulating layer overlying the quantum well layer and the source terminal. The tunneling layer being thin enough to allow tunneling between the source and the quantum well layer, and the insulating layer being thick enough to prevent tunneling therethrough.
摘要翻译：包括源极和漏极的隧道晶体管和覆盖源极的氧化硅隧道层。位于隧道层上并与漏极接触的多晶硅量子阱层。量子阱层具有将基态置于费米能级之上的厚度。定位在量子阱层上的氧化硅绝缘层和位于覆盖量子阱层和源极端子的绝缘层上的栅电极。隧道层足够薄以允许源极和量子阱层之间的隧穿，并且绝缘层足够厚以防止隧道穿过其中。

10. 发明授权

US5477169A Logic circuit with negative differential resistance device 失效
标题翻译：具有负差分电阻器件的逻辑电路
公开(公告)号：US5477169A
公开(公告)日：1995-12-19
申请号：US261799
申请日：1994-06-20
申请人： Jun Shen , Herbert Goronkin , Saied N. Tehrani
发明人： Jun Shen , Herbert Goronkin , Saied N. Tehrani
IPC分类号： H01L21/822 , G11C5/14 , H01L27/04 , H01L29/06 , H01L29/66 , H01L29/86 , H01L29/88 , H03K19/094 , H03K19/0944 , H03K19/10 , H03K19/21 , G06F7/50
CPC分类号： G11C5/142 , H03K19/094 , H03K19/10 , H03K19/215
摘要： A logic circuit including a pair of FETs connected in parallel and including first and second common current terminals, each of the FETs further having a control terminal connected to receive a logic signal thereon. A negative differential resistance device affixed to one of the first and second common current terminals and having a conductance characteristic such that the device operates at a peak current when one of the FETs is turned ON and at a valley current when both of the FETs are simultaneously turned ON. A load resistance coupled to the other of the first and second common current terminals and providing an output for the logic circuit.
摘要翻译：一种逻辑电路，包括并联连接并包括第一和第二公共电流端子的一对FET，每个FET还具有连接以在其上接收逻辑信号的控制端子。固定在第一和第二公共电流端子中的一个并具有电导特性的负差分电阻器件，使得器件在FET中的一个导通时以峰值电流工作，并且当两个FET同时处于谷值电流时工作打开。负载电阻耦合到第一和第二公共电流端子中的另一个，并提供逻辑电路的输出。

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