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1. 发明申请

US20050127409A1 System for high-precision double-diffused MOS transistors 审中-公开
标题翻译：高精度双扩散MOS晶体管系统
公开(公告)号：US20050127409A1
公开(公告)日：2005-06-16
申请号：US11042536
申请日：2005-01-25
申请人： Henry Edwards , Sameer Pendharkar , Joe Trogolo , Tathagata Chatterjee , Taylor Efland
发明人： Henry Edwards , Sameer Pendharkar , Joe Trogolo , Tathagata Chatterjee , Taylor Efland
IPC分类号： H01L29/06 , H01L29/10 , H01L29/423 , H01L29/78 , H01L29/76 , H01L21/336 , H01L31/062
CPC分类号： H01L29/0696 , H01L29/1095 , H01L29/4238 , H01L29/7801
摘要： The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (404, 516, 616), and an oxide region (414, 512, 608) overlapping the moat region. A double-diffusion region (402, 504, 618) is formed within the oxide region, having end cap regions (406, 502, 620) that are effectively deactivated utilizing geometric and implant manipulations.
摘要翻译：本发明提供了一种用于有效地生产多功能，高精度的MOS器件结构的系统，其中直线区域主导器件的行为，以简单，高效和成本有效的方式提供精确匹配大型器件的最小几何器件。本发明提供了用于生产双扩散半导体器件的方法和装置，其最小化端帽区域的性能影响。本发明提供一种MOS结构，其具有护城河区域（404,516,616）和与护城河区域重叠的氧化物区域（414,512,608）。在氧化物区域内形成双扩散区域（402,504,618），具有端盖区域（406,502,620），其可以利用几何和植入操作被有效地去激活。

2. 发明授权

US06867100B2 System for high-precision double-diffused MOS transistors 有权
标题翻译：高精度双扩散MOS晶体管系统
公开(公告)号：US06867100B2
公开(公告)日：2005-03-15
申请号：US10326214
申请日：2002-12-19
申请人： Henry L. Edwards , Sameer Pendharkar , Joe Trogolo , Tathagata Chatterjee , Taylor Efland
发明人： Henry L. Edwards , Sameer Pendharkar , Joe Trogolo , Tathagata Chatterjee , Taylor Efland
IPC分类号： H01L29/06 , H01L29/10 , H01L29/423 , H01L29/78 , H01L21/336
CPC分类号： H01L29/0696 , H01L29/1095 , H01L29/4238 , H01L29/7801
摘要： The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (404, 516, 616), and an oxide region (414, 512, 608) overlapping the moat region. A double-diffusion region (402, 504, 618) is formed within the oxide region, having end cap regions (406, 502, 620) that are effectively deactivated utilizing geometric and implant manipulations.
摘要翻译：本发明提供了一种用于有效地生产多功能，高精度的MOS器件结构的系统，其中直线区域主导器件的行为，以简单，高效和成本有效的方式提供精确匹配大型器件的最小几何器件。本发明提供了用于生产双扩散半导体器件的方法和装置，其最小化端帽区域的性能影响。本发明提供一种MOS结构，其具有护城河区域（404,516,616）和与护城河区域重叠的氧化物区域（414,512,608）。在氧化物区域内形成双扩散区域（402,504,618），具有端盖区域（406,502,620），其可以利用几何和植入操作被有效地去激活。

3. 发明申请

US20080090346A1 Reliable High-Voltage Junction Field Effect Transistor and Method of Manufacturing Therefor 有权
标题翻译：可靠的高压结场效应晶体管及其制造方法
公开(公告)号：US20080090346A1
公开(公告)日：2008-04-17
申请号：US11933909
申请日：2007-11-01
申请人： Kaiyuan Chen , Joe Trogolo , Tathagata Chatterjee , Steve Merchant
发明人： Kaiyuan Chen , Joe Trogolo , Tathagata Chatterjee , Steve Merchant
IPC分类号： H01L21/337
CPC分类号： H01L29/402 , H01L29/1066 , H01L29/41725 , H01L29/42316 , H01L29/66901 , H01L29/808
摘要： The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410). In place of or addition to the doped region (810), the high-voltage junction field effect transistor (JFET) (300) may includes a conductive field plate (920) located over and extending along the width of the gate region (410).
摘要翻译：本发明提供一种高电压结型场效应晶体管（JFET），一种制造方法和包括该高压结型场效应晶体管的集成电路。高压结场效应晶体管（JFET）（300）的一个实施例包括位于衬底（318）内的第一导电类型的阱区（320）和位于衬底（318）内的第二导电类型的栅极区（410）所述阱区域（320），所述栅极区域（410）具有长度和宽度。该实施例还包括与栅极区域（410）间隔开的位于衬底（318）内的第一导电类型的源极区（710）和漏极区（715），以及掺杂区位于栅极区域（410）中并沿着栅极区域（410）的宽度延伸的第二导电类型。高电压结场效应晶体管（JFET）300可代替或添加到掺杂区域（810），包括位于栅极区域（410）的宽度上方且沿栅极区域（410）的宽度延伸的导电场板（920）。

4. 发明授权

US07312481B2 Reliable high-voltage junction field effect transistor and method of manufacture therefor 有权
标题翻译：可靠的高压结场效应晶体管及其制造方法
公开(公告)号：US07312481B2
公开(公告)日：2007-12-25
申请号：US10956863
申请日：2004-10-01
申请人： Kaiyuan Chen , Joe Trogolo , Tathagata Chatterjee , Steve Merchant
发明人： Kaiyuan Chen , Joe Trogolo , Tathagata Chatterjee , Steve Merchant
IPC分类号： H01L29/74 , H01L29/423 , H01L31/111
CPC分类号： H01L29/402 , H01L29/1066 , H01L29/41725 , H01L29/42316 , H01L29/66901 , H01L29/808
摘要： The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410). In place of or addition to the doped region (810), the high-voltage junction field effect transistor (JFET) (300) may includes a conductive field plate (920) located over and extending along the width of the gate region (410).
摘要翻译：本发明提供一种高电压结型场效应晶体管（JFET），一种制造方法和包括该高压结型场效应晶体管的集成电路。高压结场效应晶体管（JFET）（300）的一个实施例包括位于衬底（318）内的第一导电类型的阱区（320）和位于衬底（318）内的第二导电类型的栅极区（410）所述阱区域（320），所述栅极区域（410）具有长度和宽度。该实施例还包括与栅极区域（410）间隔开的位于衬底（318）内的第一导电类型的源极区（710）和漏极区（715），以及掺杂区位于栅极区域（410）中并沿着栅极区域（410）的宽度延伸的第二导电类型。高电压结场效应晶体管（JFET）300可代替或添加到掺杂区域（810），包括位于栅极区域（410）的宽度上方且沿栅极区域（410）的宽度延伸的导电场板（920）。

5. 发明申请

US20060071247A1 Reliable high-voltage junction field effect transistor and method of manufacture therefor 有权
标题翻译：可靠的高压结场效应晶体管及其制造方法
公开(公告)号：US20060071247A1
公开(公告)日：2006-04-06
申请号：US10956863
申请日：2004-10-01
申请人： Kaiyuan Chen , Joe Trogolo , Tathagata Chatterjee , Steve Merchant
发明人： Kaiyuan Chen , Joe Trogolo , Tathagata Chatterjee , Steve Merchant
IPC分类号： H01L21/337 , H01L29/80
CPC分类号： H01L29/402 , H01L29/1066 , H01L29/41725 , H01L29/42316 , H01L29/66901 , H01L29/808
摘要： The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410). In place of or addition to the doped region (810), the high-voltage junction field effect transistor (JFET) (300) may includes a conductive field plate (920) located over and extending along the width of the gate region (410).
摘要翻译：本发明提供一种高电压结型场效应晶体管（JFET），一种制造方法和包括该高压结型场效应晶体管的集成电路。高压结场效应晶体管（JFET）（300）的一个实施例包括位于衬底（318）内的第一导电类型的阱区（320）和位于衬底（318）内的第二导电类型的栅极区（410）所述阱区域（320），所述栅极区域（410）具有长度和宽度。该实施例还包括与栅极区域（410）间隔开的位于衬底（318）内的第一导电类型的源极区（710）和漏极区（715），以及掺杂区位于栅极区域（410）中并沿着栅极区域（410）的宽度延伸的第二导电类型。高电压结场效应晶体管（JFET）300可代替或添加到掺杂区域（810），包括位于栅极区域（410）的宽度上方且沿栅极区域（410）的宽度延伸的导电场板（920）。

6. 发明授权

US07704813B2 Reliable high-voltage junction field effect transistor and method of manufacturing therefor 有权
标题翻译：可靠的高压结场效应晶体管及其制造方法
公开(公告)号：US07704813B2
公开(公告)日：2010-04-27
申请号：US11933909
申请日：2007-11-01
申请人： Kaiyuan Chen , Joe Trogolo , Tathagata Chatterjee , Steve Merchant
发明人： Kaiyuan Chen , Joe Trogolo , Tathagata Chatterjee , Steve Merchant
IPC分类号： H01L21/337
CPC分类号： H01L29/402 , H01L29/1066 , H01L29/41725 , H01L29/42316 , H01L29/66901 , H01L29/808
摘要： The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410). In place of or addition to the doped region (810), the high-voltage junction field effect transistor (JFET) (300) may includes a conductive field plate (920) located over and extending along the width of the gate region (410).
摘要翻译：本发明提供一种高电压结型场效应晶体管（JFET），一种制造方法和包括该高压结型场效应晶体管的集成电路。高压结场效应晶体管（JFET）（300）的一个实施例包括位于衬底（318）内的第一导电类型的阱区（320）和位于衬底（318）内的第二导电类型的栅极区（410）所述阱区域（320），所述栅极区域（410）具有长度和宽度。该实施例还包括与栅极区域（410）间隔开的位于衬底（318）内的第一导电类型的源极区（710）和漏极区（715），以及掺杂区位于栅极区域（410）中并沿着栅极区域（410）的宽度延伸的第二导电类型。高电压结场效应晶体管（JFET）300可代替或添加到掺杂区域（810），包括位于栅极区域（410）的宽度上方且沿栅极区域（410）的宽度延伸的导电场板（920）。

7. 发明申请

US20070205435A1 Versatile system for optimizing current gain in bipolar transistor structures 有权
标题翻译：用于优化双极晶体管结构中电流增益的通用系统
公开(公告)号：US20070205435A1
公开(公告)日：2007-09-06
申请号：US11745906
申请日：2007-05-08
申请人： Joe Trogolo , Tathagata Chatterlee , Lily Springer , Jeff Smith
发明人： Joe Trogolo , Tathagata Chatterlee , Lily Springer , Jeff Smith
IPC分类号： H01L29/739
CPC分类号： H01L29/66272 , H01L21/8249 , H01L29/0804
摘要： Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.
摘要翻译：公开了用于设计双极发射器结构的电接触的装置和方法。确定发射极结构（106,306,404,404）的面积和电接触结构（108,308,402,406）所需的电流密度通过量。基于所需的电流密度确定所需的电接触面积，并且然后设计电接触结构以将所需的电接触面积相对于发射器结构区域最小化。

8. 发明授权

US07226835B2 Versatile system for optimizing current gain in bipolar transistor structures 有权
公开(公告)号：US07226835B2
公开(公告)日：2007-06-05
申请号：US10196634
申请日：2002-07-15
申请人： Joe Trogolo , Tathagata Chatterlee , Lily Springer , Jeff Smith
发明人： Joe Trogolo , Tathagata Chatterlee , Lily Springer , Jeff Smith
IPC分类号： H01L31/0328
CPC分类号： H01L29/66272 , H01L21/8249 , H01L29/0804
摘要： Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.

9. 发明申请

US20050087812A1 Reduce 1/f noise in NPN transistors without degrading the properties of PNP transistors in integrated circuit technologies 有权
标题翻译：降低NPN晶体管中的1 / f噪声，而不降低集成电路技术中PNP晶体管的性能
公开(公告)号：US20050087812A1
公开(公告)日：2005-04-28
申请号：US10994563
申请日：2004-11-22
申请人： Joe Trogolo , William Loftin , William Kyser
发明人： Joe Trogolo , William Loftin , William Kyser
IPC分类号： H01L21/331 , H01L21/8228 , H01L27/082 , H01L29/08 , H01L29/74
CPC分类号： H01L29/66287 , H01L21/82285 , H01L27/0826 , H01L29/0804
摘要： An interfacial oxide layer (185) is formed in the emitter regions of the NPN transistor (280, 220) and the PNP transistor (290, 200). Fluorine is selectively introduced into the polysilicon emitter region of the NPN transistor (220) to reduce the 1/f noise in the NPN transistor.
摘要翻译：在NPN晶体管（280,220）和PNP晶体管（290,200）的发射极区域中形成界面氧化物层（185）。氟选择性地引入到NPN晶体管（220）的多晶硅发射极区域中，以降低NPN晶体管中的1 / f噪声。

10. 发明授权

US08110857B2 Low noise JFET 有权
标题翻译：低噪声JFET
公开(公告)号：US08110857B2
公开(公告)日：2012-02-07
申请号：US12713866
申请日：2010-02-26
申请人： Pinghai Hao , Imran Khan , Joe Trogolo
发明人： Pinghai Hao , Imran Khan , Joe Trogolo
IPC分类号： H01L29/66
CPC分类号： H01L29/8086 , H01L29/66901 , H01L29/808
摘要： A low noise (1/f) junction field effect transistor (JFET) is disclosed, wherein multiple implants push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.
摘要翻译：公开了一种低噪声（1 / f）结场效应晶体管（JFET），其中多个种植体推动晶体管的导电路径离开形成晶体管的层的表面。以这种方式，导电路径中的电流不太可能受到可能存在于层的表面处的缺陷的干扰，从而减轻（1 / f）噪声。

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