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1. 发明申请

US20050253191A1 Robust DEMOS transistors and method for making the same 有权
标题翻译：坚固的DEMOS晶体管及其制造方法
公开(公告)号：US20050253191A1
公开(公告)日：2005-11-17
申请号：US10837918
申请日：2004-05-03
申请人： Sameer Pendharkar , Ramanathan Ramani , Taylor Efland
发明人： Sameer Pendharkar , Ramanathan Ramani , Taylor Efland
IPC分类号： H01L21/336 , H01L29/08 , H01L29/10 , H01L29/76 , H01L29/78
CPC分类号： H01L29/0847 , H01L29/0878 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first portion extending partially under a gate structure between the channel and the second portion, and the second portion extending laterally between the first portion and the drain, wherein the first portion of the drift region has a concentration of first type dopants higher than the second portion.
摘要翻译：提供了扩大漏极MOS晶体管器件和制造方法，其中在第一导电类型的漏极和沟道之间形成第一导电类型的漂移区域。所述漂移区域包括第一和第二部分，所述第一部分部分地在所述通道和所述第二部分之间的栅极结构下方延伸，并且所述第二部分在所述第一部分和所述漏极之间横向延伸，其中所述漂移区域的所述第一部分具有第一种掺杂剂的浓度高于第二部分。

2. 发明授权

US06441431B1 Lateral double diffused metal oxide semiconductor device 有权
公开(公告)号：US06441431B1
公开(公告)日：2002-08-27
申请号：US09454934
申请日：1999-12-03
申请人： Taylor Efland , Chin-Yu Tsai , Sameer Pendharkar
发明人： Taylor Efland , Chin-Yu Tsai , Sameer Pendharkar
IPC分类号： H01L2976
CPC分类号： H01L29/66537 , H01L29/086 , H01L29/0878 , H01L29/1045 , H01L29/1095 , H01L29/42368 , H01L29/517 , H01L29/518 , H01L29/7816 , H01L29/7833
摘要： An embodiment of the instant invention is a transistor formed on a semiconductor substrate of a first conductivity type and having an upper surface, the transistor comprising: a well region (well 204 of FIG. 1a) formed in the semiconductor substrate (layer 202 of FIG. 1a), the well region of a second conductivity type opposite that of the first conductivity type; a source region (source region 208 of FIG. 1a) formed in the well region in the semiconductor substrate, the source region of the second conductivity type; a drain region (drain 210 of FIG. 1a) formed in the semiconductor substrate and spaced away from the source region by a channel region (given by length L1+L2), the drain region of the second conductivity type; a conductive gate electrode (layer 218 of FIG. 1a) disposed over the semiconductor substrate and over the channel region; a gate insulating layer (layer 214 of FIG. 1a) disposed between the conductive gate electrode and the semiconductor substrate and having a length, the gate insulating layer comprising: a first portion of the gate insulating layer which has a first length (L1) and a first thickness; a second portion of the gate insulating layer which has a second length (L2) and a second thickness which is substantially thicker than the first thickness, the sum of the first length and the second length equalling the length of the gate insulating layer; and wherein the first portion of the gate insulating layer being situated proximate to the source region and spaced away from the drain region by the second portion of the gate insulating layer; and wherein the well region having a dopant concentration less than that of the source region and the drain region, the well region extends at least from source region towards the drain region so as to completely underlie the first portion of the gate insulating layer and to underlie at least the second portion of the gate insulating layer.

3. 发明申请

US20140197486A1 POWER INTEGRATED CIRCUIT INCLUDING SERIES-CONNECTED SOURCE SUBSTRATE AND DRAIN SUBSTRATE POWER MOSFETS 有权
标题翻译：功率集成电路，包括串联源极基极和漏极基极功率MOSFET
公开(公告)号：US20140197486A1
公开(公告)日：2014-07-17
申请号：US13563923
申请日：2012-08-01
申请人： Christopher Boguslaw Kocon , Marie Denison , Taylor Efland
发明人： Christopher Boguslaw Kocon , Marie Denison , Taylor Efland
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L27/088 , H01L27/0922 , H01L29/0634 , H01L29/0649 , H01L29/0696 , H01L29/404 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4933 , H01L29/7802 , H01L29/7803 , H01L29/7809 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region parallel to channel current flow. The RESURF trenches have dielectric liners and electrically conductive RESURF elements on the liners. Source contact metal is disposed over the body region and source regions. A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer, and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region perpendicular to channel current flow. Source contact metal is disposed in a source contact trench and extended over the drain drift region to provide a field plate.
摘要翻译：一种半导体器件，其包含在下漏极层上方具有漏极漂移区域的高电压MOS晶体管和横向设置在衬底顶表面处的沟道区域。 RESURF沟槽穿过漏极漂移区域和与通道电流流动平行的体区域。 RESURF沟槽在衬垫上具有电介质衬垫和导电RESURF元件。源接触金属设置在身体区域和源区域上。一种半导体器件，其包含在下漏极层上具有漏极漂移区域的高电压MOS晶体管，以及横向设置在衬底顶表面处的沟道区域。 RESURF沟槽穿过垂直于沟道电流的漏极漂移区域和体区。源极接触金属设置在源极接触沟槽中并在漏极漂移区域上延伸以提供场板。

4. 发明申请

US20070122944A1 Individualized Low Parasitic Power Distribution Lines Deposited Over Active Integrated Circuits 有权
标题翻译：存储在有源集成电路上的个性化低寄生配电线路
公开(公告)号：US20070122944A1
公开(公告)日：2007-05-31
申请号：US11539486
申请日：2006-10-06
申请人： Taylor Efland , Milton Buschbom , Sameer Pendharkar
发明人： Taylor Efland , Milton Buschbom , Sameer Pendharkar
IPC分类号： H01L21/60
CPC分类号： H01L24/05 , H01L23/5286 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/04042 , H01L2224/05083 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/0518 , H01L2224/05184 , H01L2224/05187 , H01L2224/05554 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48624 , H01L2224/48639 , H01L2224/48644 , H01L2224/48664 , H01L2224/48669 , H01L2224/48724 , H01L2224/48739 , H01L2224/48744 , H01L2224/48764 , H01L2224/48769 , H01L2224/48824 , H01L2224/48839 , H01L2224/48844 , H01L2224/48864 , H01L2224/49175 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01032 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01083 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/13055 , H01L2924/14 , H01L2924/15724 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/20752 , H01L2924/20753 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00014 , H01L2924/04953 , H01L2924/00 , H01L2924/00012 , H01L2224/48869
摘要： An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by conductors to segments of the leadframe. Furthermore, the lines are fabricated with a sheet resistance of less than 1.5 mΩ/· and the majority of the lines is patterned as straight lines between the vias and the conductors, respectively.
摘要翻译：安装在引线框架上的集成电路（IC）芯片具有沉积在芯片表面上的配电线网络，使得这些线路位于IC的有源元件上方，通过金属填充的通孔垂直连接到选定的有源线路下方的组件，以及引线框架的导体。此外，线路的薄层电阻小于1.5mOmega /。并且大多数线分别被图案化为通孔和导体之间的直线。

5. 发明申请

US20050127409A1 System for high-precision double-diffused MOS transistors 审中-公开
标题翻译：高精度双扩散MOS晶体管系统
公开(公告)号：US20050127409A1
公开(公告)日：2005-06-16
申请号：US11042536
申请日：2005-01-25
申请人： Henry Edwards , Sameer Pendharkar , Joe Trogolo , Tathagata Chatterjee , Taylor Efland
发明人： Henry Edwards , Sameer Pendharkar , Joe Trogolo , Tathagata Chatterjee , Taylor Efland
IPC分类号： H01L29/06 , H01L29/10 , H01L29/423 , H01L29/78 , H01L29/76 , H01L21/336 , H01L31/062
CPC分类号： H01L29/0696 , H01L29/1095 , H01L29/4238 , H01L29/7801
摘要： The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (404, 516, 616), and an oxide region (414, 512, 608) overlapping the moat region. A double-diffusion region (402, 504, 618) is formed within the oxide region, having end cap regions (406, 502, 620) that are effectively deactivated utilizing geometric and implant manipulations.
摘要翻译：本发明提供了一种用于有效地生产多功能，高精度的MOS器件结构的系统，其中直线区域主导器件的行为，以简单，高效和成本有效的方式提供精确匹配大型器件的最小几何器件。本发明提供了用于生产双扩散半导体器件的方法和装置，其最小化端帽区域的性能影响。本发明提供一种MOS结构，其具有护城河区域（404,516,616）和与护城河区域重叠的氧化物区域（414,512,608）。在氧化物区域内形成双扩散区域（402,504,618），具有端盖区域（406,502,620），其可以利用几何和植入操作被有效地去激活。

6. 发明申请

US20050118753A1 Low cost fabrication method for high voltage, high drain current MOS transistor 有权
标题翻译：低成本高漏极电流MOS晶体管制造方法
公开(公告)号：US20050118753A1
公开(公告)日：2005-06-02
申请号：US10725642
申请日：2003-12-02
申请人： Taylor Efland , Jozef Mitros , Imran Khan
发明人： Taylor Efland , Jozef Mitros , Imran Khan
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/78
CPC分类号： H01L29/0847 , H01L29/0878 , H01L29/1083 , H01L29/1087 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A method for reducing the drain resistance of a drain-extended MOS transistor in a semiconductor wafer, while maintaining a high transistor breakdown voltage. The method provides a first well (502) of a first conductivity type, operable as the extension of the transistor drain (501) of the first conductivity type; portions of the well are covered by a first insulator (503) having a first thickness. A second well (504) of the opposite conductivity type is intended to contain the transistor source (506) of the first conductivity type; portions of the second well are covered by a second insulator (507) thinner than the first insulator. The first and second wells form a junction (505) that terminates at the second insulator (530a, 530b). The method deposits a photoresist layer (510) over the wafer, which is patterned by opening a window (510a) that extends from the drain to the junction termination. Next, ions (540) of the first conductivity type are implanted through the window into the first well; these said ions have an energy to limit the penetration depth (541) to the first insulator thickness, and a dose to create a well region (560) of high doping concentration adjacent to the junction termination (530a).
摘要翻译：一种在保持高晶体管击穿电压的同时降低半导体晶片中的漏极扩展MOS晶体管的漏极电阻的方法。该方法提供第一导电类型的第一阱（502），其可操作为第一导电类型的晶体管漏极（501）的延伸; 阱的一部分被具有第一厚度的第一绝缘体（503）覆盖。相反导电类型的第二阱（504）旨在包含第一导电类型的晶体管源（506）; 第二阱的部分被比第一绝缘体薄的第二绝缘体（507）覆盖。第一和第二阱形成终止于第二绝缘体（530a，530b）的结（505）。该方法将光致抗蚀剂层（510）沉积在晶片之上，其通过打开从漏极延伸到结终端的窗口（510a）而被图案化。接下来，通过窗口将第一导电类型的离子（540）注入到第一阱中; 这些所述离子具有将穿透深度（541）限制到第一绝缘体厚度的能量，以及用于产生邻近连接终端（530a）的高掺杂浓度的阱区（560）的剂量。

7. 发明授权

US06867100B2 System for high-precision double-diffused MOS transistors 有权
标题翻译：高精度双扩散MOS晶体管系统
公开(公告)号：US06867100B2
公开(公告)日：2005-03-15
申请号：US10326214
申请日：2002-12-19
申请人： Henry L. Edwards , Sameer Pendharkar , Joe Trogolo , Tathagata Chatterjee , Taylor Efland
发明人： Henry L. Edwards , Sameer Pendharkar , Joe Trogolo , Tathagata Chatterjee , Taylor Efland
IPC分类号： H01L29/06 , H01L29/10 , H01L29/423 , H01L29/78 , H01L21/336
CPC分类号： H01L29/0696 , H01L29/1095 , H01L29/4238 , H01L29/7801
摘要： The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (404, 516, 616), and an oxide region (414, 512, 608) overlapping the moat region. A double-diffusion region (402, 504, 618) is formed within the oxide region, having end cap regions (406, 502, 620) that are effectively deactivated utilizing geometric and implant manipulations.
摘要翻译：本发明提供了一种用于有效地生产多功能，高精度的MOS器件结构的系统，其中直线区域主导器件的行为，以简单，高效和成本有效的方式提供精确匹配大型器件的最小几何器件。本发明提供了用于生产双扩散半导体器件的方法和装置，其最小化端帽区域的性能影响。本发明提供一种MOS结构，其具有护城河区域（404,516,616）和与护城河区域重叠的氧化物区域（414,512,608）。在氧化物区域内形成双扩散区域（402,504,618），具有端盖区域（406,502,620），其可以利用几何和植入操作被有效地去激活。

8. 发明授权

US08928075B2 Power integrated circuit including series-connected source substrate and drain substrate power MOSFETs 有权
标题翻译：功率集成电路包括串联源极衬底和漏极衬底功率MOSFET
公开(公告)号：US08928075B2
公开(公告)日：2015-01-06
申请号：US13563923
申请日：2012-08-01
申请人： Christopher Boguslaw Kocon , Marie Denison , Taylor Efland
发明人： Christopher Boguslaw Kocon , Marie Denison , Taylor Efland
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/088 , H01L29/78
CPC分类号： H01L27/088 , H01L27/0922 , H01L29/0634 , H01L29/0649 , H01L29/0696 , H01L29/404 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4933 , H01L29/7802 , H01L29/7803 , H01L29/7809 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region parallel to channel current flow. The RESURF trenches have dielectric liners and electrically conductive RESURF elements on the liners. Source contact metal is disposed over the body region and source regions. A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer, and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region perpendicular to channel current flow. Source contact metal is disposed in a source contact trench and extended over the drain drift region to provide a field plate.
摘要翻译：一种半导体器件，其包含在下漏极层上方具有漏极漂移区域的高电压MOS晶体管和横向设置在衬底顶表面处的沟道区域。 RESURF沟槽穿过漏极漂移区域和与通道电流流动平行的体区域。 RESURF沟槽在衬垫上具有电介质衬垫和导电RESURF元件。源接触金属设置在身体区域和源区域上。一种半导体器件，其包含在下漏极层上具有漏极漂移区域的高电压MOS晶体管，以及横向设置在衬底顶表面处的沟道区域。 RESURF沟槽穿过垂直于沟道电流的漏极漂移区域和体区。源极接触金属设置在源极接触沟槽中并在漏极漂移区域上延伸以提供场板。

9. 发明申请

US20050255655A1 N-channel LDMOS with buried P-type region to prevent parasitic bipolar effects 有权
标题翻译： N沟道LDMOS具有掩埋P型区域，以防止寄生双极效应
公开(公告)号：US20050255655A1
公开(公告)日：2005-11-17
申请号：US11179857
申请日：2005-07-12
申请人： Philip Hower , Taylor Efland
发明人： Philip Hower , Taylor Efland
IPC分类号： H01L27/085 , H01L21/336 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/78
CPC分类号： H01L29/7816 , H01L29/0878 , H01L29/1095 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/66689
摘要： An improved n-channel integrated lateral DMOS (10) in which a buried body region (30), beneath and self-aligned to the source (18) and normal body diffusions, provides a low impedance path for holes emitted at the drain region (16). This greatly reduces secondary electron generation, and accordingly reduces the gain of the parasitic PNP bipolar device. The reduced regeneration in turn raises the critical field value, and hence the safe operating area.
摘要翻译：改进的n沟道集成横向DMOS（10），其中在源极（18）下方并自对准并且正常体扩散的掩埋体区域（30）为漏极区域处发射的空穴提供低阻抗路径（ 16）。这大大减少了二次电子产生，从而降低了寄生PNP双极器件的增益。减少的再生反过来提高了临界场值，从而提高了安全操作面积。

10. 发明申请

US20050248027A1 Circuit structure integrating the power distribution functions of circuits and leadframes into the chip surface 有权
公开(公告)号：US20050248027A1
公开(公告)日：2005-11-10
申请号：US11154190
申请日：2005-06-16
申请人： Taylor Efland
发明人： Taylor Efland
IPC分类号： H01L21/60 , H01L23/31 , H01L23/50 , H01L23/528 , H01L23/34
CPC分类号： H01L24/05 , H01L23/3171 , H01L23/50 , H01L23/5286 , H01L24/03 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48624 , H01L2224/48639 , H01L2224/48644 , H01L2224/48664 , H01L2224/48669 , H01L2224/48724 , H01L2224/48739 , H01L2224/48764 , H01L2224/48769 , H01L2224/48839 , H01L2224/48844 , H01L2224/48864 , H01L2224/49 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01032 , H01L2924/01042 , H01L2924/01043 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01083 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/10253 , H01L2924/10329 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/20752 , H01L2924/00 , H01L2224/48824 , H01L2224/48869 , H01L2224/48744 , H01L2924/20753
摘要： An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by conductors to segments of the leadframe. The network relocates most of the conventional power distribution interconnections from the circuit level to the newly created surface network, thus saving substantial amounts of silicon real estate and permitting shrinkage of the IC area. The network is electrically connected to selected active components by metal-filled vias; since these vias can easily be redesigned to other locations, IC designers gain a new degree of design freedom. The network relocates most of the bond pads dedicated to power supply from the conventional alignment along the chip periphery onto the newly created bondable lines, saving substantial additional amounts of silicon real estate, and freeing the bonding machines from their extremely tight connector placement and attachment rules to much more relaxed bonding programs. The network is deposited and patterned in wafer processing as a sequence of metal layers specifically suited for providing power current and electrical ground potential. The network has attachable outermost metal surface and is laid out so that network portions form pads convenient for attaching balls of bonding wires or solder.

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