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1. 发明申请

US20070033556A1 Edge recognition based high voltage pseudo layer verification methodology for mix signal design layout 有权
标题翻译：基于边缘识别的高电压伪层验证方法，用于混合信号设计布局
公开(公告)号：US20070033556A1
公开(公告)日：2007-02-08
申请号：US11199337
申请日：2005-08-08
申请人： Lily Springer , Haim Horovitz , Robert Shaw , Sameer Pendharkar , Wen-Hwa Chu , Paul Mannas
发明人： Lily Springer , Haim Horovitz , Robert Shaw , Sameer Pendharkar , Wen-Hwa Chu , Paul Mannas
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Validation of at least some of a proposed semiconductor design layout is disclosed. According to one or more aspects of the present invention, a first voltage dependent design rule is applied to an edge of an area of the layout if the edge is not covered by a pseudo layer. A second voltage dependent design rule is, on the other hand, applied to the edge of the area if the edge is covered by the pseudo layer.
摘要翻译：公开了所提出的半导体设计布局中的至少一些的验证。根据本发明的一个或多个方面，如果边缘未被伪层覆盖，则将第一电压依赖设计规则应用于布局区域的边缘。另一方面，如果边缘被伪层覆盖，则第二电压依赖设计规则被应用于该区域的边缘。

2. 发明申请

US20060189089A1 Integrated high voltage capacitor having capacitance uniformity structures and a method of manufacture therefor 有权
标题翻译：具有电容均匀结构的集成高压电容器及其制造方法
公开(公告)号：US20060189089A1
公开(公告)日：2006-08-24
申请号：US11250047
申请日：2005-10-13
申请人： David Larkin , Lily Springer , Makoto Takemura , Ashish Gokhale , Dhaval Saraiya
发明人： David Larkin , Lily Springer , Makoto Takemura , Ashish Gokhale , Dhaval Saraiya
IPC分类号： H02M3/335 , H01L21/20 , H01L29/00
CPC分类号： H01L27/0688 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a semiconductor substrate (105), and an insulator (130) located over the first capacitor plate (120), at least a portion of the insulator (130) comprising an interlevel dielectric layer (135, 138, 143, or 148). The integrated high voltage capacitor further includes capacitance uniformity structures (910) located at least partially within the insulator (130) and a second capacitor plate (160) located over the insulator (130).
摘要翻译：本发明提供一种集成的高压电容器，因此制造方法以及包括该高压电容器的集成电路芯片。集成的高压电容器以及其它特征包括位于半导体衬底（105）上方或半导体衬底（105）中的第一电容器板（120）和位于第一电容器板（120）上方的绝缘体（130），至少一部分所述绝缘体（130）包括层间介电层（135,138,143或148）。集成高压电容器还包括至少部分位于绝缘体（130）内的电容均匀性结构（910）和位于绝缘体（130）上方的第二电容器板（160）。

3. 发明授权

US06958269B2 Memory device with reduced cell size 有权
标题翻译：具有减小的单元大小的存储器件
公开(公告)号：US06958269B2
公开(公告)日：2005-10-25
申请号：US10178100
申请日：2002-06-24
申请人： Josef Czeslaw Mitros , Imran Khan , Lily Springer
发明人： Josef Czeslaw Mitros , Imran Khan , Lily Springer
IPC分类号： H01L21/28 , H01L29/423 , H01L21/236 , H01L29/745
CPC分类号： H01L29/42324 , H01L21/28273
摘要： A method for manufacturing a memory device includes forming an oxide layer adjacent a substrate. A floating gate layer is formed and disposed outwardly from the oxide layer. A dielectric layer is formed, such that it is disposed outwardly from the floating gate layer. Then, a conductive material layer is formed and disposed outwardly from the dielectric layer, wherein the conductive material layer forms a control gate that is substantially isolated from the floating gate layer by the dielectric layer.
摘要翻译：一种用于制造存储器件的方法包括在衬底附近形成氧化物层。形成浮栅，并从氧化物层向外设置。形成介电层，使得其从浮栅层向外设置。然后，形成导电材料层并从电介质层向外设置导电材料层，其中导电材料层形成通过介电层基本上与浮动栅极隔离的控制栅极。

4. 发明申请

US20050045948A1 Single poly-emitter PNP using DWELL diffusion in a BiCMOS technology 有权
公开(公告)号：US20050045948A1
公开(公告)日：2005-03-03
申请号：US10650621
申请日：2003-08-28
申请人： Lily Springer
发明人： Lily Springer
IPC分类号： H01L21/331 , H01L21/8249 , H01L29/08 , H01L29/735 , H01L29/94 , H01L29/76 , H01L31/062
CPC分类号： H01L29/6625 , H01L21/8249 , H01L29/0808 , H01L29/735
摘要： A method of forming a bipolar transistor device, and more particularly a vertical poly-emitter PNP transistor, as part of a BiCMOS type manufacturing process is disclosed. The formation of the PNP transistor during a CMOS/DMOS fabrication process requires merely one additional mask to facilitate formation of a very small emitter in a portion of an N-type surface layer of a double diffused well (DWELL). Unlike conventional PNP transistors, a separate mask is not required to establish the base of the transistor as the transistor base is formed from a portion of the double diffused well and the DWELL includes a P-type body layer formed via implantation through the same opening in the same mask utilized to establish the N-type surface layer of the double diffused well. The base is also thin thus improving the transistor's frequency and gain.

5. 发明授权

US06747308B2 Single poly EEPROM with reduced area 有权
标题翻译：单个多重EEPROM，减少面积
公开(公告)号：US06747308B2
公开(公告)日：2004-06-08
申请号：US10334319
申请日：2002-12-30
申请人： Jozef C. Mitros , Lily Springer , Roland Bucksch
发明人： Jozef C. Mitros , Lily Springer , Roland Bucksch
IPC分类号： H01L29788
CPC分类号： H01L29/7885 , G11C2216/10 , H01L27/115 , H01L29/42324
摘要： An EEPROM (100) comprises a source region (122), a drain region (120); and a polysilicon layer (110). The polysilicon layer (110) comprises a floating gate comprising at least one polysilicon finger (112A-112E) operatively coupling the source region (122) and drain region (120) and a control gate comprising at least one of the polysilicon fingers (112A-112E) capacitively coupled to the floating gate. The EEPROM (100) has a substantially reduce area compared to prior art EEPROM since an n-well region is eliminated.
摘要翻译： EEPROM（100）包括源区（122），漏区（120）; 和多晶硅层（110）。多晶硅层（110）包括浮动栅极，其包括可操作地耦合源极区域（122）和漏极区域（120）的至少一个多晶硅指状物（112A-112E）和包括至少一个多晶硅指状物（112A- 112E）电容耦合到浮动栅极。与现有技术的EEPROM相比，EEPROM（100）具有大大减小的面积，因为消除了n阱区域。

6. 发明授权

US06716709B1 Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps 有权
标题翻译：形成有栅格或岛状注入掩模的晶体管，以形成减少的扩散深度区域，而无需额外的掩模和工艺步骤
公开(公告)号：US06716709B1
公开(公告)日：2004-04-06
申请号：US10335322
申请日：2002-12-31
申请人： Lily Springer , Jeff Smith , Sheldon Haynie , Joe R. Trogolo
发明人： Lily Springer , Jeff Smith , Sheldon Haynie , Joe R. Trogolo
IPC分类号： H01L21336
CPC分类号： H01L29/66272 , H01L21/266 , H01L21/74 , H01L21/8249 , H01L29/0821 , H01L29/7322
摘要： A method of forming two regions having differing depths using a single implantation process is provided. A mask having two openings associated therewith is formed over a semiconductor body, wherein one of the openings has a size larger than an implantation design rule, and the other opening has a size smaller than the design rule. An implant is performed into the semiconductor body through the implant mask, resulting in two distinct doped regions, wherein the region associated with the larger opening has more dopant than the region associated with the smaller opening. Subsequent activation and thermal processing results in the one region diffusing a greater amount than the second region, thereby resulting in two regions formed concurrently having different depths.
摘要翻译：提供了使用单个注入工艺形成具有不同深度的两个区域的方法。具有与其相关联的两个开口的掩模形成在半导体本体上，其中一个开口具有大于植入设计规则的尺寸，另一个开口的尺寸小于设计规则。通过注入掩模对半导体本体进行注入，产生两个不同的掺杂区域，其中与较大开口相关联的区域具有比与较小开口相关的区域更多的掺杂剂。随后的激活和热处理导致一个区域扩散比第二区域更大的量，从而导致形成为同时具有不同深度的两个区域。

7. 发明授权

US08664080B2 Vertical ESD protection device 有权
标题翻译：垂直ESD保护装置
公开(公告)号：US08664080B2
公开(公告)日：2014-03-04
申请号：US13477792
申请日：2012-05-22
申请人： Toshiyuki Tani , Hiroshi Yamasaki , Kentaro Takahashi , Lily Springer
发明人： Toshiyuki Tani , Hiroshi Yamasaki , Kentaro Takahashi , Lily Springer
IPC分类号： H01L29/06
CPC分类号： H01L27/0259 , H01L21/76224 , H01L23/60 , H01L24/05 , H01L29/861 , H01L2224/02166 , H01L2924/12036 , H01L2924/1305 , H01L2924/1461 , H01L2924/00
摘要： A method for forming a vertical electrostatic discharge (ESD) protection device includes depositing a multi-layer n-type epitaxial layer on a substrate having p-type surface including first epitaxial depositing to form a first n-type epitaxial layer on the p-type surface, and second epitaxial depositing to form a second n-type epitaxial layer formed on the first n-type epitaxial layer. The first type epitaxial layer has a peak doping level which is at least double that of the second n-type epitaxial layer. A p+ layer is formed on the second n-type epitaxial layer. An etch step etches through the p+ layer and multi-layer n-type epitaxial layer to reach the substrate to form a trench. The trench is filled with a filler material to form a trench isolation region. A metal contact is formed on the p+ layer for providing contact to the p+ layer.
摘要翻译：一种用于形成垂直静电放电（ESD）保护装置的方法包括在具有包括第一外延沉积的p型表面的衬底上沉积多层n型外延层，以在p型上形成第一n型外延层表面和第二外延沉积以形成形成在第一n型外延层上的第二n型外延层。第一类型外延层具有至少是第二n型外延层的两倍的峰值掺杂水平。在第二n型外延层上形成p +层。蚀刻步骤通过p +层和多层n型外延层蚀刻到达衬底以形成沟槽。沟槽填充有填充材料以形成沟槽隔离区域。在p +层上形成金属接触以提供与p +层的接触。

8. 发明申请

US20060186450A1 Integrated high voltage capacitor and a method of manufacture therefor 审中-公开
标题翻译：集成式高压电容器及其制造方法
公开(公告)号：US20060186450A1
公开(公告)日：2006-08-24
申请号：US11249535
申请日：2005-10-13
申请人： David Larkin , Lily Springer , Makoto Takemura , Ashish Gokhale , Dhaval Saraiya
发明人： David Larkin , Lily Springer , Makoto Takemura , Ashish Gokhale , Dhaval Saraiya
IPC分类号： H01L29/94
CPC分类号： H01L29/94
摘要： The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a semiconductor substrate (105), and an insulator (130) located over the first capacitor plate (120), at least a portion of the insulator (130) comprising an interlevel dielectric layer (135, 138, 143, or 148). The integrated high voltage capacitor further includes a second capacitor plate (160) located over the insulator (130).
摘要翻译：本发明提供了一种集成的高压电容器，因此制造方法和包括其的集成电路芯片。集成的高压电容器以及其它特征包括位于半导体衬底（105）上方或半导体衬底（105）中的第一电容器板（120）和位于第一电容器板（120）上方的绝缘体（130），至少一部分绝缘体（130）包括层间介电层（135,138,143或148）。集成高压电容器还包括位于绝缘体（130）上方的第二电容器板（160）。

9. 发明授权

US07164174B2 Single poly-emitter PNP using dwell diffusion in a BiCMOS technology 有权
标题翻译：在BiCMOS技术中使用驻留扩散的单多晶硅PNP
公开(公告)号：US07164174B2
公开(公告)日：2007-01-16
申请号：US11191788
申请日：2005-07-28
申请人： Lily Springer
发明人： Lily Springer
IPC分类号： H01L29/732
CPC分类号： H01L29/6625 , H01L21/8249 , H01L29/0808 , H01L29/735
摘要： A method of forming a bipolar transistor device, and more particularly a vertical poly-emitter PNP transistor, as part of a BiCMOS type manufacturing process is disclosed. The formation of the PNP transistor during a CMOS/DMOS fabrication process requires merely one additional mask to facilitate formation of a very small emitter in a portion of an N-type surface layer of a double diffused well (DWELL). Unlike conventional PNP transistors, a separate mask is not required to establish the base of the transistor as the transistor base is formed from a portion of the double diffused well and the DWELL includes a P-type body layer formed via implantation through the same opening in the same mask utilized to establish the N-type surface layer of the double diffused well. The base is also thin thus improving the transistor's frequency and gain.
摘要翻译：公开了作为BiCMOS型制造工艺的一部分的双极晶体管器件，特别是垂直多晶硅发射极PNP晶体管的形成方法。在CMOS / DMOS制造工艺期间，PNP晶体管的形成仅需要一个附加的掩模，以便于在双扩散阱的N型表面层（DWELL）的一部分中形成非常小的发射极。与常规PNP晶体管不同，由于晶体管基极由双扩散阱的一部分形成，所以不需要单独的掩模来建立晶体管的基极，并且DWELL包括通过相同开口的相同开口形成的P型体层用于建立双扩散井的N型表面层的相同掩模。基极也很薄，从而提高晶体管的频率和增益。

10. 发明授权

US06949424B2 Single poly-emitter PNP using DWELL diffusion in a BiCMOS technology 有权
标题翻译：在BiCMOS技术中使用DWELL扩散的单个多发射体PNP
公开(公告)号：US06949424B2
公开(公告)日：2005-09-27
申请号：US10650621
申请日：2003-08-28
申请人： Lily Springer
发明人： Lily Springer
IPC分类号： H01L21/331 , H01L21/8249 , H01L29/08 , H01L29/735 , H01L21/8238
CPC分类号： H01L29/6625 , H01L21/8249 , H01L29/0808 , H01L29/735
摘要： A method of forming a bipolar transistor device, and more particularly a vertical poly-emitter PNP transistor, as part of a BiCMOS type manufacturing process is disclosed. The formation of the PNP transistor during a CMOS/DMOS fabrication process requires merely one additional mask to facilitate formation of a very small emitter in a portion of an N-type surface layer of a double diffused well (DWELL). Unlike conventional PNP transistors, a separate mask is not required to establish the base of the transistor as the transistor base is formed from a portion of the double diffused well and the DWELL includes a P-type body layer formed via implantation through the same opening in the same mask utilized to establish the N-type surface layer of the double diffused well. The base is also thin thus improving the transistor's frequency and gain.
摘要翻译：公开了作为BiCMOS型制造工艺的一部分的双极晶体管器件，特别是垂直多晶硅发射极PNP晶体管的形成方法。在CMOS / DMOS制造工艺期间，PNP晶体管的形成仅需要一个附加的掩模，以便于在双扩散阱的N型表面层（DWELL）的一部分中形成非常小的发射极。与常规PNP晶体管不同，由于晶体管基极由双扩散阱的一部分形成，所以不需要单独的掩模来建立晶体管的基极，并且DWELL包括通过相同开口的相同开口形成的P型体层用于建立双扩散井的N型表面层的相同掩模。基极也很薄，从而提高晶体管的频率和增益。

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