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1. 发明申请

US20050260510A1 Method for determining the relative positional accuracy of two structure elements on a wafer 有权
标题翻译：用于确定晶片上两个结构元件的相对位置精度的方法
公开(公告)号：US20050260510A1
公开(公告)日：2005-11-24
申请号：US10950165
申请日：2004-09-24
申请人： Heiko Hommen , Jens Stacker , Maria de la Piedad Fernandez-Martinez , Jens Bruch , Thorsten Schedel
发明人： Heiko Hommen , Jens Stacker , Maria de la Piedad Fernandez-Martinez , Jens Bruch , Thorsten Schedel
IPC分类号： G03F7/20 , G03F9/00 , H01L21/66 , H01L23/544 , G03C5/00
CPC分类号： G03F7/70633 , H01L22/34 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A measurement mark (3) for determining the relative positional accuracy of a progressive projection onto a wafer (5), the projection being performed with two masks (3, 4), comprising two structure elements (10, 20) formed on a respective one of the masks (1, 2). The structure elements (10, 20) overlap with regard to their position on the masks so that, during the projection of the second structure element (20), an electrically conductive structure (30) formed on the basis of the first structure element on the wafer (5) is overformed by removal of a portion (31). In an electrical line width measurement, the reduced width (CD, CD30a) of the structure (30) is measured and compared either with the original width (62) or with that width (CD30b) of a further partial element (30b) produced by the overforming.
摘要翻译：一种用于确定在晶片（5）上的逐行投影的相对位置精度的测量标记（3），所述投影由两个掩模（3,4）执行，包括形成在相应的一个上的两个结构元件（10,20）的面罩（1,2）。结构元件（10,20）关于它们在掩模上的位置重叠，使得在第二结构元件（20）的突出期间，形成在第一结构元件的基础上的导电结构（30）晶片（5）通过去除部分（31）而变形。在电线宽度测量中，测量结构（30）的减小的宽度（CD，CD'30a），并将其与原始宽度（62）或与该宽度（CD < 30b）通过过度成形而产生的另一部分元件（30b）。

2. 发明授权

US07186484B2 Method for determining the relative positional accuracy of two structure elements on a wafer 有权
标题翻译：用于确定晶片上两个结构元件的相对位置精度的方法
公开(公告)号：US07186484B2
公开(公告)日：2007-03-06
申请号：US10950165
申请日：2004-09-24
申请人： Heiko Hommen , Jens Stäcker , Maria de la Piedad Fernandez-Martinez , Jens Uwe Bruch , Thorsten Schedel
发明人： Heiko Hommen , Jens Stäcker , Maria de la Piedad Fernandez-Martinez , Jens Uwe Bruch , Thorsten Schedel
IPC分类号： G03F9/00
CPC分类号： G03F7/70633 , H01L22/34 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A measurement mark (3) for determining the relative positional accuracy of a progressive projection onto a wafer (5), the projection being performed with two masks (3, 4), comprising two structure elements (10, 20) formed on a respective one of the masks (1, 2). The structure elements (10, 20) overlap with regard to their position on the masks so that, during the projection of the second structure element (20), an electrically conductive structure (30) formed on the basis of the first structure element on the wafer (5) is overformed by removal of a portion (31). In an electrical line width measurement, the reduced width (CD, CD30a) of the structure (30) is measured and compared either with the original width (62) or with that width (CD30b) of a further partial element (30b) produced by the overforming.
摘要翻译：一种用于确定在晶片（5）上的逐行投影的相对位置精度的测量标记（3），所述投影由两个掩模（3,4）执行，包括形成在相应的一个上的两个结构元件（10,20）的面罩（1,2）。结构元件（10,20）关于它们在掩模上的位置重叠，使得在第二结构元件（20）的突出期间，形成在第一结构元件的基础上的导电结构（30）晶片（5）通过去除部分（31）而变形。在电线宽度测量中，测量结构（30）的减小的宽度（CD，CD'30a），并将其与原始宽度（62）或与该宽度（CD < 30b）通过过度成形而产生的另一部分元件（30b）。

3. 发明授权

US06979522B2 Method for exposing at least one or at least two semiconductor wafers 失效
标题翻译：用于暴露至少一个或至少两个半导体晶片的方法
公开(公告)号：US06979522B2
公开(公告)日：2005-12-27
申请号：US10635583
申请日：2003-08-06
申请人： Heiko Hommen , Ralf Otto , Thorsten Schedel , Sebastian Schmidt , Thomas Fischer
发明人： Heiko Hommen , Ralf Otto , Thorsten Schedel , Sebastian Schmidt , Thomas Fischer
IPC分类号： G03F7/20 , G03F9/00 , H01L21/027 , G03C5/00
CPC分类号： G03F7/70633 , G03F9/7046
摘要： A batch of semiconductor wafers are exposed after an alignment in a wafer stepper or scanner and each of their alignment parameters are determined. Using, e.g., a linear formula with tool specific coefficients, the overlay accuracy can be calculated from these alignment parameters in advance with a high degree of accuracy as if a measurement with an overlay inspection tool had been performed. The exposure tool-offset can be adjusted on a wafer-to-wafer basis to correct for the derived overlay inaccuracy. Moreover, the alignment parameters for a specific wafer can be used to change the tool-offset for the same wafer prior to exposure. The required inspection tool capacity is advantageously reduced, the wafer rework decreases, and time is saved to perform the exposure step.
摘要翻译：一批半导体晶片在晶片步进器或扫描仪中对齐后进行曝光，并确定其每个对准参数。使用例如具有刀具特定系数的线性公式，可以以高精确度的方式从这些对准参数中预先计算覆盖精度，如同已经执行了覆盖检查工具的测量一样。可以在晶圆到晶圆的基础上调整曝光工具偏移量，以校正衍生的叠加误差。此外，特定晶片的对准参数可用于在曝光之前改变相同晶片的刀具偏移。所需的检查工具容量有利地减少，晶片返工减少，并节省时间以执行曝光步骤。

4. 发明授权

US06684124B2 Method for controlling a processing device for a sequential processing of semiconductor wafers 有权
标题翻译：用于控制用于半导体晶片的顺序处理的处理装置的方法
公开(公告)号：US06684124B2
公开(公告)日：2004-01-27
申请号：US10134106
申请日：2002-04-29
申请人： Thorsten Schedel , Karl Schumacher , Thomas Fischer , Heiko Hommen , Ralf Otto , Sebastian Schmidt
发明人： Thorsten Schedel , Karl Schumacher , Thomas Fischer , Heiko Hommen , Ralf Otto , Sebastian Schmidt
IPC分类号： G06F1900
CPC分类号： G03F7/70525 , G03F7/70625 , G03F7/70633 , H01L22/20
摘要： While a first leading semiconductor wafer (11) already processed in a process appliance (1) and belonging to a batch is being measured in a microscope measuring instrument (2) in relation to values for the structure parameters 30, a second or further semiconductor wafer (12) belonging to the batch is processed in the process appliance (1). An event signal (100) reports, for example, an inspection carried out successfully of the first wafer, so that the following wafers (12) no longer need to be inspected. Using the measured results, the process parameters (31) of the process appliance (1) are automatically readjusted. Events such as maintenance work or parameter drifts in trend maps etc. are detected in control units (8 or 9) and, via the output of an event signal (102), for example in an event database (40), lead to the event-based selection of structure parameters (30′) to be measured and/or to the initiation of a leading wafer (11). Limiting-value violations (21) of at least one process parameter (31), detected by a control unit (8), are responded to by a warning signal (101) and likewise fed into the event database (40).
摘要翻译：虽然已经在处理器具（1）中处理并属于批次的第一个领先的半导体晶片（11）在显微镜测量仪器（2）中相对于结构参数30的值被测量，第二或另外的半导体晶片（12）在处理器具（1）中进行处理。事件信号（100）报告例如第一晶片成功执行的检查，使得不再需要检查以下晶片（12）。使用测量结果，自动重新调整过程设备（1）的过程参数（31）。在控制单元（8或9）中检测诸如维护工作或趋势图中参数漂移的事件，并且例如在事件数据库（40）中，通过事件信号（102）的输出导致事件对待测量的结构参数（30'）和/或引导晶片（11）的启动进行选择。由控制单元（8）检测到的至少一个处理参数（31）的限制值违反（21）由警告信号（101）响应，并且同样馈送到事件数据库（40）中。

5. 发明授权

US06780552B2 Method for controlling the quality of a lithographic structuring step 失效
标题翻译：用于控制光刻结构步骤质量的方法
公开(公告)号：US06780552B2
公开(公告)日：2004-08-24
申请号：US10175591
申请日：2002-06-19
申请人： Thorsten Schedel , Jens Zimmermann , Sebastian Schmidt
发明人： Thorsten Schedel , Jens Zimmermann , Sebastian Schmidt
IPC分类号： G03F900
CPC分类号： G03F7/70625 , G03F7/70633 , H01L22/20
摘要： After exposing a semiconductor wafer, quality parameters, for example, the critical dimension, the overlay accuracy, and alignment parameters, etc. are measured in successive inspections and are compared with tolerance range widths that are specified dynamically by calculating the range from measured values of one or more of the other quality parameters. For example, the tolerance range width for the overlay accuracy can be increased for smaller measured critical dimension values of the same structures without affecting the functionality of the integrated circuit. Using a forward mechanism, the tolerance ranges can also be adjusted with the quality parameter measurements from a first layer to the quality parameter tolerance range width of a second layer.
摘要翻译：在暴露半导体晶片之后，在连续检查中测量质量参数，例如临界尺寸，覆盖精度和对准参数等，并与通过计算从一个或多个其他质量参数。例如，对于相同结构的较小测量临界尺寸值，可以增加覆盖精度的公差范围宽度，而不会影响集成电路的功能。使用向前机构，也可以通过从第一层到第二层的质量参数公差范围宽度的质量参数测量来调整公差范围。

6. 发明授权

US10031409B2 Reflective photomask and reflection-type mask blank 有权
公开(公告)号：US10031409B2
公开(公告)日：2018-07-24
申请号：US15179775
申请日：2016-06-10
申请人： Markus Bender , Thorsten Schedel
发明人： Markus Bender , Thorsten Schedel
IPC分类号： G03F1/24 , G03F1/22 , G03F1/38
摘要： A reflective photomask includes a substrate with a substrate layer of a low thermal expansion material. The substrate layer includes a main portion of a first structural configuration and an auxiliary portion of a second structural configuration of the low thermal expansion material. The auxiliary portion is formed in a frame section surrounding a pattern section of the substrate. A multilayer mirror is formed on a first surface of the substrate. A reflectivity of the multilayer mirror is at least 50% at an exposure wavelength below 15 nm. A frame trench extending through the multilayer mirror exposes the substrate in the frame section. The auxiliary portion may include scatter centers for out-of-band radiation.

7. 发明申请

US20170108766A1 REFLECTIVE PHOTOMASK AND REFLECTION-TYPE MASK BLANK 审中-公开
公开(公告)号：US20170108766A1
公开(公告)日：2017-04-20
申请号：US15179775
申请日：2016-06-10
申请人： Markus Bender , Thorsten Schedel
发明人： Markus Bender , Thorsten Schedel
IPC分类号： G03F1/24
CPC分类号： G03F1/24 , G03F1/38
摘要： A reflective photomask includes a substrate with a substrate layer of a low thermal expansion material. The substrate layer includes a main portion of a first structural configuration and an auxiliary portion of a second structural configuration of the low thermal expansion material. The auxiliary portion is formed in a frame section surrounding a pattern section of the substrate. A multilayer mirror is formed on a first surface of the substrate. A reflectivity of the multilayer mirror is at least 50% at an exposure wavelength below 15 nm. A frame trench extending through the multilayer mirror exposes the substrate in the frame section. The auxiliary portion may include scatter centres for out-of-band radiation.

8. 发明授权

US06593254B2 Method for clamping a semiconductor device in a manufacturing process 有权
公开(公告)号：US06593254B2
公开(公告)日：2003-07-15
申请号：US10112271
申请日：2002-03-28
申请人： Manfred Kraxenberger , Ines Thümmel , Bruno Spuler , Thorsten Schedel , Karl Mautz
发明人： Manfred Kraxenberger , Ines Thümmel , Bruno Spuler , Thorsten Schedel , Karl Mautz
IPC分类号： H01L2144
CPC分类号： H01L21/302 , Y10S438/928
摘要： There is disclosed a method for clamping a semiconductor wafer, preferably suitable for a wafer with a diameter of 300 mm or larger. After depositing at least one encapsulating material layer over the front side and backside of the wafer, the material layer over the front side of the wafer is etched selectively to form a predetermined structure in following process steps. Wafer warpage is caused as a result of unequal wafer bowing stress of the material layer. By removing the material layer over the backside of the wafer partially or completely in accordance with the desired reduction of the bowing stress wafer warpage is reduced. In a further course of the manufacturing process, the semiconductor device is clamped electrostatically, physically or by use of vacuum.

9. 发明申请

US20090166848A1 Method for Enhancing the Adhesion of a Passivation Layer on a Semiconductor Device 审中-公开
标题翻译：用于增强半导体器件上的钝化层的附着力的方法
公开(公告)号：US20090166848A1
公开(公告)日：2009-07-02
申请号：US11967165
申请日：2007-12-29
申请人： Volker Berghof , Thorsten Schedel
发明人： Volker Berghof , Thorsten Schedel
IPC分类号： H01L23/12 , H01L21/44
CPC分类号： H01L23/5283 , H01L23/525 , H01L24/02 , H01L2924/01079 , H01L2924/14
摘要： In a method for making a semiconductor component, an integrated circuit is provided with a chip pad on an active side. A conductive track is connected to the chip pad and a passivation layer covers the conductive track. Forming the conductive track includes structuring an uneven sidewall for form closure with the passivation layer.
摘要翻译：在制造半导体部件的方法中，集成电路在主动侧设置有芯片焊盘。导电轨道连接到芯片焊盘，钝化层覆盖导电轨道。形成导电轨道包括构造不平坦的侧壁以与钝化层形成闭合。

10. 发明授权

US06908775B2 Method for performing an alignment measurement of two patterns in different layers on a semiconductor wafer 失效
标题翻译：用于在半导体晶片上执行不同层中的两个图案的对准测量的方法
公开(公告)号：US06908775B2
公开(公告)日：2005-06-21
申请号：US10713690
申请日：2003-11-14
申请人： Rolf Heine , Sebastian Schmidt , Thorsten Schedel
发明人： Rolf Heine , Sebastian Schmidt , Thorsten Schedel
IPC分类号： G03F7/20 , G03F9/00 , G06T7/00 , H01L21/027 , H01L21/66 , G01R31/26
CPC分类号： G03F7/70633 , G03F9/7046 , G03F9/7076 , G06T7/0002 , G06T7/0004 , G06T7/33 , G06T2207/30148
摘要： In an alignment or overlay measurement of patterns on a semiconductor wafer an error that occurs during the measurement in one of a predefined number of alignment structures in an exposure field of a corresponding predefined set of exposure fields can be handled by selecting an alignment structure in a substitute exposure field. The latter exposure field need not be part of the predefined set of exposure fields, that is, an inter-field change may be effected. The number of alignment measurements on a wafer remains constant and the quality is increased. Alternatively, when using another alignment structure in the same exposure field—by effecting an intra-field change—the method becomes particularly advantageous when different minimum structure sizes are considered for the substitute targets. Due to the different selectivity in, say, a previous CMP process, such targets might not erode and do not cause an error in a measurement, thus providing an increased alignment or overlay quality.
摘要翻译：在半导体晶片上的图案的对准或覆盖测量中，可以通过选择一个对准结构中的一个对准结构来处理在相应的预定曝光区域的曝光区域中的预定数量的对准结构之一中的测量期间发生的误差替代曝光领域。后一曝光场不需要是预定义的一组曝光场的一部分，也就是说可以实现场间变化。晶片上的对准测量数量保持不变，并且质量得到提高。或者，当在相同的曝光场中使用另一对准结构时，通过进行场内变化，当替代目标考虑不同的最小结构尺寸时，该方法变得特别有利。由于在先前的CMP过程中具有不同的选择性，所以这样的目标可能不会被侵蚀，并且不会在测量中引起误差，从而提供更高的对准或覆盖质量。

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