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1. 发明申请

US20080307150A1 Optimized Switching Method 有权
标题翻译：优化切换方法
公开(公告)号：US20080307150A1
公开(公告)日：2008-12-11
申请号：US12196025
申请日：2008-08-21
申请人： Heath Stewart , Chris Haywood , Mike De la Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
发明人： Heath Stewart , Chris Haywood , Mike De la Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
IPC分类号： G06F13/14
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.
摘要翻译：公开了一种总线优化技术。根据总线优化技术，从交换机的端口单元中删除输出缓冲器和输出逻辑，并将其包含在开关中的控制矩阵中。在多个端口单元的第一端口单元中接收的数据单元被提供给控制矩阵。控制矩阵评估何时将数据单元发送到第二个端口单元。在第二个端口单元中不作出输出决定。

2. 发明授权

US07426602B2 Switch for bus optimization 有权
标题翻译：切换总线优化
公开(公告)号：US07426602B2
公开(公告)日：2008-09-16
申请号：US11031420
申请日：2005-01-07
申请人： Heath Stewart , Chris Haywood , Mike de la Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
发明人： Heath Stewart , Chris Haywood , Mike de la Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
IPC分类号： G06F13/14 , G06F3/00
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.
摘要翻译：公开了一种总线优化技术。根据总线优化技术，从交换机的端口单元中删除输出缓冲器和输出逻辑，并将其包含在开关中的控制矩阵中。在多个端口单元的第一端口单元中接收的数据单元被提供给控制矩阵。控制矩阵评估何时将数据单元发送到第二个端口单元。在第二个端口单元中不作出输出决定。

3. 发明授权

US07590791B2 Optimized switching method 有权
标题翻译：优化切换方式
公开(公告)号：US07590791B2
公开(公告)日：2009-09-15
申请号：US12196025
申请日：2008-08-21
申请人： Heath Stewart , Chris Haywood , Michael De La Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
发明人： Heath Stewart , Chris Haywood , Michael De La Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
IPC分类号： G06F13/14 , G06F3/00
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.
摘要翻译：公开了一种总线优化技术。根据总线优化技术，从交换机的端口单元中删除输出缓冲器和输出逻辑，并将其包含在开关中的控制矩阵中。在多个端口单元的第一端口单元中接收的数据单元被提供给控制矩阵。控制矩阵评估何时将数据单元发送到第二个端口单元。在第二个端口单元中不作出输出决定。

4. 发明申请

US20050154804A1 Switch for bus optimization 有权
标题翻译：切换总线优化
公开(公告)号：US20050154804A1
公开(公告)日：2005-07-14
申请号：US11031420
申请日：2005-01-07
申请人： Heath Stewart , Chris Haywood , Michael De La Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
发明人： Heath Stewart , Chris Haywood , Michael De La Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
IPC分类号： G06F3/00 , G06F13/14 , G06F13/40
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.
摘要翻译：公开了一种总线优化技术。根据总线优化技术，从交换机的端口单元中删除输出缓冲器和输出逻辑，并将其包含在开关中的控制矩阵中。在多个端口单元的第一端口单元中接收的数据单元被提供给控制矩阵。控制矩阵评估何时将数据单元发送到第二个端口单元。在第二个端口单元中没有作出输出决定。

5. 发明授权

US07990987B2 Network processor having bypass capability 有权
标题翻译：网络处理器具有旁路功能
公开(公告)号：US07990987B2
公开(公告)日：2011-08-02
申请号：US10374214
申请日：2003-02-25
申请人： Thomas C Reiner , Kirk Jong , Phil Terry , Neely Walls , Chris Haywood , Michael de la Garrigue , Adam Rappoport
发明人： Thomas C Reiner , Kirk Jong , Phil Terry , Neely Walls , Chris Haywood , Michael de la Garrigue , Adam Rappoport
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L47/245 , H04L47/70 , H04L47/724 , H04L49/25 , H04L49/3009
摘要： A network processor having bypass capability in which some data units are diverted from being processed by the processor core of the network processor. In one embodiment, a network processor may include a receiver to receive data units, configuration information used to evaluate whether the data units require processing, a processor core to process data units that require processing, a bypass store to hold those data units which do not require processing by the processor core, and a transmitter to transmit the data units. In one embodiment, a method may include receiving a plurality of data units, receiving configuration information, evaluating whether each of the data units requires processing based on the configuration information, bypassing processing those of the data units that do not require processing based on the evaluating, processing those of the data units that require processing based on the evaluating, and transmitting the data units.
摘要翻译：具有旁路能力的网络处理器，其中一些数据单元被转移到由网络处理器的处理器核心处理。在一个实施例中，网络处理器可以包括用于接收数据单元的接收器，用于评估数据单元是否需要处理的配置信息，处理器核心来处理需要处理的数据单元，旁路存储器来保存那些不需要处理的数据单元需要处理器核心的处理，以及发送器发送数据单元。在一个实施例中，一种方法可以包括接收多个数据单元，接收配置信息，评估每个数据单元是否需要基于配置信息进行处理，绕过基于评估的不需要处理的数据单元的处理，根据评估处理需要处理的数据单元的数据单元，并发送数据单元。

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