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1. 发明申请

US20070081539A1 Method For Reordering Sequenced Packets 失效
标题翻译：重新排序顺序包的方法
公开(公告)号：US20070081539A1
公开(公告)日：2007-04-12
申请号：US11610447
申请日：2006-12-13
申请人： Nadim Shaikli
发明人： Nadim Shaikli
IPC分类号： H04L12/56
CPC分类号： H04L47/34 , H04L47/10 , H04L47/286 , H04L47/50 , H04L47/564
摘要： There are disclosed a method and apparatus for reordering sequenced data packets. An expiration time is calculated for each received data packet. The expiration time and a packet sequence number are stored in a table. The table is read to determine the next data packet to be transmitted in sequence number order. The next data packet is output if available. If the next data packet is not available, a true expiration time is determined for the unavailable next data packet. If the unavailable next data packet fails to arrive before a current time is greater than the expiration time of the unavailable data packet, the unavailable next data packet is considered lost.
摘要翻译：公开了一种重新排序顺序数据包的方法和装置。为每个接收到的数据包计算一个到期时间。到期时间和分组序列号存储在表中。读取表以确定要按顺序号顺序发送的下一个数据包。如果可用，则输出下一个数据包。如果下一个数据包不可用，则确定不可用的下一个数据包的真实到期时间。如果当前时间之前不可用的下一个数据包未能到达不可用数据包的到期时间，则不可用的下一个数据包被认为丢失。

2. 发明申请

US20070260782A1 Packets transfer device having data absorbing buffers with elastic buffer capacities 有权
标题翻译：具有具有弹性缓冲能力的数据吸收缓冲器的分组传送装置
公开(公告)号：US20070260782A1
公开(公告)日：2007-11-08
申请号：US11390754
申请日：2006-03-28
申请人： Nadim Shaikli
发明人： Nadim Shaikli
IPC分类号： G06F5/00
CPC分类号： H04L47/50 , G06F13/4022 , G06F2213/0026 , H04L47/10 , H04L47/6215 , H04L47/624 , H04L47/6275 , H04L49/90 , H04L49/901 , H04L49/9052 , H04L49/9057 , H04L49/9094
摘要： In PCI-Express and alike communications systems, data bandwidth per channel can vary as a result of negotiated port bifurcation during network bring-up. Disclosed are systems and methods for adjusting FIFO depths in response to negotiated bandwidth per channel so that data absorbing FIFO's of respective channels are not arbitrarily too deep or too shallow relative to the data bandwidths of the channels the FIFO's serve.
摘要翻译：在PCI-Express和相似的通信系统中，每个通道的数据带宽可能因网络启动过程中协商的端口分岔而变化。公开了用于响应于每个通道的协商带宽来调整FIFO深度的系统和方法，使得相应信道的数据吸收FIFO相对于FIFO服务的信道的数据带宽不是任意太深或太浅。

3. 发明授权

US08255599B2 Packets transfer device having data absorbing buffers with elastic buffer capacities 有权
标题翻译：具有具有弹性缓冲能力的数据吸收缓冲器的分组传送装置
公开(公告)号：US08255599B2
公开(公告)日：2012-08-28
申请号：US11390754
申请日：2006-03-28
申请人： Nadim Shaikli
发明人： Nadim Shaikli
IPC分类号： G06F3/00 , G06F13/36
CPC分类号： H04L47/50 , G06F13/4022 , G06F2213/0026 , H04L47/10 , H04L47/6215 , H04L47/624 , H04L47/6275 , H04L49/90 , H04L49/901 , H04L49/9052 , H04L49/9057 , H04L49/9094
摘要： In PCI-Express and alike communications systems, data bandwidth per channel can vary as a result of negotiated port bifurcation during network bring-up. Disclosed are systems and methods for adjusting FIFO depths in response to negotiated bandwidth per channel so that data absorbing FIFO's of respective channels are not arbitrarily too deep or too shallow relative to the data bandwidths of the channels the FIFO's serve.
摘要翻译：在PCI-Express和相似的通信系统中，每个通道的数据带宽可能因网络启动过程中协商的端口分岔而变化。公开了用于响应于每个通道的协商带宽来调整FIFO深度的系统和方法，使得相应信道的数据吸收FIFO相对于FIFO服务的信道的数据带宽不是任意太深或太浅。

4. 发明授权

US07646780B2 System for reordering sequenced based packets in a switching network 失效
标题翻译：用于在交换网络中重新排序基于顺序的分组的系统
公开(公告)号：US07646780B2
公开(公告)日：2010-01-12
申请号：US11610451
申请日：2006-12-13
申请人： Nadim Shaikli
发明人： Nadim Shaikli
IPC分类号： H04L12/56
CPC分类号： H04L47/34 , H04L47/10 , H04L47/286 , H04L47/50 , H04L47/564
摘要： System for reordering sequenced based packets in a switching network. The system includes time stamp logic that operates to associate a receive time indicator with each received data packet. The system also includes Enqueue logic that operates to compute an expiration time for each received packet based on the receive time indicator, and stores the expiration time and the sequence identifier for each received packet into a table. Dequeue logic operates to read the table to determine the received data packets to output in an output stream so that the received data packets are output in a selected order. The Dequeue logic also operates to determine a true expiration time for one or more unreceived data packets, and if the true expiration time for a selected unreceived data packet is reached, the Dequeue logic operates to omit the selected unreceived data packet from the output stream.
摘要翻译：用于在交换网络中重新排序基于顺序的分组的系统。系统包括时间戳逻辑，其操作以将接收时间指示符与每个接收到的数据分组相关联。该系统还包括基于接收时间指示器计算每个接收到的分组的到期时间的入队逻辑，并将每个接收的分组的到期时间和序列标识符存储在表中。出队逻辑用于读取表以确定在输出流中输出的接收数据分组，使得接收到的数据分组以选定顺序输出。出队逻辑还用于确定一个或多个未接收数据分组的真实到期时间，并且如果达到所选择的未接收数据分组的真实到期时间，则出队逻辑操作以从输出流中省略所选择的未接收数据分组。

5. 发明申请

US20080307150A1 Optimized Switching Method 有权
标题翻译：优化切换方法
公开(公告)号：US20080307150A1
公开(公告)日：2008-12-11
申请号：US12196025
申请日：2008-08-21
申请人： Heath Stewart , Chris Haywood , Mike De la Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
发明人： Heath Stewart , Chris Haywood , Mike De la Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
IPC分类号： G06F13/14
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.
摘要翻译：公开了一种总线优化技术。根据总线优化技术，从交换机的端口单元中删除输出缓冲器和输出逻辑，并将其包含在开关中的控制矩阵中。在多个端口单元的第一端口单元中接收的数据单元被提供给控制矩阵。控制矩阵评估何时将数据单元发送到第二个端口单元。在第二个端口单元中不作出输出决定。

6. 发明授权

US07426602B2 Switch for bus optimization 有权
标题翻译：切换总线优化
公开(公告)号：US07426602B2
公开(公告)日：2008-09-16
申请号：US11031420
申请日：2005-01-07
申请人： Heath Stewart , Chris Haywood , Mike de la Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
发明人： Heath Stewart , Chris Haywood , Mike de la Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
IPC分类号： G06F13/14 , G06F3/00
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.
摘要翻译：公开了一种总线优化技术。根据总线优化技术，从交换机的端口单元中删除输出缓冲器和输出逻辑，并将其包含在开关中的控制矩阵中。在多个端口单元的第一端口单元中接收的数据单元被提供给控制矩阵。控制矩阵评估何时将数据单元发送到第二个端口单元。在第二个端口单元中不作出输出决定。

7. 发明授权

US07590791B2 Optimized switching method 有权
标题翻译：优化切换方式
公开(公告)号：US07590791B2
公开(公告)日：2009-09-15
申请号：US12196025
申请日：2008-08-21
申请人： Heath Stewart , Chris Haywood , Michael De La Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
发明人： Heath Stewart , Chris Haywood , Michael De La Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
IPC分类号： G06F13/14 , G06F3/00
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.
摘要翻译：公开了一种总线优化技术。根据总线优化技术，从交换机的端口单元中删除输出缓冲器和输出逻辑，并将其包含在开关中的控制矩阵中。在多个端口单元的第一端口单元中接收的数据单元被提供给控制矩阵。控制矩阵评估何时将数据单元发送到第二个端口单元。在第二个端口单元中不作出输出决定。

8. 发明申请

US20070081558A1 System For Reordering Sequenced Based Packets In A Switching Network 失效
标题翻译：用于在交换网络中重新排序基于顺序的分组的系统
公开(公告)号：US20070081558A1
公开(公告)日：2007-04-12
申请号：US11610451
申请日：2006-12-13
申请人： Nadim Shaikli
发明人： Nadim Shaikli
IPC分类号： H04J3/24
CPC分类号： H04L47/34 , H04L47/10 , H04L47/286 , H04L47/50 , H04L47/564
摘要： System for reordering sequenced based packets in a switching network. The system includes time stamp logic that operates to associate a receive time indicator with each received data packet. The system also includes Enqueue logic that operates to compute an expiration time for each received packet based on the receive time indicator, and stores the expiration time and the sequence identifier for each received packet into a table. Dequeue logic operates to read the table to determine the received data packets to output in an output stream so that the received data packets are output in a selected order. The Dequeue logic also operates to determine a true expiration time for one or more unreceived data packets, and if the true expiration time for a selected unreceived data packet is reached, the Dequeue logic operates to omit the selected unreceived data packet from the output stream.
摘要翻译：用于在交换网络中重新排序基于顺序的分组的系统。系统包括时间戳逻辑，其操作以将接收时间指示符与每个接收到的数据分组相关联。该系统还包括基于接收时间指示器计算每个接收到的分组的到期时间的入队逻辑，并将每个接收的分组的到期时间和序列标识符存储在表中。出队逻辑用于读取表以确定在输出流中输出的接收数据分组，使得接收到的数据分组以选定顺序输出。出队逻辑还用于确定一个或多个未接收数据分组的真实到期时间，并且如果达到所选择的未接收数据分组的真实到期时间，则出队逻辑操作以从输出流中省略所选择的未接收数据分组。

9. 发明申请

US20050154804A1 Switch for bus optimization 有权
标题翻译：切换总线优化
公开(公告)号：US20050154804A1
公开(公告)日：2005-07-14
申请号：US11031420
申请日：2005-01-07
申请人： Heath Stewart , Chris Haywood , Michael De La Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
发明人： Heath Stewart , Chris Haywood , Michael De La Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
IPC分类号： G06F3/00 , G06F13/14 , G06F13/40
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.
摘要翻译：公开了一种总线优化技术。根据总线优化技术，从交换机的端口单元中删除输出缓冲器和输出逻辑，并将其包含在开关中的控制矩阵中。在多个端口单元的第一端口单元中接收的数据单元被提供给控制矩阵。控制矩阵评估何时将数据单元发送到第二个端口单元。在第二个端口单元中没有作出输出决定。

10. 发明授权

US08437369B2 Packets transfer device that intelligently accounts for variable egress channel widths when scheduling use of dispatch bus by egressing packet streams 有权
标题翻译：分组传输设备，通过出口分组流调度使用调度总线时智能地考虑变量出口信道宽度
公开(公告)号：US08437369B2
公开(公告)日：2013-05-07
申请号：US11437082
申请日：2006-05-19
申请人： Nadim Shaikli
发明人： Nadim Shaikli
IPC分类号： H04J3/00
CPC分类号： H04J3/047 , H04L47/10 , H04L47/50 , H04L47/6215
摘要： In PCI-Express and alike communications systems, data bandwidth per channel can vary as a result of negotiated port aggregation and/or bifurcation during network bring-up. Disclosed are systems and methods for opportunistically interleaving dispatches of packet data for secondary egress channels when the data bandwidth of a primary egress channel is relatively small and thus creates slack on a dispatch bus between dispatches of primary data blocks.
摘要翻译：在PCI-Express和相似的通信系统中，每个通道的数据带宽可能因网络启动期间协商的端口聚合和/或分岔而变化。公开了当主出口信道的数据带宽相对较小并且因此在主数据块的分派之间在调度总线上产生松弛时，用于机会地交织用于次出口信道的分组数据分派的系统和方法。

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