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1. 发明授权

US07590791B2 Optimized switching method 有权
标题翻译：优化切换方式
公开(公告)号：US07590791B2
公开(公告)日：2009-09-15
申请号：US12196025
申请日：2008-08-21
申请人： Heath Stewart , Chris Haywood , Michael De La Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
发明人： Heath Stewart , Chris Haywood , Michael De La Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
IPC分类号： G06F13/14 , G06F3/00
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.
摘要翻译：公开了一种总线优化技术。根据总线优化技术，从交换机的端口单元中删除输出缓冲器和输出逻辑，并将其包含在开关中的控制矩阵中。在多个端口单元的第一端口单元中接收的数据单元被提供给控制矩阵。控制矩阵评估何时将数据单元发送到第二个端口单元。在第二个端口单元中不作出输出决定。

2. 发明申请

US20050154804A1 Switch for bus optimization 有权
标题翻译：切换总线优化
公开(公告)号：US20050154804A1
公开(公告)日：2005-07-14
申请号：US11031420
申请日：2005-01-07
申请人： Heath Stewart , Chris Haywood , Michael De La Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
发明人： Heath Stewart , Chris Haywood , Michael De La Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
IPC分类号： G06F3/00 , G06F13/14 , G06F13/40
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.
摘要翻译：公开了一种总线优化技术。根据总线优化技术，从交换机的端口单元中删除输出缓冲器和输出逻辑，并将其包含在开关中的控制矩阵中。在多个端口单元的第一端口单元中接收的数据单元被提供给控制矩阵。控制矩阵评估何时将数据单元发送到第二个端口单元。在第二个端口单元中没有作出输出决定。

3. 发明授权

US06377713B1 Synchronous DRAM bandwidth optimization for display downsizing of an MPEG-2 image 有权
标题翻译：用于显示MPEG-2图像尺寸缩小的同步DRAM带宽优化
公开(公告)号：US06377713B1
公开(公告)日：2002-04-23
申请号：US09238951
申请日：1999-01-27
申请人： Bao Vuong
发明人： Bao Vuong
IPC分类号： G06K932
CPC分类号： G06T3/4007 , H04N5/14 , H04N5/45 , H04N7/0135 , H04N19/423 , H04N19/427 , H04N19/428 , H04N19/59 , H04N19/61 , H04N21/42692 , H04N21/4316 , H04N21/440263
摘要： A method and apparatus for downsizing a digital video image, such as an image corresponding to the MPEG-2 standard. The system is particularly suitable for providing a reduced image for a picture-in-picture mode on a television. Digital video pixel data that is received from a channel is decompressed to provide pixel data of an original image (e.g., A1, A2, A3, A4). Horizontally adjacent pixel pairs of the original image are averaged to provide horizontally downsized pixel data (e.g., (A1+A2)/2, (A3+A4)/2), which is stored in a first bank of a multi-bank memory. Data from every other pixel of the original image (e.g., A2, A4) is stored in a second bank of the dual-bank memory. To obtain a downsized image, vertically adjacent lines of the horizontally downsized pixel data are retrieved from the first bank, and averaged to provide vertically and horizontally downsized pixel data for display. Alternatively, to recover pixel data corresponding to the original image for decompressing predictive-coded images, portions of the horizontally downsized pixel data may be retrieved from the first bank with corresponding portions of the data from the second bank (e.g., A1=2(A1+A2)/2−A2).
摘要翻译：一种数字视频图像缩小的方法和装置，例如对应于MPEG-2标准的图像。该系统特别适用于在电视机上提供用于画中画模式的缩小图像。从信道接收的数字视频像素数据被解压缩以提供原始图像（例如，A1，A2，A3，A4）的像素数据。将原始图像的水平相邻像素对平均以提供存储在多存储体存储器的第一组中的水平缩小的像素数据（例如，（A1 + A2）/ 2，（A3 + A4）/ 2）。来自原始图像（例如，A2，A4）的每个其他像素的数据被存储在双存储体存储器的第二组中。为了获得缩小的图像，从第一组中检索水平缩小的像素数据的垂直相邻行，并且平均以提供用于显示的垂直和水平的缩小的像素数据。或者，为了恢复对应于原始图像的像素数据以解压缩预测编码图像，可以从第一组中检索来自第二组的数据的相应部分的水平缩小的像素数据的部分（例如，A1 = 2（A1 + A2）/ 2-A2）。

4. 发明申请

US20080307150A1 Optimized Switching Method 有权
标题翻译：优化切换方法
公开(公告)号：US20080307150A1
公开(公告)日：2008-12-11
申请号：US12196025
申请日：2008-08-21
申请人： Heath Stewart , Chris Haywood , Mike De la Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
发明人： Heath Stewart , Chris Haywood , Mike De la Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
IPC分类号： G06F13/14
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.
摘要翻译：公开了一种总线优化技术。根据总线优化技术，从交换机的端口单元中删除输出缓冲器和输出逻辑，并将其包含在开关中的控制矩阵中。在多个端口单元的第一端口单元中接收的数据单元被提供给控制矩阵。控制矩阵评估何时将数据单元发送到第二个端口单元。在第二个端口单元中不作出输出决定。

5. 发明授权

US07426602B2 Switch for bus optimization 有权
标题翻译：切换总线优化
公开(公告)号：US07426602B2
公开(公告)日：2008-09-16
申请号：US11031420
申请日：2005-01-07
申请人： Heath Stewart , Chris Haywood , Mike de la Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
发明人： Heath Stewart , Chris Haywood , Mike de la Garrigue , Nadim Shaikli , Ken Wong , Bao Vuong , Thomas Reiner , Adam Rappoport
IPC分类号： G06F13/14 , G06F3/00
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.
摘要翻译：公开了一种总线优化技术。根据总线优化技术，从交换机的端口单元中删除输出缓冲器和输出逻辑，并将其包含在开关中的控制矩阵中。在多个端口单元的第一端口单元中接收的数据单元被提供给控制矩阵。控制矩阵评估何时将数据单元发送到第二个端口单元。在第二个端口单元中不作出输出决定。

6. 发明授权

US06115072A 16:9 aspect ratio conversion by letterbox method for an MPEG image 有权
标题翻译： 16：9宽幅比转换通过letterbox方法为MPEG图像
公开(公告)号：US06115072A
公开(公告)日：2000-09-05
申请号：US238958
申请日：1999-01-27
申请人： Bao Vuong , Candace Anderson
发明人： Bao Vuong , Candace Anderson
IPC分类号： H04N5/44 , H04N7/26 , H04N7/50 , H04N7/01
CPC分类号： H04N7/0122 , H04N19/157 , H04N19/159 , H04N19/172 , H04N19/423 , H04N19/427 , H04N19/61 , H04N19/85 , H04N21/440272 , H04N5/4401 , Y10S348/913
摘要： A method and apparatus for converting a digital video image to a higher aspect ratio format at a decoder by line dropping. For example, conversion from a 4:3 to a 16:9 letterbox format may be achieved. Line dropping for non-anchor pictures (e.g., B-pictures) occurs on a decoding-side of the decoder, prior to storage in memory. Line dropping for anchor pictures (e.g., I- and P-pictures) occurs on a display-side of the decoder, after being retrieved from the memory, and prior to display. Additional memory space is freed to allow storage of additional decoded data, thus compensating for the decrease in display processing time caused by a reduced number of active video lines that are processed with the letter box format.
摘要翻译：一种用于通过线下降在解码器处将数字视频图像转换为较高宽高比格式的方法和装置。例如，可以实现从4：3到16：9信箱格式的转换。存储在存储器中之前，在解码器的解码侧出现用于非锚图像（例如，B图像）的行丢弃。在从存储器检索并且在显示之前，在解码器的显示侧出现锚图像（例如，I和P图像）的行丢弃。释放额外的存储空间以允许附加解码数据的存储，从而补偿由信箱格式处理的活动视频行数减少所导致的显示处理时间的减少。

7. 发明授权

US5675387A Method and apparatus for efficient addressing of DRAM in a video decompression processor 失效
标题翻译：用于在视频解压缩处理器中有效地寻址DRAM的方法和装置
公开(公告)号：US5675387A
公开(公告)日：1997-10-07
申请号：US687319
申请日：1996-07-25
申请人： Chris Hoogenboom , Bao Vuong
发明人： Chris Hoogenboom , Bao Vuong
IPC分类号： H04N11/04 , H03M7/36 , H04N7/26 , H04N7/32 , H04N7/50 , H04N7/18
CPC分类号： H04N19/433 , H04N19/423 , H04N19/61
摘要： Pixel data is stored and subsequently read from a random access memory of a video decompression processor in a manner that reduces the number of times different rows of the RAM must be addressed in order to retrieve portions of the pixel data therefrom. Pixel data from a video frame is stored in the RAM as a plurality of pages. Each page substantially fills a different row of the RAM and corresponds to a different section of the video frame. A motion vector is decoded to determine the location of a prediction area within the video frame. In the event that the prediction area encompasses more than one of the pages of the video frame, the pixel data is retrieved one page at a time, minimizing the number of row changes required when addressing the RAM to retrieve the data.
摘要翻译：像素数据被存储并随后从视频解压缩处理器的随机存取存储器中以一种减少RAM的不同行必须被寻址的次数的方式读取，以便从其中检索像素数据的部分。来自视频帧的像素数据作为多页存储在RAM中。每个页面基本上填充RAM的不同行并对应于视频帧的不同部分。对运动矢量进行解码以确定视频帧内的预测区域的位置。在预测区域包含视频帧的多个页面的情况下，一次检索一个页面的像素数据，从而最小化在寻址RAM以检索数据时所需的行更改数量。

8. 发明授权

US5638128A Pixel interpolation filters for video decompression processor 失效
标题翻译：视频解压缩处理器的像素插值滤波器
公开(公告)号：US5638128A
公开(公告)日：1997-06-10
申请号：US335651
申请日：1994-11-08
申请人： Chris Hoogenboom , Bao Vuong
发明人： Chris Hoogenboom , Bao Vuong
IPC分类号： H04N7/32 , H04N5/14 , H04N7/26 , H04N7/36 , H04N7/46 , H04N7/50
CPC分类号： H04N19/577 , H04N19/423 , H04N19/43 , H04N19/523 , H04N19/61 , H04N5/145
摘要： A method and apparatus are disclosed for interpolating pixels to obtain subpels for use by a video decompression processor. A prediction area is defined from which subpels are necessary to decompress a portion of a video image. Instead of reading all of the pixels from the prediction area and then processing them together to perform the necessary interpolation, portions of the pixel data are read and simultaneously averaged using in-place computation in order to reduce hardware requirements. Rounding of subpixel results is achieved using the carry input of conventional adders to add a binary "1" to the averaged pixels, which are subsequently truncated to provide the interpolated subpels.
摘要翻译：公开了一种用于内插像素以获得视频解压缩处理器使用的子层的方法和装置。定义预测区域，从中需要哪个子to子来解压缩视频图像的一部分。代替从预测区域读取所有像素，然后将它们一起处理以执行必要的插值，使用就地计算来读取并同时对像素数据的部分进行平均，以便减少硬件要求。使用常规加法器的进位输入来实现子像素结果的舍入，以向平均像素添加二进制“1”，随后被截断以提供内插的子像素。

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