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1. 发明申请

US20080012642A1 SERIAL LINK RECEIVER WITH WIDE INPUT VOLTAGE RANGE AND TOLERANCE TO HIGH POWER VOLTAGE SUPPLY 有权
标题翻译：具有宽输入电压范围和宽电压电源供应的串行接收器
公开(公告)号：US20080012642A1
公开(公告)日：2008-01-17
申请号：US11417626
申请日：2006-05-04
申请人： Hayden Cranford , Westerfield Ficken , David Freitas , Joseph Stevens
发明人： Hayden Cranford , Westerfield Ficken , David Freitas , Joseph Stevens
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F1/52 , H03F3/45973 , H03F2203/45078 , H03F2203/45431 , H03F2203/45541 , H03F2203/45561 , H03F2203/45588
摘要： A circuit device and method for designing a serial link receiver, which accommodates a wide input voltage range and provides tolerance to high termination voltages. The receiver is designed with a pair of RC networks connected inline between the input and the preamplifier and a common mode feedback loop, which monitors shifts in the common mode voltage and adjusts the inputs provided to the preamplifier. The circuit device maintains a flat bandwidth to accommodate all signaling rates.
摘要翻译：一种用于设计串行链路接收机的电路装置和方法，其适应宽的输入电压范围并且提供对高终端电压的容限。接收机设计有一对连接在输入和前置放大器之间的RC网络和一个共模反馈环路，它监控共模电压的变化并调整提供给前置放大器的输入。电路设备保持平坦的带宽以适应所有信令速率。

2. 发明申请

US20050281355A1 Reducing power consumption in signal detection 有权
标题翻译：降低信号检测中的功耗
公开(公告)号：US20050281355A1
公开(公告)日：2005-12-22
申请号：US10873672
申请日：2004-06-22
申请人： Hayden Cranford , Westerfield Ficken
发明人： Hayden Cranford , Westerfield Ficken
IPC分类号： H04L27/06 , H04L27/08
CPC分类号： H04L27/06 , H04L27/08
摘要： Methods, systems, and media to time-share the signal detection between reference voltages for a data transmission are contemplated. Embodiments include a time-sharing detector that is designed to enable comparison of a first reference voltage and a second reference voltage against the serial data transmission in a specified pattern. In many embodiments, the pattern is pre-defined and, in some embodiments, the pattern includes an overlap period. During the overlap period both the first and the second reference voltages are compared with the data transmission to determine if valid data can be detected. Upon detecting a valid bit based upon one of the reference voltages, an output signal is generated to indicate that the data transmission includes a valid data signal. Advantageously, alternating between the comparisons can reduce power consumption. In many embodiments, the power reduction can be, for example, 50%, depending upon the specified pattern.
摘要翻译：考虑用于数据传输的参考电压之间的时间共享信号检测的方法，系统和媒体。实施例包括分时检测器，其被设计为能够以指定的模式与第一参考电压和第二参考电压相对于串行数据传输进行比较。在许多实施例中，图案是预定义的，并且在一些实施例中，图案包括重叠周期。在重叠期间，将第一和第二参考电压与数据传输进行比较，以确定是否可以检测有效数据。在基于参考电压之一检测到有效位时，产生输出信号以指示数据传输包括有效数据信号。有利地，比较之间的交替可以降低功耗。在许多实施例中，取决于指定的模式，功率降低可以是例如50％。

3. 发明申请

US20050058231A1 Equalizer for reduced intersymbol interference via partial clock switching 有权
标题翻译：均衡器通过部分时钟切换减少符号间干扰
公开(公告)号：US20050058231A1
公开(公告)日：2005-03-17
申请号：US10665235
申请日：2003-09-17
申请人： Hayden Cranford , Westerfield Ficken , Wentai Liu
发明人： Hayden Cranford , Westerfield Ficken , Wentai Liu
IPC分类号： H04L1/00 , H04L25/03
CPC分类号： H04L25/03133
摘要： A method and system for is disclosed for reducing intersymbol interference in a stream of data bits to be transmitted over a transmission medium. Aspects of the present invention include a phase delayed clock generated from a reference clock that produces an edge on sub-bit boundaries; and a digital filter coupled to the phase delayed clock for performing equalization on the data bits, wherein the phase delayed clock causes the digital filter to perform partial clock switching, such that equalization is performed on the data bits on-sub-bit boundaries.
摘要翻译：公开了一种用于减少要在传输介质上传输的数据位流中的符号间干扰的方法和系统。本发明的方面包括从产生子位边界边缘的参考时钟产生的相位延迟时钟; 以及耦合到所述相位延迟时钟的数字滤波器，用于对所述数据位执行均衡，其中所述相位延迟时钟使所述数字滤波器执行部分时钟切换，使得对所述数据位在子位边界执行均衡。

4. 发明申请

US20060267616A1 Systems and methods for controlling of electro-migration 有权
标题翻译：用于控制电迁移的系统和方法
公开(公告)号：US20060267616A1
公开(公告)日：2006-11-30
申请号：US11140765
申请日：2005-05-31
申请人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
发明人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
IPC分类号： G01R31/02
CPC分类号： G01R31/2858 , H01L21/76886 , H01L2924/0002 , H04B7/0814 , H01L2924/00
摘要： Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration. A plurality of switches are provided to switch current directions through a lowest level of metallization so that the circuits function normally even though the polarity of the applied voltage has been reversed.
摘要翻译：公开了用于控制电迁移的系统和方法，并减少其有害影响。实施例提供了当指示电迁移程度的测量指示操作的愈合周期是有必要的时将施加的电压反转到集成电路。在愈合周期中，集成电路的电路正常工作，但电迁移效应相反。在一个实施例中，微电子机械开关设置在最低级别的金属化处，以将电流方向切换到集成电路的金属化水平。在另一个实施例中，如果指示电迁移程度的测量超过参考电平达指定量，则施加到集成电路的电压的极性反转，导致电流切换方向以对抗电迁移。提供多个开关以切换电流方向通过最低金属化水平，使得即使施加的电压的极性已经被反转，电路也能正常工作。

5. 发明申请

US20050127978A1 Electronic component value trimming systems 失效
标题翻译：电子元件修整系统
公开(公告)号：US20050127978A1
公开(公告)日：2005-06-16
申请号：US10967756
申请日：2004-10-18
申请人： Hayden Cranford , Louis Hsu , James Mason , Gareth Nicholls , Philip Murfet , Samuel Ray
发明人： Hayden Cranford , Louis Hsu , James Mason , Gareth Nicholls , Philip Murfet , Samuel Ray
IPC分类号： H01C17/22 , H03K3/00
CPC分类号： H01C17/22
摘要： Described is a system for trimming the value of an electronic component. The system comprises: at least one trimming component, each trimming component having an associated switch for selectively connecting that trimming component to the electronic component in response to a corresponding bit in a control vector. A comparator is included for generating an output bit having a first value if a net value of the electronic component and any connected trimming components differs from a desired value. A controller connected to the switches and the comparator generates the control vector in dependence on the output of comparator, the controller comprising a shift register for sequentially receiving successive output bits from the comparator; wherein the control vector comprises the contents of the shift register and wherein a bit of said first value in control vector effects switching of the corresponding switch.
摘要翻译：描述了一种用于修整电子部件的值的系统。该系统包括：至少一个修整部件，每个修剪部件具有相关联的开关，用于响应于控制矢量中的对应位选择性地将修剪部件连接到电子部件。如果电子部件的净值和任何连接的修整部件与期望值不同，则包括比较器以产生具有第一值的输出位。连接到开关和比较器的控制器根据比较器的输出产生控制向量，该控制器包括用于顺序地从比较器接收连续输出位的移位寄存器; 其中所述控制向量包括所述移位寄存器的内容，并且其中所述控制矢量中的所述第一值的位影响相应开关的切换。

6. 发明申请

US20080112521A1 Clock Data Recovering System with External Early/Late Input 有权
标题翻译：具有外部早/晚输入的时钟数据恢复系统
公开(公告)号：US20080112521A1
公开(公告)日：2008-05-15
申请号：US11966438
申请日：2007-12-28
申请人： Martin Schmatz , Hayden Cranford , Vernon Norman
发明人： Martin Schmatz , Hayden Cranford , Vernon Norman
IPC分类号： H04L7/00
CPC分类号： H03L7/091 , H03L7/0814 , H03L7/089 , H04L7/0331
摘要： The invention is directed to a clock data recovery system for resampling a clock signal according to an incoming data signal. The clock data recovery system comprises a clock generator for generating the clock signal and a phase adjustment unit for generating sampling phases dependent on a phase adjustment control signal. It also comprises a data sampling unit operable to generate a stream of input samples and an edge detector for generating therefrom an internal early signal and an internal late signal. A phase adjustment control unit is disposed for generating under use of the early signal and the late signal the phase adjustment control signal. The phase adjustment control unit is feedable with an external early/late signal and/or comprises an output for delivering an export early/late signal.
摘要翻译：本发明涉及一种用于根据输入数据信号重新采样时钟信号的时钟数据恢复系统。时钟数据恢复系统包括用于产生时钟信号的时钟发生器和用于根据相位调整控制信号产生采样相位的相位调整单元。它还包括可操作以产生输入样本流的数据采样单元和用于从其产生内部早期信号和内部迟滞信号的边缘检测器。设置相位调整控制单元，用于在早期信号的使用下产生相位调整控制信号，并且延迟信号。相位调整控制单元可以用外部早/晚信号进给，和/或包括用于传送出口早/晚信号的输出。

7. 发明申请

US20070244656A1 METHOD AND APPARATUS FOR DETERMINING JITTER AND PULSE WIDTH FROM CLOCK SIGNAL COMPARISONS 失效
标题翻译：用于确定时钟信号比较的抖动和脉冲宽度的方法和装置
公开(公告)号：US20070244656A1
公开(公告)日：2007-10-18
申请号：US11279651
申请日：2006-04-13
申请人： Hayden Cranford , Fadi Gebara , Jeremy Schaub
发明人： Hayden Cranford , Fadi Gebara , Jeremy Schaub
IPC分类号： G06F19/00 , G01R29/02 , G06F17/40
CPC分类号： G01R31/31709 , G01R31/31725
摘要： A method and apparatus for determining jitter and pulse width from clock signal comparisons provides a low cost and production-integrable mechanism for measuring a clock signal with a reference clock, both of unknown frequency. The measured clock signal is sampled at transitions of a reference clock and the sampled values are collected in a histogram according to a folding of the samples around a timebase which is either swept to detect a minimum jitter for the folded data or is obtained from direct frequency analysis for the sample set. The histogram for the correct estimated period is statistically analyzed to yield the pulse width, which is the difference between the peaks of the probability density function and jitter, which corresponds to width of the density function peaks. Frequency drift is corrected by adjusting the timebase used to fold the data across the sample set.
摘要翻译：用于从时钟信号比较确定抖动和脉冲宽度的方法和装置提供了一种低成本和可生产可集成的机制，用于测量具有未知频率的参考时钟的时钟信号。测量的时钟信号在参考时钟的转变时被采样，并且采样值被收集在直方图中，根据时基的周围样本的折叠，该时基被扫描以检测折叠数据的最小抖动，或者从直接频率获得分析样本集。统计分析正确估计周期的直方图以产生脉冲宽度，其是概率密度函数和抖动的峰值之间的差异，其对应于密度函数峰值的宽度。通过调整用于将样本集合中的数据折叠的时基来校正频率漂移。

8. 发明申请

US20070200744A1 INTRINSIC RC POWER DISTRIBUTION FOR NOISE FILTERING OF ANALOG SUPPLIES 有权
标题翻译：用于噪声滤波的模拟电源的内部RC功率分配
公开(公告)号：US20070200744A1
公开(公告)日：2007-08-30
申请号：US11276451
申请日：2006-02-28
申请人： Anthony Bonaccio , Hayden Cranford , Joseph Iadanza , Sebastian Ventrone , Stephen Wyatt
发明人： Anthony Bonaccio , Hayden Cranford , Joseph Iadanza , Sebastian Ventrone , Stephen Wyatt
IPC分类号： H03M1/66
CPC分类号： G05F1/46
摘要： Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.
摘要翻译：用于模拟电路的模拟电源和用于向模拟电路提供模拟信号的过程。模拟电源包括具有可变电阻器的噪声滤波器和耦合以调节可变电阻器的控制装置。控制装置被构造和布置成设置可变电阻器的电阻以最大化噪声滤波并优化模拟电路的性能。

9. 发明申请

US20070061665A1 Clock and data recovery system and method for clock and data recovery based on a forward error correction 有权
标题翻译：基于前向纠错的时钟和数据恢复系统及时钟和数据恢复方法
公开(公告)号：US20070061665A1
公开(公告)日：2007-03-15
申请号：US11214161
申请日：2005-08-29
申请人： Hayden Cranford , Martin Schmatz , Thomas Toifl
发明人： Hayden Cranford , Martin Schmatz , Thomas Toifl
IPC分类号： H03M13/00
CPC分类号： H03M13/336 , H03L7/091 , H04L1/0053 , H04L1/0061 , H04L7/033 , H04L7/048
摘要： The forward error correction based clock and data recovery system according to the invention comprises a data latch (16) for intermediately storing received data, which is triggered by a sampling clock (sclk). The system further comprises an error determination unit (20, 21) for determining whether and which of the sampled received data is wrong, and for generating out of it a phase/frequency correction signal (ctrl). Furthermore, the system comprises a clock generator (23, 24, 25) for generating the sampling clock (sclk) depending on the correction signal (ctrl).
摘要翻译：根据本发明的基于前向纠错的时钟和数据恢复系统包括用于中间存储由采样时钟（sclk）触发的接收数据的数据锁存器（16）。该系统还包括用于确定采样的接收数据是否以及哪个是错误的并且用于产生相位/频率校正信号（ctrl）的错误确定单元（20,21）。此外，该系统包括用于根据校正信号（ctrl）产生采样时钟（sclk）的时钟发生器（23,24,25）。

10. 发明申请

US20060209944A1 Altering power consumption in communication links based on measured noise 有权
公开(公告)号：US20060209944A1
公开(公告)日：2006-09-21
申请号：US11079952
申请日：2005-03-15
申请人： Juan Carballo , Hayden Cranford , Gareth Nicholls , Vernon Norman , Brian Schuh
发明人： Juan Carballo , Hayden Cranford , Gareth Nicholls , Vernon Norman , Brian Schuh
IPC分类号： H04B17/00 , H03D1/04
CPC分类号： H04B17/382 , H04B17/24 , H04B17/345
摘要： A method, circuit and system for altering the power consumption in communication links. A type of noise and an amount of jitter in a signal transmitted across a communication link is measured. Upon determining the contribution of the measured noise to the measured jitter in the signal, the measured noise is classified based on such contribution and the intensity of the measured jitter. The power consumption in a component(s) of the communication link may be adjusted based on the classification of the measured noise. For example, if the measured noise is classified as being a low amount of noise, then the power consumption of the component(s) may be reduced such as by lowering the voltage of the power supply and/or reducing the complexity of the circuitry. By reducing the power consumption when the communication link is not subject to the worst-case condition, a savings in power consumption may be made.

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