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1. 发明授权

US07034566B2 Method and circuit for increased noise immunity for clocking signals in high speed digital systems 失效
标题翻译：用于提高高速数字系统中时钟信号抗噪声的方法和电路
公开(公告)号：US07034566B2
公开(公告)日：2006-04-25
申请号：US10777952
申请日：2004-02-12
申请人： Hayden C. Cranford, Jr. , Joseph M. Stevens
发明人： Hayden C. Cranford, Jr. , Joseph M. Stevens
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/0005 , H03K19/018585
摘要： Aspects for increased noise immunity for clocking signals in high speed digital systems are described. The aspects include buffering a differential clock signal with a single buffer circuit for a plurality of load circuits and configuring the single buffer circuit to adjust to alterations in the number of load circuits receiving the differential clock signal. The configuring achieves a constant bandwidth and voltage level for the clock signal output while adjusting to alterations in the number of load circuits.
摘要翻译：描述了用于在高速数字系统中提高时钟信号的抗噪声性的方面。这些方面包括使用用于多个负载电路的单个缓冲电路来缓冲差分时钟信号，并且配置单个缓冲器电路以适应接收差分时钟信号的负载电路的数量的变化。配置在调整到负载电路数量的变化时，可实现时钟信号输出的恒定带宽和电压电平。

2. 发明授权

US07940846B2 Test circuit for serial link receiver 有权
标题翻译：串行链路接收机测试电路
公开(公告)号：US07940846B2
公开(公告)日：2011-05-10
申请号：US11621016
申请日：2007-01-08
申请人： Hayden C. Cranford, Jr. , Daniel P. Greenberg , Joseph M. Stevens , Westerfield J. Ficken
发明人： Hayden C. Cranford, Jr. , Daniel P. Greenberg , Joseph M. Stevens , Westerfield J. Ficken
IPC分类号： H04B3/00
CPC分类号： G01R31/31715
摘要： A test circuit for a serial link receiver includes a first current source coupled to a first input of the serial link receiver, and a second current source coupled to a second input of the serial link receiver. The first current source is symmetrically matched to the second current source. A first switch of the first current source is turned on to permit a charge-retaining mechanism thereof to be charged. A second switch of the first current source is turned on to permit the retained charge retained to be asserted on the first input. The charge turns on a control switch of the first current source, through which the charge is asserted on the first input. A charge-draining mechanism of the first current source is turned on to thereafter permit the charge to be drained in a controlled manner after the charge has been asserted.
摘要翻译：用于串行链路接收机的测试电路包括耦合到串行链路接收机的第一输入端的第一电流源和耦合到串行链路接收机的第二输入端的第二电流源。第一电流源与第二电流源对称地匹配。第一电流源的第一开关被接通以允许其电荷保持机构被充电。第一电流源的第二开关导通，以允许保留的保留电荷在第一输入上被断言。电荷打开第一个电流源的控制开关，电荷在第一个输入端被断言。接通第一电流源的电荷排放机构，之后允许电荷在电荷被断言之后以受控的方式排出。

3. 发明申请

US20110057727A1 ADAPTIVE COMMON MODE BIAS FOR DIFFERENTIAL AMPLIFIER INPUT CIRCUITS 有权
标题翻译：用于差分放大器输入电路的自适应通用模式偏置
公开(公告)号：US20110057727A1
公开(公告)日：2011-03-10
申请号：US12557139
申请日：2009-09-10
申请人： Hayden C. Cranford, JR. , Todd M. Rasmus , Joseph M. Stevens
发明人： Hayden C. Cranford, JR. , Todd M. Rasmus , Joseph M. Stevens
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F1/3211 , H03F3/45632 , H03F2203/45008 , H03F2203/45078 , H03F2203/45292 , H03F2203/45342
摘要： A method and apparatus for extending the common mode range of a differential amplifier. A circuit has a common mode detection circuit, a common mode voltage inversion circuit, and a differential amplifier. The common mode detection circuit receives a differential signal and detects a common mode voltage. The common mode voltage inversion circuit is coupled to the common mode detection circuit. The common mode voltage inversion circuit has an input node that receives the common mode voltage and an output node that outputs body voltage, wherein the common mode voltage inversion circuit creates an inverse relationship between the common mode voltage and the body voltage. The differential amplifier includes a differential pair of transistors that have a pair of body terminals coupled to the output node of the common mode voltage inversion circuit.
摘要翻译：一种用于扩展差分放大器的共模范围的方法和装置。电路具有共模检测电路，共模电压反相电路和差分放大器。共模检测电路接收差分信号并检测共模电压。共模电压反相电路耦合到共模检测电路。共模电压反相电路具有接收共模电压的输入节点和输出体电压的输出节点，其中共模电压反相电路在共模电压和体电压之间产生反向关系。差分放大器包括具有耦合到共模电压反相电路的输出节点的一对主体端子的差分对晶体管。

4. 发明授权

US08363736B2 Test circuit for serial link receiver 失效
标题翻译：串行链路接收机测试电路
公开(公告)号：US08363736B2
公开(公告)日：2013-01-29
申请号：US13044604
申请日：2011-03-10
申请人： Hayden C. Cranford , Daniel P. Greenberg , Joseph M. Stevens , Westerfield J. Ficken
发明人： Hayden C. Cranford , Daniel P. Greenberg , Joseph M. Stevens , Westerfield J. Ficken
IPC分类号： H04L25/00 , H04B17/00
CPC分类号： G01R31/31715
摘要： A test circuit for a serial link receiver includes a first current source coupled to a first input of the serial link receiver, and a second current source coupled to a second input of the serial link receiver. The first current source is symmetrically matched to the second current source. A first switch of the first current source is turned on to permit a charge-retaining mechanism thereof to be charged. A second switch of the first current source is turned on to permit the retained charge retained to be asserted on the first input. The charge turns on a control switch of the first current source, through which the charge is asserted on the first input. A charge-draining mechanism of the first current source is turned on to thereafter permit the charge to be drained in a controlled manner after the charge has been asserted.
摘要翻译：用于串行链路接收机的测试电路包括耦合到串行链路接收机的第一输入端的第一电流源和耦合到串行链路接收机的第二输入端的第二电流源。第一电流源与第二电流源对称地匹配。第一电流源的第一开关被接通以允许其电荷保持机构被充电。第一电流源的第二开关导通，以允许保留的保留电荷在第一输入上被断言。电荷打开第一个电流源的控制开关，电荷在第一个输入端被断言。接通第一电流源的电荷排放机构，之后允许电荷在电荷被断言之后以受控的方式排出。

5. 发明申请

US20110156663A1 TEST CIRCUIT FOR SERIAL LINK RECEIVER 失效
标题翻译：串行接收器测试电路
公开(公告)号：US20110156663A1
公开(公告)日：2011-06-30
申请号：US13044604
申请日：2011-03-10
申请人： Hayden C. Cranford , Daniel P. Greenberg , Joseph M. Stevens , Westerfield J. Ficken
发明人： Hayden C. Cranford , Daniel P. Greenberg , Joseph M. Stevens , Westerfield J. Ficken
IPC分类号： H02J7/00
CPC分类号： G01R31/31715
摘要： A test circuit for a serial link receiver includes a first current source coupled to a first input of the serial link receiver, and a second current source coupled to a second input of the serial link receiver. The first current source is symmetrically matched to the second current source. A first switch of the first current source is turned on to permit a charge-retaining mechanism thereof to be charged. A second switch of the first current source is turned on to permit the retained charge retained to be asserted on the first input. The charge turns on a control switch of the first current source, through which the charge is asserted on the first input. A charge-draining mechanism of the first current source is turned on to thereafter permit the charge to be drained in a controlled manner after the charge has been asserted.
摘要翻译：用于串行链路接收机的测试电路包括耦合到串行链路接收机的第一输入端的第一电流源和耦合到串行链路接收机的第二输入端的第二电流源。第一电流源与第二电流源对称地匹配。第一电流源的第一开关被接通以允许其电荷保持机构被充电。第一电流源的第二开关导通，以允许保留的保留电荷在第一输入上被断言。电荷打开第一个电流源的控制开关，电荷在第一个输入端被断言。接通第一电流源的电荷排放机构，之后允许电荷在电荷被断言之后以受控的方式排出。

6. 发明申请

US20080165837A1 TEST CIRCUIT FOR SERIAL LINK RECEIVER 有权
标题翻译：串行接收器测试电路
公开(公告)号：US20080165837A1
公开(公告)日：2008-07-10
申请号：US11621016
申请日：2007-01-08
申请人： Hayden C. Cranford , Daniel P. Greenberg , Joseph M. Stevens , Westerfield J. Ficken
发明人： Hayden C. Cranford , Daniel P. Greenberg , Joseph M. Stevens , Westerfield J. Ficken
IPC分类号： H04Q1/20 , H04B3/46 , H04B17/00
CPC分类号： G01R31/31715
摘要： A test circuit for a serial link receiver includes a first current source coupled to a first input of the serial link receiver, and a second current source coupled to a second input of the serial link receiver. The first current source is symmetrically matched to the second current source. A first switch of the first current source is turned on to permit a charge-retaining mechanism thereof to be charged. A second switch of the first current source is turned on to permit the retained charge retained to be asserted on the first input. The charge turns on a control switch of the first current source, through which the charge is asserted on the first input. A charge-draining mechanism of the first current source is turned on to thereafter permit the charge to be drained in a controlled manner after the charge has been asserted.
摘要翻译：用于串行链路接收机的测试电路包括耦合到串行链路接收机的第一输入端的第一电流源和耦合到串行链路接收机的第二输入端的第二电流源。第一电流源与第二电流源对称地匹配。第一电流源的第一开关被接通以允许其电荷保持机构被充电。第一电流源的第二开关导通，以允许保留的保留电荷在第一输入上被断言。电荷打开第一个电流源的控制开关，电荷在第一个输入端被断言。接通第一电流源的电荷排放机构，之后允许电荷在电荷被断言之后以受控的方式排出。

7. 发明授权

US07332932B2 Serial link receiver with wide input voltage range and tolerance to high power voltage supply 有权
标题翻译：具有宽输入电压范围的串行链路接收器和高电源电压容限
公开(公告)号：US07332932B2
公开(公告)日：2008-02-19
申请号：US11417626
申请日：2006-05-04
申请人： Hayden C. Cranford , Westerfield J. Ficken , David A. Freitas , Joseph M. Stevens
发明人： Hayden C. Cranford , Westerfield J. Ficken , David A. Freitas , Joseph M. Stevens
IPC分类号： H03K17/16 , H03K19/003 , H03K19/0175
CPC分类号： H03F3/45475 , H03F1/52 , H03F3/45973 , H03F2203/45078 , H03F2203/45431 , H03F2203/45541 , H03F2203/45561 , H03F2203/45588
摘要： A circuit device and method for designing a serial link receiver, which accommodates a wide input voltage range and provides tolerance to high termination voltages. The receiver is designed with a pair of RC networks connected inline between the input and the preamplifier and a common mode feedback loop, which monitors shifts in the common mode voltage and adjusts the inputs provided to the preamplifier. The circuit device maintains a flat bandwidth to accommodate all signaling rates.
摘要翻译：一种用于设计串行链路接收机的电路装置和方法，其适应宽的输入电压范围并且提供对高终端电压的容限。接收机设计有一对连接在输入和前置放大器之间的RC网络和一个共模反馈环路，它监控共模电压的变化并调整提供给前置放大器的输入。电路设备保持平坦的带宽以适应所有信令速率。

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