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1. 发明申请

US20110057727A1 ADAPTIVE COMMON MODE BIAS FOR DIFFERENTIAL AMPLIFIER INPUT CIRCUITS 有权
标题翻译：用于差分放大器输入电路的自适应通用模式偏置
公开(公告)号：US20110057727A1
公开(公告)日：2011-03-10
申请号：US12557139
申请日：2009-09-10
申请人： Hayden C. Cranford, JR. , Todd M. Rasmus , Joseph M. Stevens
发明人： Hayden C. Cranford, JR. , Todd M. Rasmus , Joseph M. Stevens
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F1/3211 , H03F3/45632 , H03F2203/45008 , H03F2203/45078 , H03F2203/45292 , H03F2203/45342
摘要： A method and apparatus for extending the common mode range of a differential amplifier. A circuit has a common mode detection circuit, a common mode voltage inversion circuit, and a differential amplifier. The common mode detection circuit receives a differential signal and detects a common mode voltage. The common mode voltage inversion circuit is coupled to the common mode detection circuit. The common mode voltage inversion circuit has an input node that receives the common mode voltage and an output node that outputs body voltage, wherein the common mode voltage inversion circuit creates an inverse relationship between the common mode voltage and the body voltage. The differential amplifier includes a differential pair of transistors that have a pair of body terminals coupled to the output node of the common mode voltage inversion circuit.
摘要翻译：一种用于扩展差分放大器的共模范围的方法和装置。电路具有共模检测电路，共模电压反相电路和差分放大器。共模检测电路接收差分信号并检测共模电压。共模电压反相电路耦合到共模检测电路。共模电压反相电路具有接收共模电压的输入节点和输出体电压的输出节点，其中共模电压反相电路在共模电压和体电压之间产生反向关系。差分放大器包括具有耦合到共模电压反相电路的输出节点的一对主体端子的差分对晶体管。

2. 发明授权

US07405620B2 Differential amplifier and method 有权
标题翻译：差分放大器和方法
公开(公告)号：US07405620B2
公开(公告)日：2008-07-29
申请号：US11458712
申请日：2006-07-20
申请人： Hayden C. Cranford, Jr. , Todd M. Rasmus
发明人： Hayden C. Cranford, Jr. , Todd M. Rasmus
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F1/52 , H03F2203/45352 , H03F2203/45481
摘要： A method of forming a differential amplifier on a substrate which has a greater tolerance for applied voltages and a chip so formed. The differential amplifier circuit on a substrate has additional transistors connected with resistors which form a voltage divider, thereby sharing the voltage stress which may be applied and accommodating enhanced capabilities for the differential amplifier.
摘要翻译：一种在衬底上形成差分放大器的方法，该衬底对所施加的电压具有较大的容差以及如此形成的芯片。衬底上的差分放大器电路具有与形成分压器的电阻器连接的附加晶体管，从而共享可施加的电压应力并且为差分放大器提供增强的能力。

3. 发明授权

US06977558B2 Self-adaptive voltage regulator for a phase-locked loop 失效
公开(公告)号：US06977558B2
公开(公告)日：2005-12-20
申请号：US10650396
申请日：2003-08-28
申请人： Hayden C. Cranford, Jr. , Stacy J. Garvin , Vernon R. Norman , Todd M. Rasmus , Peter R. Seidel
发明人： Hayden C. Cranford, Jr. , Stacy J. Garvin , Vernon R. Norman , Todd M. Rasmus , Peter R. Seidel
IPC分类号： H03L7/08 , H03L7/14
CPC分类号： H03L7/08 , H03L2207/06
摘要： A self-adaptive voltage regulator for a phase-locked loop is disclosed. The phase-locked loop includes a phase detector, a charge pump, a low pass filter, and a voltage control oscillator, wherein the low pass filter inputs a control voltage to a voltage controlled oscillator for generation of an output clock. According to the method and system disclosed herein, the self-adaptive voltage regulator is coupled to an output of the low pass filter for sensing the control voltage during normal operation of the phase-locked loop, and for dynamically adjusting the supply voltage, which is input to the voltage controlled oscillator in response to the control voltage, such that the phase-locked loop maintains the control voltage within a predefined range of a reference voltage.

4. 发明授权

US07042277B2 Circuit and method for reducing jitter in a PLL of high speed serial links 失效
标题翻译：用于降低高速串行链路PLL的抖动的电路和方法
公开(公告)号：US07042277B2
公开(公告)日：2006-05-09
申请号：US10685022
申请日：2003-10-14
申请人： Hayden C. Cranford, Jr. , Stacy J. Garvin , Vernon R. Norman , Todd M. Rasmus
发明人： Hayden C. Cranford, Jr. , Stacy J. Garvin , Vernon R. Norman , Todd M. Rasmus
IPC分类号： G01F1/10
CPC分类号： H03L7/10
摘要： Aspects for reducing jitter in a PLL of a high speed serial link include examining at least one parameter related to performance of a voltage controlled oscillator (VCO) in the PLL, and controlling adjustment of a supply voltage to the VCO based on the examining. A regulator control circuit performs the examining and controlling.
摘要翻译：降低高速串行链路的PLL中的抖动的方面包括检查与PLL中的压控振荡器（VCO）的性能有关的至少一个参数，以及基于检查来控制对VCO的电源电压的调整。调节器控制电路进行检查和控制。

5. 发明授权

US07268613B2 Transistor switch with integral body connection to prevent latchup 失效
标题翻译：晶体管开关具有整体连接，以防止闭锁
公开(公告)号：US07268613B2
公开(公告)日：2007-09-11
申请号：US11263008
申请日：2005-10-31
申请人： Hayden C. Cranford, Jr. , Stacy J. Garvin , Todd M. Rasmus
发明人： Hayden C. Cranford, Jr. , Stacy J. Garvin , Todd M. Rasmus
IPC分类号： G05F3/02
CPC分类号： H03K17/161 , H03K2217/0018
摘要： A circuit device having a transistor-based switch topology that substantially eliminates the possibility of latchup of the device. A series-connected low voltage threshold (LVT) N-channel transistor and a pull-up resistor are coupled across a switching (P-channel) transistor so that an integral body connection is provided for the switching transistor, which connects the body of the switching transistor to a node between the pull-up resistor and source terminal of the LVT transistor. The LVT transistor is connected with its gate and drain terminal connected to the output terminal of the switching transistor. The resistor is connected at its other end to the power supply side terminal of the switching transistor. The addition of these components in the particular configuration allows the body connection of the switching transistor to be automatically switched to the highest potential diffusion node.
摘要翻译：一种具有基于晶体管的开关拓扑的电路器件，其基本上消除了器件闭锁的可能性。串联的低电压阈值（LVT）N沟道晶体管和上拉电阻跨越开关（P沟道）晶体管耦合，以便为开关晶体管提供一体的主体连接，开关晶体管连接开关晶体管连接到LVT晶体管的上拉电阻和源极端子之间的一个节点。 LVT晶体管的栅极和漏极端子连接到开关晶体管的输出端子。电阻器的另一端连接到开关晶体管的电源侧端子。在特定配置中添加这些组件允许开关晶体管的主体连接自动切换到最高电位扩散节点。

6. 发明申请

US20080018400A1 Differential Amplifier and Method 有权
标题翻译：差分放大器和方法
公开(公告)号：US20080018400A1
公开(公告)日：2008-01-24
申请号：US11458712
申请日：2006-07-20
申请人： Hayden C. Cranford, Jr. , Todd M. Rasmus
发明人： Hayden C. Cranford, Jr. , Todd M. Rasmus
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F1/52 , H03F2203/45352 , H03F2203/45481
摘要： A method of forming a differential amplifier on a substrate which has a greater tolerance for applied voltages and a chip so formed. The differential amplifier circuit on a substrate has additional transistors connected with resistors which form a voltage divider, thereby sharing the voltage stress which may be applied and accommodating enhanced capabilities for the differential amplifier.
摘要翻译：一种在衬底上形成差分放大器的方法，该衬底对所施加的电压具有较大的容差以及如此形成的芯片。衬底上的差分放大器电路具有与形成分压器的电阻器连接的附加晶体管，从而共享可施加的电压应力并且为差分放大器提供增强的能力。

7. 发明授权

US07307447B2 Self series terminated serial link transmitter having segmentation for amplitude, pre-emphasis, and slew rate control and voltage regulation for amplitude accuracy and high voltage protection 有权
标题翻译：自串式串行链路发射机具有用于振幅，预加重和转换速率控制的分段，以及用于振幅精度和高电压保护的电压调节
公开(公告)号：US07307447B2
公开(公告)日：2007-12-11
申请号：US11263138
申请日：2005-10-27
申请人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Todd M. Rasmus
发明人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Todd M. Rasmus
IPC分类号： H03K17/16 , H03B1/00
CPC分类号： H03K17/164 , H03K19/018585 , H04L25/0272 , H04L25/0278 , H04L25/028
摘要： A circuit design method and transmitter that enables flexible control of amplitude, pre-emphasis, and slew rate utilizing a design of a segmented self-series terminated (SSST) transmitter having a parallel configuration of multiple, individually controllable segments of dual pull-up and pull-down transistors. Amplitude control, slew rate control and pre-emphasis control are enabled by manipulation/selection of normal or inverted inputs for the various segments. Also provided is a mechanism for providing/maintaining accurate output across a self-series terminated (SST) transmitter by regulating the supply voltage. Regulation of the supply voltage allows compatibility with conventional serial link receiver termination voltages and protects the transmitter output devices when those voltages are larger than the normal supply for the devices.
摘要翻译：一种电路设计方法和发射机，其利用分段自串式终止（SSST）发射机的设计来灵活地控制振幅，预加重和转换速率，该发射机具有双重上拉的多个单独可控段的并行配置，下拉晶体管。幅度控制，转换速率控制和预加重控制可以通过对各个段的正常或反相输入进行操作/选择来实现。还提供了一种用于通过调节电源电压来提供/保持跨越自串式端接（SST）发射器的精确输出的机构。电源电压的调节允许与传统的串行链路接收器终端电压兼容，并在这些电压大于设备的正常供电时保护发射机输出设备。

8. 发明申请

US20120153910A1 DUAL-LOOP VOLTAGE REGULATOR ARCHITECTURE WITH HIGH DC ACCURACY AND FAST RESPONSE TIME 有权
标题翻译：具有高直流精度和快速响应时间的双环电压调节器架构
公开(公告)号：US20120153910A1
公开(公告)日：2012-06-21
申请号：US13213578
申请日：2011-08-19
申请人： John F. Bulzacchelli , Carrie E. Cox , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
发明人： John F. Bulzacchelli , Carrie E. Cox , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
IPC分类号： G05F1/10
CPC分类号： G05F1/575
摘要： Dual-loop voltage regulator circuits and methods in which a dual-loop voltage regulation framework is implemented with a first inner loop having a bang-bang voltage regulator to achieve nearly instantaneous response time, and a second outer loop, which is slower in operating speed than the first inner loop, to controllably adjust a trip point of the bang-bang voltage regulator to achieve high DC accuracy.
摘要翻译：双环路电压调节器电路和方法，其中使用具有爆轰电压调节器的第一内环实现双回路电压调节框架以实现几乎瞬时的响应时间，以及第二外环，其操作速度较慢比第一个内环，可控地调节砰砰电压调节器的跳闸点，以实现高直流精度。

9. 发明授权

US07705640B2 Common-mode feedback method using a current starved replica biasing 有权
标题翻译：共模反馈方法使用当前饥饿的副本偏置
公开(公告)号：US07705640B2
公开(公告)日：2010-04-27
申请号：US12019748
申请日：2008-01-25
申请人： Steven M. Clements , Todd M. Rasmus
发明人： Steven M. Clements , Todd M. Rasmus
IPC分类号： H03L7/06
CPC分类号： H03L7/0895
摘要： A method, system, and circuit design product for setting the common-mode voltage level of a charge pump to yield low duty cycle distortion from a voltage controlled oscillator (VCO). Differential charge pumps utilize common-mode feedback (CMF) networks to control the common-mode voltage level. A replica circuit of a current starved delay cell from a VCO replaces the unity gain buffering circuit within a common-mode feedback circuit. Inserting the current starved delay cell replica circuit permits adequate negative feedback compensation, while allowing a phase locked loop (PLL) to operate with a wide bandwidth. As a result of utilizing the replica circuit of a current starved delay cell from a VCO, the common-mode voltage level is optimally centered to interface with the VCO, thereby minimizing duty cycle distortion.
摘要翻译：一种用于设置电荷泵的共模电压电平以从压控振荡器（VCO）产生低占空比失真的方法，系统和电路设计产品。差分电荷泵利用共模反馈（CMF）网络来控制共模电压电平。来自VCO的当前饥饿延迟单元的复制电路替代共模反馈电路内的单位增益缓冲电路。插入当前受饥饿的延迟单元复制电路允许充分的负反馈补偿，同时允许锁相环（PLL）以宽带宽工作。作为利用来自VCO的当前饥饿延迟单元的复制电路的结果，共模电压电平被最佳地集中于与VCO的接口，从而最小化占空比失真。

10. 发明授权

US09110488B2 Wide-bandwidth linear regulator 有权
标题翻译：宽带线性稳压器
公开(公告)号：US09110488B2
公开(公告)日：2015-08-18
申请号：US13154840
申请日：2011-06-07
申请人： Bradford L. Hunter , Todd M. Rasmus
发明人： Bradford L. Hunter , Todd M. Rasmus
IPC分类号： G05F1/00 , G05F1/575 , G05F1/565 , G05F1/56
CPC分类号： G05F1/575 , G05F1/56
摘要： A linear regulator and a method of regulating a supply voltage are provided. Embodiments include a linear regulator with a first feedback loop and a second feedback loop. The first feedback loop is characterized by a first bandwidth and a first gain. The first feedback loop includes a first amplifier characterized by an output impedance which is significantly reduced in order to maximize the bandwidth of the first feedback loop when driving the capacitance of a control input of a series pass element. The second feedback loop is characterized by a second bandwidth and a second gain. The second feedback loop includes a second amplifier that controls the current in the first amplifier in the first feedback loop.
摘要翻译：提供线性调节器和调节电源电压的方法。实施例包括具有第一反馈回路和第二反馈回路的线性调节器。第一反馈回路的特征在于第一带宽和第一增益。第一反馈回路包括第一放大器，其特征在于输出阻抗显着减小，以便在驱动串联通过元件的控制输入的电容时使第一反馈环路的带宽最大化。第二反馈回路的特征在于第二带宽和第二增益。第二反馈回路包括控制第一反馈回路中的第一放大器中的电流的第二放大器。

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