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1. 发明授权

US07940846B2 Test circuit for serial link receiver 有权
标题翻译：串行链路接收机测试电路
公开(公告)号：US07940846B2
公开(公告)日：2011-05-10
申请号：US11621016
申请日：2007-01-08
申请人： Hayden C. Cranford, Jr. , Daniel P. Greenberg , Joseph M. Stevens , Westerfield J. Ficken
发明人： Hayden C. Cranford, Jr. , Daniel P. Greenberg , Joseph M. Stevens , Westerfield J. Ficken
IPC分类号： H04B3/00
CPC分类号： G01R31/31715
摘要： A test circuit for a serial link receiver includes a first current source coupled to a first input of the serial link receiver, and a second current source coupled to a second input of the serial link receiver. The first current source is symmetrically matched to the second current source. A first switch of the first current source is turned on to permit a charge-retaining mechanism thereof to be charged. A second switch of the first current source is turned on to permit the retained charge retained to be asserted on the first input. The charge turns on a control switch of the first current source, through which the charge is asserted on the first input. A charge-draining mechanism of the first current source is turned on to thereafter permit the charge to be drained in a controlled manner after the charge has been asserted.
摘要翻译：用于串行链路接收机的测试电路包括耦合到串行链路接收机的第一输入端的第一电流源和耦合到串行链路接收机的第二输入端的第二电流源。第一电流源与第二电流源对称地匹配。第一电流源的第一开关被接通以允许其电荷保持机构被充电。第一电流源的第二开关导通，以允许保留的保留电荷在第一输入上被断言。电荷打开第一个电流源的控制开关，电荷在第一个输入端被断言。接通第一电流源的电荷排放机构，之后允许电荷在电荷被断言之后以受控的方式排出。

2. 发明授权

US06968413B2 Method and system for configuring terminators in a serial communication system 有权
标题翻译：用于在串行通信系统中配置终端器的方法和系统
公开(公告)号：US06968413B2
公开(公告)日：2005-11-22
申请号：US10266132
申请日：2002-10-07
申请人： Hayden C. Cranford, Jr. , Westerfield J. Ficken , Paul A. Owczarski
发明人： Hayden C. Cranford, Jr. , Westerfield J. Ficken , Paul A. Owczarski
IPC分类号： G06F13/00 , H04L25/02
CPC分类号： H04L25/0278
摘要： A system and method is disclosed that efficiently provides standard termination blocks in an approved cell library that are flexible and customizable. A serial communications system includes a transmitter for sending a serial data signal at an output of the transmitter; a transmitter terminator, coupled to the output and responsive to a first configuration signal, to variably terminate a first selected property of the output; a receiver for processing the serial data signal at an input of the receiver, the input of the receiver coupled to the output of the transmitter; and a receiver terminator, coupled to the input of the receiver and responsive to a second configuration signal to variably terminate a second selected properly of the input. The method for operating a serial communications system includes the steps of: (a) providing a plurality of unidirectional serial links, each of the links between a transmitter and a receiver, an output of each transmitter coupled to an input of a corresponding receiver by a medium type with each output having a transmitter terminator and each input having a receiver terminator; (b) terminating variably a selected property of the output of each transmitter to match the medium type coupling the output to the input of the corresponding receiver by use of a transmitter termination configuration signal asserted to the transmitter; and (c) terminating variably a selected property of the input of each receiver to match the medium type coupling the input to the output of the corresponding transmitter by use of a receiver termination configuration signal asserted to the receiver.
摘要翻译：公开了一种系统和方法，其有效地提供了可被灵活和可定制的批准的小区库中的标准终端块。串行通信系统包括用于在发射机的输出端发送串行数据信号的发射机; 发射器终端器，耦合到所述输出并且响应于第一配置信号可变地终止所述输出的第一选定属性; 用于在接收机的输入端处理串行数据信号的接收机，耦合到发射机的输出的接收机的输入; 以及接收器终端器，其耦合到所述接收器的输入并且响应于第二配置信号可变地终止所选输入的第二选择。用于操作串行通信系统的方法包括以下步骤：（a）提供多个单向串行链路，发射机和接收机之间的每个链路，每个发射机的输出端通过一个中间型，每个输出具有发射器终端器，每个输入具有接收器终端器; （b）可变地终止每个发射机的输出的选定属性，以使得通过使用被确定给发射机的发射机终端配置信号将输出耦合到相应接收机的输入的媒体类型; 以及（c）可变地终止每个接收机的输入的选定属性以将通过使用被确认给接收机的接收机终端配置信号将输入耦合到相应发射机的输出的媒体类型。

3. 发明授权

US07286620B2 Equalizer for reduced intersymbol interference via partial clock switching 有权
标题翻译：均衡器通过部分时钟切换减少符号间干扰
公开(公告)号：US07286620B2
公开(公告)日：2007-10-23
申请号：US10665235
申请日：2003-09-17
申请人： Hayden C. Cranford, Jr. , Westerfield J. Ficken , Wentai Liu
发明人： Hayden C. Cranford, Jr. , Westerfield J. Ficken , Wentai Liu
IPC分类号： H04L1/00
CPC分类号： H04L25/03133
摘要： A method and system for is disclosed for reducing intersymbol interference in a stream of data bits to be transmitted over a transmission medium. Aspects of the present invention include a phase delayed clock generated from a reference clock that produces an edge on sub-bit boundaries; and a digital filter coupled to the phase delayed clock for performing equalization on the data bits, wherein the phase delayed clock causes the digital filter to perform partial clock switching, such that equalization is performed on the data bits on-sub-bit boundaries.
摘要翻译：公开了一种用于减少要在传输介质上传输的数据位流中的符号间干扰的方法和系统。本发明的方面包括从产生子位边界边缘的参考时钟产生的相位延迟时钟; 以及耦合到所述相位延迟时钟的数字滤波器，用于对所述数据位执行均衡，其中所述相位延迟时钟使所述数字滤波器执行部分时钟切换，使得对所述数据位在子位边界执行均衡。

4. 发明授权

US07289572B2 Method and system for scalable pre-driver to driver interface 有权
标题翻译：可扩展的预驱动程序到驱动程序接口的方法和系统
公开(公告)号：US07289572B2
公开(公告)日：2007-10-30
申请号：US10265755
申请日：2002-10-07
申请人： Hayden C. Cranford, Jr. , Westerfield J. Ficken
发明人： Hayden C. Cranford, Jr. , Westerfield J. Ficken
IPC分类号： H04L27/00
CPC分类号： H04L25/028 , H04L25/0272
摘要： A system and method for a predriver and driver interface having scalable output drive capability with corresponding scalable power is disclosed. The system includes a predriver to driver interface having a data source; a plurality of predrivers, each coupled to the data source and responsive to an enable signal, for driving a predriven data signal only when a corresponding enable signal is asserted and for consuming reduced power when the corresponding enable signal is deasserted; a plurality of drivers, each coupled to one of the plurality of predrivers to receive a corresponding predriven data signal from the corresponding predriver and responsive to the enable signal coupled to the corresponding predriver, for driving an output with the predriven data signal only when the corresponding enable signal is asserted and for consuming reduced power when the corresponding enable signal is deasserted; and a controller, coupled to the predrivers and the drivers, for selectively asserting the enable signals to provide variable output drive capability of the data source to the output while providing scalable power consumption.
摘要翻译：公开了一种具有可扩展输出驱动能力和相应的可扩展功率的预驱动器和驱动器接口的系统和方法。该系统包括具有数据源的驱动器接口的预驱动器; 每个耦合到数据源并且响应于使能信号的预驱动器，用于仅在相应的使能信号被断言时驱动预驱动数据信号，并且当相应的使能信号被无效时消耗降低的功率; 多个驱动器，每个驱动器耦合到所述多个预驱动器中的一个，以从相应的预驱动器接收相应的预驱动数据信号，并且响应于耦合到相应的预驱动器的使能信号，仅在相应的预驱动器驱动具有预驱动数据信号的输出时使能信号被断言并且当相应的使能信号被无效时消耗降低的功率; 以及耦合到预驱动器和驱动器的控制器，用于选择性地确定使能信号，以在提供可缩放功率消耗的同时向输出端提供数据源的可变输出驱动能力。

5. 发明授权

US07034566B2 Method and circuit for increased noise immunity for clocking signals in high speed digital systems 失效
标题翻译：用于提高高速数字系统中时钟信号抗噪声的方法和电路
公开(公告)号：US07034566B2
公开(公告)日：2006-04-25
申请号：US10777952
申请日：2004-02-12
申请人： Hayden C. Cranford, Jr. , Joseph M. Stevens
发明人： Hayden C. Cranford, Jr. , Joseph M. Stevens
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/0005 , H03K19/018585
摘要： Aspects for increased noise immunity for clocking signals in high speed digital systems are described. The aspects include buffering a differential clock signal with a single buffer circuit for a plurality of load circuits and configuring the single buffer circuit to adjust to alterations in the number of load circuits receiving the differential clock signal. The configuring achieves a constant bandwidth and voltage level for the clock signal output while adjusting to alterations in the number of load circuits.
摘要翻译：描述了用于在高速数字系统中提高时钟信号的抗噪声性的方面。这些方面包括使用用于多个负载电路的单个缓冲电路来缓冲差分时钟信号，并且配置单个缓冲器电路以适应接收差分时钟信号的负载电路的数量的变化。配置在调整到负载电路数量的变化时，可实现时钟信号输出的恒定带宽和电压电平。

6. 发明授权

US07809054B2 One-sample-per-bit decision feedback equalizer (DFE) clock and data recovery 失效
标题翻译：单采样每位决策反馈均衡器（DFE）时钟和数据恢复
公开(公告)号：US07809054B2
公开(公告)日：2010-10-05
申请号：US11405997
申请日：2006-04-18
申请人： Juan A. Carballo , Hayden C. Cranford, Jr. , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
发明人： Juan A. Carballo , Hayden C. Cranford, Jr. , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03063
摘要： Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a decision feedback equalizer along with the appropriate (CDR) loop phase detector to maintain a single sample per bit requirement. The incoming voltage is converted to a current and connected to a current summing node. Weighted currents determined by the values of previously detected bits and their respective feedback coefficients are also connected to this node. Additionally, the summed currents is integrated and converted to a voltage. A sampler is utilized to make a bit decision based on the resulting voltage. After sampling, the integrator is reset before analysis of the next bit. The necessary amplification is achieved by maximizing the sensitivity of the latch, using integration in front of the data latch.
摘要翻译：公开了一种在接收机中利用/产生一个每位采样的判决反馈均衡器（DFE）时钟和数据恢复（CDR）架构的接收器电路，方法和设计架构，并且降低了误码率（BER ）。集成接收机与决策反馈均衡器以及适当的（CDR）环路相位检测器相结合，以保持每位需求的单个采样。输入电压被转换为电流并连接到电流求和节点。由先前检测到的位及其各自的反馈系数的值确定的加权电流也连接到该节点。另外，总和电流被积分并转换成电压。采样器用于基于所得到的电压进行位决定。采样后，积分器在分析下一位之前被复位。通过使用在数据锁存器前面的积分来最大化锁存器的灵敏度来实现必要的放大。

7. 发明授权

US07755420B2 Intrinsic RC power distribution for noise filtering of analog supplies 失效
标题翻译：用于模拟电源噪声滤波的本征RC功率分配
公开(公告)号：US07755420B2
公开(公告)日：2010-07-13
申请号：US12196718
申请日：2008-08-22
申请人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
发明人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
IPC分类号： H03K5/00
CPC分类号： G05F1/46
摘要： Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.
摘要翻译：用于模拟电路的模拟电源和用于向模拟电路提供模拟信号的过程。模拟电源包括具有可变电阻器的噪声滤波器和耦合以调节可变电阻器的控制装置。控制装置被构造和布置成设置可变电阻器的电阻以最大化噪声滤波并优化模拟电路的性能。

8. 发明授权

US07721134B2 Method for on-chip diagnostic testing and checking of receiver margins 失效
标题翻译：用于片上诊断测试和接收器边距检查的方法
公开(公告)号：US07721134B2
公开(公告)日：2010-05-18
申请号：US11566576
申请日：2006-12-04
申请人： Hayden C. Cranford, Jr. , Daniel J. Friedman , Mounir Meghelli , Thomas H. Toifl
发明人： Hayden C. Cranford, Jr. , Daniel J. Friedman , Mounir Meghelli , Thomas H. Toifl
IPC分类号： H04L25/00 , H03D3/24
CPC分类号： G01R31/3171 , B82Y25/00 , G01R33/093
摘要： A method and system for determining the eye pattern margin parameters of a receiver system during diagnostic testing is presented. The circuitry in the receiver's front end comprises a series of latches, XOR gates and OR gates which first provide the data samples and edge samples, i.e., data sampled at the rising or falling edge of an (edge) clock characterized by a phase delay relative to the data sampling clock. The receiver also comprises optimization circuitry for the ideal alignment of the edge clock (edges) with the data edges. The method further provides for a phase shifting of the edge clock to the left and right from the ideal/locked position to screen the data eye pattern in order to compute the Bit Error Rate (BER) value. The position of the edge clock relative to the data sampling clock determines the horizontal eye opening for the computed BER.
摘要翻译：提出了一种用于在诊断测试期间确定接收机系统的眼图边缘参数的方法和系统。接收机前端的电路包括一系列锁存器，XOR门和OR门，它们首先提供数据样本和边缘采样，即在（边沿）时钟的上升沿或下降沿采样的数据，其特征在于相位延迟相对到数据采样时钟。接收机还包括用于边缘时钟（边缘）与数据边缘的理想对准的优化电路。该方法还提供了边缘时钟从理想/锁定位置向左和向右移相以屏蔽数据眼图，以便计算误码率（BER）值。边缘时钟相对于数据采样时钟的位置决定了计算的BER的水平眼睛开度。

9. 发明授权

US07684478B2 Generating an eye diagram of integrated circuit transmitted signals 失效
标题翻译：生成集成电路传输信号的眼图
公开(公告)号：US07684478B2
公开(公告)日：2010-03-23
申请号：US11427831
申请日：2006-06-30
申请人： Hayden C. Cranford, Jr. , Fadi H. Gebara , Jeremy D. Schaub
发明人： Hayden C. Cranford, Jr. , Fadi H. Gebara , Jeremy D. Schaub
IPC分类号： H04B17/00 , H04L27/06
CPC分类号： G01R31/31711 , H04L1/205 , H04L1/24
摘要： A sequence of K voltage samples of a transmitted data signal is generated by sampling, digitizing, and storing voltage samples of the data signal with an imbedded sample clock on an IC having an unknown period TS. The K voltage samples are plotted against a time base of K sequential times TB[K] normalized so all samples fall within one cycle of the data clock used to generate the data signal or a unit time of 1. The time base is generated by estimating the sample clock period TSE to be some multiple of 1/P where P is greater than K. Eye diagrams are analyzed for time jitter wherein only the minimum value of jitter is saved. TSE is incremented by 1/P until TS is greater than one half the data clock period. The eye diagram at the TSE with the minimum time jitter is used to analyze the data channels.
摘要翻译：通过在具有未知周期TS的IC上以嵌入的采样时钟采样，数字化和存储数据信号的电压采样来生成发送数据信号的K个电压样本的序列。 K电压样本相对于K次顺序TB [K]的时基绘制，归一化，所以所有采样都落在用于生成数据信号的数据时钟或单位时间为1的一个周期内。时基是通过估计采样时钟周期TSE为1 / P的某个倍数，其中P大于K.眼图分析时间抖动，其中只保存抖动的最小值。 TSE递增1 / P，直到TS大于数据时钟周期的一半。 TSE具有最小时间抖动的眼图用于分析数据通道。

10. 发明授权

US07661052B2 Using statistical signatures for testing high-speed circuits 失效
标题翻译：使用统计特征来测试高速电路
公开(公告)号：US07661052B2
公开(公告)日：2010-02-09
申请号：US12021950
申请日：2008-01-29
申请人： Hayden C. Cranford, Jr. , Vernon R. Norman , Martin L. Schmatz
发明人： Hayden C. Cranford, Jr. , Vernon R. Norman , Martin L. Schmatz
IPC分类号： G06F11/277 , G06F11/16
CPC分类号： G01R31/31901 , G01R31/31707
摘要： A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.
摘要翻译：公开了一种用于测试高速电路的方法和系统。该方法和系统包括使用常规测试仪获得高速电路的高速统计特征。该方法和系统还包括将高速电路的高速统计签名与预期签名进行比较。因此，可以确定高速电路是否在期望的参数内起作用。

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