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1. 发明申请

US20070049015A1 Silicided recessed silicon 有权
标题翻译：硅胶凹槽硅
公开(公告)号：US20070049015A1
公开(公告)日：2007-03-01
申请号：US11219303
申请日：2005-09-01
申请人： Hasan Nejad , Thomas Figura , Gordon Haller , Ravi Iyer , John Meldrim , Justin Harnish
发明人： Hasan Nejad , Thomas Figura , Gordon Haller , Ravi Iyer , John Meldrim , Justin Harnish
IPC分类号： H01L21/4763
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L27/10852 , H01L27/10876 , H01L27/10897 , H01L29/4975 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.
摘要翻译：为嵌入硅完全硅化提供了方法和结构。在沟槽内提供硅。在硅上提供了一种金属混合物，其中一种金属在硅中比硅中更容易扩散到金属中，而另一种金属在硅中比在金属中的硅更容易扩散。示例性的混合物包括80％的镍和20％的钴。尽管沟槽的纵横比相对较高，但沟槽内的硅可以完全无硅化物形成。在其他设备中，可以通过用于存储器阵列的方法形成凹陷接入设备（RAD）。

2. 发明申请

US20070105357A1 SILICIDED RECESSED SILICON 有权
标题翻译：硅化硅
公开(公告)号：US20070105357A1
公开(公告)日：2007-05-10
申请号：US11614802
申请日：2006-12-21
申请人： Hasan Nejad , Thomas Figura , Gordon Haller , Ravi Iyer , John Meldrim , Justin Harnish
发明人： Hasan Nejad , Thomas Figura , Gordon Haller , Ravi Iyer , John Meldrim , Justin Harnish
IPC分类号： H01L21/3205 , H01L23/48
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L27/10852 , H01L27/10876 , H01L27/10897 , H01L29/4975 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.
摘要翻译：为嵌入硅完全硅化提供了方法和结构。在沟槽内提供硅。在硅上提供了一种金属混合物，其中一种金属在硅中比硅中更容易扩散到金属中，而另一种金属在硅中比在金属中的硅更容易扩散。示例性的混合物包括80％的镍和20％的钴。尽管沟槽的纵横比相对较高，但沟槽内的硅可以完全无硅化物形成。在其他设备中，可以通过用于存储器阵列的方法形成凹陷接入设备（RAD）。

3. 发明申请

US20060263979A1 Methods of forming devices associated with semiconductor constructions 有权
标题翻译：形成与半导体结构相关的器件的方法
公开(公告)号：US20060263979A1
公开(公告)日：2006-11-23
申请号：US11131994
申请日：2005-05-18
申请人： Hasan Nejad , Gordon Haller , Thomas Figura , Ravi Iyer
发明人： Hasan Nejad , Gordon Haller , Thomas Figura , Ravi Iyer
IPC分类号： H01L21/8242 , H01L21/22 , H01L21/4763 , H01L21/44 , H01L21/302 , H01L21/38
CPC分类号： H01L27/10894 , H01L27/10876 , H01L27/10897 , Y10S439/917
摘要： The invention includes methods of forming devices associated with semiconductor constructions. In exemplary methods, common processing steps are utilized to form fully silicided recessed array access gates and partially silicided periphery transistor gates.
摘要翻译：本发明包括形成与半导体结构相关的器件的方法。在示例性方法中，利用通常的处理步骤来形成完全硅化的凹陷阵列存取栅极和部分硅化的外围晶体管栅极。

4. 发明申请

US20070166920A1 Transistor gate forming methods and transistor structures 有权
标题翻译：晶体管栅极形成方法和晶体管结构
公开(公告)号：US20070166920A1
公开(公告)日：2007-07-19
申请号：US11716433
申请日：2007-03-08
申请人： Sanh Tang , Gordon Haller , Prashant Raghu , Ravi Iyer
发明人： Sanh Tang , Gordon Haller , Prashant Raghu , Ravi Iyer
IPC分类号： H01L21/336
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66787
摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.
摘要翻译：晶体管栅极形成方法包括在线路开口内形成金属层，并在金属层的开口内形成填充层。填充层相对于金属层基本上可选择性地蚀刻。晶体管结构包括线路开口，开口内的电介质层，开口内的电介质层上的金属层，以及开口内的金属层上的填充层。如果填充层被金属层的增加的厚度代替，则金属层/填充层组合的内在特性小于否则会存在。本发明至少应用于三维晶体管结构。

5. 发明申请

US20070048941A1 Transistor gate forming methods and transistor structures 有权
公开(公告)号：US20070048941A1
公开(公告)日：2007-03-01
申请号：US11219077
申请日：2005-09-01
申请人： Sanh Tang , Gordon Haller , Prashant Raghu , Ravi Iyer
发明人： Sanh Tang , Gordon Haller , Prashant Raghu , Ravi Iyer
IPC分类号： H01L21/336
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66787
摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.

6. 发明申请

US20070048930A1 Peripheral gate stacks and recessed array gates 有权
标题翻译：外围栅极堆叠和凹陷阵列栅极
公开(公告)号：US20070048930A1
公开(公告)日：2007-03-01
申请号：US11219304
申请日：2005-09-01
申请人： Thomas Figura , Gordon Haller
发明人： Thomas Figura , Gordon Haller
IPC分类号： H01L21/8242
CPC分类号： H01L21/823456 , H01L21/82345 , H01L27/10852 , H01L27/10876 , H01L27/10897
摘要： Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate stack patterning in the periphery, word lines are recessed within the trenches for the array RADs. Side wall spacer formation in the periphery simultaneously provides an insulating cap layer burying the word lines within the trenches of the array.
摘要翻译：提供了用于在集成电路的两个不同区域中同时处理晶体管的方法。在逻辑区域中提供平面晶体管，而在用于存储器件的阵列区域中提供凹入式存取设备（RAD）。在周边的栅堆栈图案化期间，字线凹入用于阵列RAD的沟槽内。在外围的侧壁间隔物形成同时提供了一个绝缘盖层，掩埋了阵列的沟槽内的字线。

7. 发明申请

US20150279851A1 METHODS OF TUNNEL OXIDE LAYER FORMATION IN 3D NAND MEMORY STRUCTURES AND ASSOCIATED DEVICES 有权
标题翻译：三维NAND存储器结构和相关器件中的氧化锆层形成方法
公开(公告)号：US20150279851A1
公开(公告)日：2015-10-01
申请号：US14227217
申请日：2014-03-27
申请人： Darwin Fan , Sateesh Koka , Gordon Haller , John Hopkins , Shyam Surthi , Anish Khandekar
发明人： Darwin Fan , Sateesh Koka , Gordon Haller , John Hopkins , Shyam Surthi , Anish Khandekar
IPC分类号： H01L27/115 , H01L29/423 , H01L21/28
CPC分类号： H01L27/11524 , H01L21/28273 , H01L27/11556
摘要： 3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.
摘要翻译：提供3D NAND存储器结构及相关方法。在一些实施例中，这样的结构可以包括设置在第一绝缘层和第二绝缘层之间的控制栅极材料和浮置栅极材料，设置在浮置栅极材料和控制栅极材料之间的多层电介质（IPD）层，使得IPD层将控制栅极材料与浮动栅极材料电隔离，以及沉积在与控制栅极材料相对的浮动栅极材料上的隧道电介质材料。

8. 发明申请

US20130168756A1 SOURCE/DRAIN ZONES WITH A DELECTRIC PLUG OVER AN ISOLATION REGION BETWEEN ACTIVE REGIONS AND METHODS 有权
标题翻译：具有活动区域和方法之间的隔离区域的电压插入源/漏区
公开(公告)号：US20130168756A1
公开(公告)日：2013-07-04
申请号：US13343087
申请日：2012-01-04
申请人： John Hopkins , James Mathew , Jie Sun , Gordon Haller
发明人： John Hopkins , James Mathew , Jie Sun , Gordon Haller
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/76224 , H01L27/11524 , H01L27/1157
摘要： Devices, memory arrays, and methods are disclosed. In an embodiment, one such device has a source/drain zone that has first and second active regions, and an isolation region and a dielectric plug between the first and second active regions. The dielectric plug may extend below upper surfaces of the first and second active regions and may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.
摘要翻译：公开了设备，存储器阵列和方法。在一个实施例中，一个这样的器件具有源极/漏极区域，其具有第一和第二有源区域，以及在第一和第二有源区域之间的隔离区域和电介质插塞。电介质插塞可以延伸到第一和第二有源区域的上表面之下，并且可以由对于特定各向同性去除化学物质具有比隔离区域的电介质材料更低的去除速率的电介质材料形成。

9. 发明授权

US08222105B2 Methods of fabricating a memory device 有权
标题翻译：制造存储器件的方法
公开(公告)号：US08222105B2
公开(公告)日：2012-07-17
申请号：US12703502
申请日：2010-02-10
申请人： Gordon Haller , Sanh D. Tang , Steve Cummings
发明人： Gordon Haller , Sanh D. Tang , Steve Cummings
IPC分类号： H01L29/94
CPC分类号： H01L21/823487 , H01L27/10817 , H01L27/10823 , H01L27/10876 , H01L27/10888
摘要： A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.
摘要翻译：包括垂直晶体管的存储器件包括直接耦合到每个存储器单元的源极区域的数字线。由于不使用电插头来形成数字线和源极区之间的接触，所以可以减少多个制造步骤，并且还可以减少制造缺陷的可能性。在一些实施例中，存储器件可以包括垂直晶体管，其具有从硅衬底的上部凹陷的栅极区域。随着从硅衬底凹入的栅极区域，栅极区域与源极/漏极区域进一步间隔开，因此，可以减小栅极区域和源极/漏极区域之间的交叉电容。

10. 发明授权

US08076721B2 Fin structures and methods of fabricating fin structures 有权
标题翻译：鳍结构和制造鳍结构的方法
公开(公告)号：US08076721B2
公开(公告)日：2011-12-13
申请号：US12795495
申请日：2010-06-07
申请人： Sahn D. Tang , Gordon Haller
发明人： Sahn D. Tang , Gordon Haller
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L21/3086 , H01L27/0886 , H01L29/0649 , H01L29/66795 , H01L29/7851
摘要： There is provided fin structures and methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins.
摘要翻译：提供了用于制造翅片结构的翅片结构和方法。更具体地，翅片结构形成在基板中。翅片结构可以包括由通道分开的两个翅片，其中翅片可以用作场效应晶体管的翅片。翅片结构形成在衬底的上表面下方，并且可以在不利用光刻掩模来形成以蚀刻鳍片的情况下形成。

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