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1. 发明申请

US20070166920A1 Transistor gate forming methods and transistor structures 有权
标题翻译：晶体管栅极形成方法和晶体管结构
公开(公告)号：US20070166920A1
公开(公告)日：2007-07-19
申请号：US11716433
申请日：2007-03-08
申请人： Sanh Tang , Gordon Haller , Prashant Raghu , Ravi Iyer
发明人： Sanh Tang , Gordon Haller , Prashant Raghu , Ravi Iyer
IPC分类号： H01L21/336
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66787
摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.
摘要翻译：晶体管栅极形成方法包括在线路开口内形成金属层，并在金属层的开口内形成填充层。填充层相对于金属层基本上可选择性地蚀刻。晶体管结构包括线路开口，开口内的电介质层，开口内的电介质层上的金属层，以及开口内的金属层上的填充层。如果填充层被金属层的增加的厚度代替，则金属层/填充层组合的内在特性小于否则会存在。本发明至少应用于三维晶体管结构。

2. 发明申请

US20070048941A1 Transistor gate forming methods and transistor structures 有权
公开(公告)号：US20070048941A1
公开(公告)日：2007-03-01
申请号：US11219077
申请日：2005-09-01
申请人： Sanh Tang , Gordon Haller , Prashant Raghu , Ravi Iyer
发明人： Sanh Tang , Gordon Haller , Prashant Raghu , Ravi Iyer
IPC分类号： H01L21/336
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66787
摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.

3. 发明申请

US20080099847A1 Integrated Circuits and Methods of Forming a Field Effect Transistor 有权
标题翻译：集成电路和形成场效应晶体管的方法
公开(公告)号：US20080099847A1
公开(公告)日：2008-05-01
申请号：US11957013
申请日：2007-12-14
申请人： Sanh Tang , Gordon Haller
发明人： Sanh Tang , Gordon Haller
IPC分类号： H01L29/786
CPC分类号： H01L29/0653 , H01L21/0237 , H01L21/02532 , H01L21/02595 , H01L21/0262 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L21/84 , H01L27/1203
摘要： Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semiconductive material. Semiconductor material is formed on the insulative material. A field effect transistor is included and comprises a gate, a channel region, and a pair of source/drain regions. In one implementation, one of the source/drain regions is formed in the semiconductor material, and the other of the source/drain regions is formed in the bulk semiconductive material. In one implementation, the electrically insulative material extends from beneath one of the source/drain regions to beneath only a portion of the channel region. Other aspects and implementations, including methodical aspects, are disclosed.
摘要翻译：公开了形成场效应晶体管的集成电路和方法。在一个方面，集成电路包括包括本体半导体材料的半导体衬底。电绝缘材料容纳在本体半导体材料内。在绝缘材料上形成半导体材料。包括场效应晶体管，并包括栅极，沟道区和一对源极/漏极区。在一个实施方案中，源/漏区中的一个形成在半导体材料中，并且源/漏区中的另一个在体半导体材料中形成。在一个实施方案中，电绝缘材料从源极/漏极区域之一延伸到仅沟道区域的仅一部分的下方。公开了其他方面和实施方式，包括方法方面。

4. 发明申请

US20070051997A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20070051997A1
公开(公告)日：2007-03-08
申请号：US11218184
申请日：2005-08-31
申请人： Gordon Haller , Sanh Tang , Steve Cummings
发明人： Gordon Haller , Sanh Tang , Steve Cummings
IPC分类号： H01L29/94 , H01L21/8242
CPC分类号： H01L21/823487 , H01L27/10817 , H01L27/10823 , H01L27/10876 , H01L27/10888
摘要： A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.
摘要翻译：包括垂直晶体管的存储器件包括直接耦合到每个存储器单元的源极区域的数字线。由于不使用电插头来形成数字线和源极区之间的接触，所以可以减少多个制造步骤，并且还可以减少制造缺陷的可能性。在一些实施例中，存储器件可以包括垂直晶体管，其具有从硅衬底的上部凹陷的栅极区域。随着从硅衬底凹入的栅极区域，栅极区域与源极/漏极区域进一步间隔开，因此，可以减小栅极区域和源极/漏极区域之间的交叉电容。

5. 发明申请

US20070045712A1 Memory cell layout and process flow 有权
标题翻译：存储单元格布局和流程
公开(公告)号：US20070045712A1
公开(公告)日：2007-03-01
申请号：US11219349
申请日：2005-09-01
申请人： Gordon Haller , David Hwang , Sanh Tang , Ceredig Roberts
发明人： Gordon Haller , David Hwang , Sanh Tang , Ceredig Roberts
IPC分类号： H01L29/788
CPC分类号： H01L21/3088 , H01L21/0338 , H01L27/0207 , H01L27/10891 , H01L27/10894
摘要： A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are defined by a first pitch, with one word line located between each drain and the source. Digit lines are defined by a second pitch, one of the digit lines being coupled to the source and forming a second axis. The active areas of the memory array are tilted at 45° to the grid defined by the word lines and digit lines. The word line pitch is about 1.5 F, while the digit line pitch is about 3 F.
摘要翻译：存储器件包括有源区域，其包括源极和限定第一轴线的至少两个漏极。至少两个基本上平行的字线由第一间距限定，一个字线位于每个漏极和源之间。数字线由第二间距限定，其中一个数字线耦合到源并形成第二轴。存储器阵列的有效区域与由字线和数字线限定的栅格倾斜45°。字线间距约为1.5 F，而数字线间距约为3 F。

6. 发明申请

US20060046424A1 Methods of forming semiconductor constructions 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US20060046424A1
公开(公告)日：2006-03-02
申请号：US10925789
申请日：2004-08-24
申请人： Randal Chance , Gordon Haller , Sanh Tang , Steven Cummings
发明人： Randal Chance , Gordon Haller , Sanh Tang , Steven Cummings
IPC分类号： H01L21/76
CPC分类号： H01L29/66666 , H01L21/823437 , H01L21/823487 , H01L27/10808 , H01L27/10876 , H01L29/42368 , H01L29/512 , H01L29/7827
摘要： The invention includes semiconductor constructions containing vertically-extending pillars, and methods for forming such constructions. The vertically-extending pillars can be incorporated into transistor devices, and can contain vertically-extending channel regions of the transistor devices. The transistor devices can be incorporated into integrated circuitry, and in some aspects are incorporated into memory constructions, such as, for example, dynamic random access memory (DRAM) constructions.
摘要翻译：本发明包括包含垂直延伸柱的半导体结构以及用于形成这种结构的方法。垂直延伸的柱可以并入晶体管器件中，并且可以包含晶体管器件的垂直延伸的沟道区域。晶体管器件可以并入到集成电路中，并且在一些方面被并入存储器结构中，例如动态随机存取存储器（DRAM）结构。

7. 发明申请

US20060043450A1 Vertical transistors 有权
公开(公告)号：US20060043450A1
公开(公告)日：2006-03-02
申请号：US10934621
申请日：2004-09-02
申请人： Sanh Tang , Gordon Haller
发明人： Sanh Tang , Gordon Haller
IPC分类号： H01L29/94
CPC分类号： H01L27/10885 , H01L21/28132 , H01L27/10814 , H01L27/10876 , H01L27/10888 , H01L29/66666
摘要： Vertical transistors for memory cells, such as 4F2 memory cells, are disclosed. The memory cells use digit line connections formed within the isolation trench to connect the digit line with the lower active area. Vertical transistor pillars can be formed from epitaxial silicon or etched from bulk silicon. Memory cells can be formed by creating a cell capacitor electrically connected to each transistor pillar.

8. 发明申请

US20070141771A1 Integrated circuits and methods of forming a field effect transistor 有权
公开(公告)号：US20070141771A1
公开(公告)日：2007-06-21
申请号：US11704487
申请日：2007-02-09
申请人： Sanh Tang , Gordon Haller
发明人： Sanh Tang , Gordon Haller
IPC分类号： H01L21/8238
CPC分类号： H01L29/0653 , H01L21/0237 , H01L21/02532 , H01L21/02595 , H01L21/0262 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L21/84 , H01L27/1203
摘要： Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semiconductive material. Semiconductor material is formed on the insulative material. A field effect transistor is included and comprises a gate, a channel region, and a pair of source/drain regions. In one implementation, one of the source/drain regions is formed in the semiconductor material, and the other of the source/drain regions is formed in the bulk semiconductive material. In one implementation, the electrically insulative material extends from beneath one of the source/drain regions to beneath only a portion of the channel region. Other aspects and implementations, including methodical aspects, are disclosed.

9. 发明申请

US20060261393A1 Semiconductor constructions and transistors, and methods of forming semiconductor constructions and transistors 有权
公开(公告)号：US20060261393A1
公开(公告)日：2006-11-23
申请号：US11496930
申请日：2006-07-31
申请人： Sanh Tang , Gordon Haller , Kris Brown , Tuman Earl Allen
发明人： Sanh Tang , Gordon Haller , Kris Brown , Tuman Earl Allen
IPC分类号： H01L29/94
CPC分类号： H01L29/41758 , H01L27/10817 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L29/1037 , H01L29/4236 , H01L29/4238 , H01L29/66621 , H01L29/78
摘要： The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.

10. 发明申请

US20060205128A1 Integrated circuits and methods of forming a field effect transistor 有权
标题翻译：集成电路和形成场效应晶体管的方法
公开(公告)号：US20060205128A1
公开(公告)日：2006-09-14
申请号：US11076774
申请日：2005-03-10
申请人： Sanh Tang , Gordon Haller
发明人： Sanh Tang , Gordon Haller
IPC分类号： H01L21/8234 , H01L21/76 , H01L21/20
CPC分类号： H01L29/0653 , H01L21/0237 , H01L21/02532 , H01L21/02595 , H01L21/0262 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L21/84 , H01L27/1203
摘要： Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semiconductive material. Semiconductor material is formed on the insulative material. A field effect transistor is included and comprises a gate, a channel region, and a pair of source/drain regions. In one implementation, one of the source/drain regions is formed in the semiconductor material, and the other of the source/drain regions is formed in the bulk semiconductive material. In one implementation, the electrically insulative material extends from beneath one of the source/drain regions to beneath only a portion of the channel region. Other aspects and implementations, including methodical aspects, are disclosed.
摘要翻译：公开了形成场效应晶体管的集成电路和方法。在一个方面，集成电路包括包括本体半导体材料的半导体衬底。电绝缘材料容纳在本体半导体材料内。在绝缘材料上形成半导体材料。包括场效应晶体管，并包括栅极，沟道区和一对源极/漏极区。在一个实施方案中，源/漏区中的一个形成在半导体材料中，并且源/漏区中的另一个在体半导体材料中形成。在一个实施方案中，电绝缘材料从源极/漏极区域之一延伸到仅沟道区域的仅一部分的下方。公开了其他方面和实施方式，包括方法方面。

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