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1. 发明申请

US20070049015A1 Silicided recessed silicon 有权
标题翻译：硅胶凹槽硅
公开(公告)号：US20070049015A1
公开(公告)日：2007-03-01
申请号：US11219303
申请日：2005-09-01
申请人： Hasan Nejad , Thomas Figura , Gordon Haller , Ravi Iyer , John Meldrim , Justin Harnish
发明人： Hasan Nejad , Thomas Figura , Gordon Haller , Ravi Iyer , John Meldrim , Justin Harnish
IPC分类号： H01L21/4763
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L27/10852 , H01L27/10876 , H01L27/10897 , H01L29/4975 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.
摘要翻译：为嵌入硅完全硅化提供了方法和结构。在沟槽内提供硅。在硅上提供了一种金属混合物，其中一种金属在硅中比硅中更容易扩散到金属中，而另一种金属在硅中比在金属中的硅更容易扩散。示例性的混合物包括80％的镍和20％的钴。尽管沟槽的纵横比相对较高，但沟槽内的硅可以完全无硅化物形成。在其他设备中，可以通过用于存储器阵列的方法形成凹陷接入设备（RAD）。

2. 发明申请

US20070105357A1 SILICIDED RECESSED SILICON 有权
标题翻译：硅化硅
公开(公告)号：US20070105357A1
公开(公告)日：2007-05-10
申请号：US11614802
申请日：2006-12-21
申请人： Hasan Nejad , Thomas Figura , Gordon Haller , Ravi Iyer , John Meldrim , Justin Harnish
发明人： Hasan Nejad , Thomas Figura , Gordon Haller , Ravi Iyer , John Meldrim , Justin Harnish
IPC分类号： H01L21/3205 , H01L23/48
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L27/10852 , H01L27/10876 , H01L27/10897 , H01L29/4975 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.
摘要翻译：为嵌入硅完全硅化提供了方法和结构。在沟槽内提供硅。在硅上提供了一种金属混合物，其中一种金属在硅中比硅中更容易扩散到金属中，而另一种金属在硅中比在金属中的硅更容易扩散。示例性的混合物包括80％的镍和20％的钴。尽管沟槽的纵横比相对较高，但沟槽内的硅可以完全无硅化物形成。在其他设备中，可以通过用于存储器阵列的方法形成凹陷接入设备（RAD）。

3. 发明申请

US20060263979A1 Methods of forming devices associated with semiconductor constructions 有权
标题翻译：形成与半导体结构相关的器件的方法
公开(公告)号：US20060263979A1
公开(公告)日：2006-11-23
申请号：US11131994
申请日：2005-05-18
申请人： Hasan Nejad , Gordon Haller , Thomas Figura , Ravi Iyer
发明人： Hasan Nejad , Gordon Haller , Thomas Figura , Ravi Iyer
IPC分类号： H01L21/8242 , H01L21/22 , H01L21/4763 , H01L21/44 , H01L21/302 , H01L21/38
CPC分类号： H01L27/10894 , H01L27/10876 , H01L27/10897 , Y10S439/917
摘要： The invention includes methods of forming devices associated with semiconductor constructions. In exemplary methods, common processing steps are utilized to form fully silicided recessed array access gates and partially silicided periphery transistor gates.
摘要翻译：本发明包括形成与半导体结构相关的器件的方法。在示例性方法中，利用通常的处理步骤来形成完全硅化的凹陷阵列存取栅极和部分硅化的外围晶体管栅极。

4. 发明申请

US20070048930A1 Peripheral gate stacks and recessed array gates 有权
标题翻译：外围栅极堆叠和凹陷阵列栅极
公开(公告)号：US20070048930A1
公开(公告)日：2007-03-01
申请号：US11219304
申请日：2005-09-01
申请人： Thomas Figura , Gordon Haller
发明人： Thomas Figura , Gordon Haller
IPC分类号： H01L21/8242
CPC分类号： H01L21/823456 , H01L21/82345 , H01L27/10852 , H01L27/10876 , H01L27/10897
摘要： Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate stack patterning in the periphery, word lines are recessed within the trenches for the array RADs. Side wall spacer formation in the periphery simultaneously provides an insulating cap layer burying the word lines within the trenches of the array.
摘要翻译：提供了用于在集成电路的两个不同区域中同时处理晶体管的方法。在逻辑区域中提供平面晶体管，而在用于存储器件的阵列区域中提供凹入式存取设备（RAD）。在周边的栅堆栈图案化期间，字线凹入用于阵列RAD的沟槽内。在外围的侧壁间隔物形成同时提供了一个绝缘盖层，掩埋了阵列的沟槽内的字线。

5. 发明授权

US5661064A Method of forming a capacitor having container members 失效
标题翻译：形成具有容器构件的电容器的方法
公开(公告)号：US5661064A
公开(公告)日：1997-08-26
申请号：US558643
申请日：1995-11-13
申请人： Thomas Figura , Pierre C. Fazan
发明人： Thomas Figura , Pierre C. Fazan
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： A capacitor construction includes, a) first and second electrically conductive capacitor plates separated by an intervening capacitor dielectric layer, the first capacitor plate comprising first and second container members, the second container member being received inside of the first container member, the first and second container members comprising a respective ring portion and a respective base portion; and b) a pedestal disk positioned elevationally intermediate the first container member base and the second container member base to space and support the second container member relative to the first container member. The structure is preferably produced by using a series of alternating first and second layers of semiconductive material provided over a molding layer within a container contact opening therein. One of the first and second layers has an average conductivity enhancing dopant concentration of greater than about 5.times.10.sup.19 ions/cm.sup.3, with the other of the first and second layers having an average conductivity enhancing dopant concentration from 0 ions/cm.sup.3 to about 5.times.10.sup.19 ions/cm.sup.3. At least one of the first and second layers is selectively etchable relative to the other of the first and second layers to facilitate a container construction and formation of the pedestal disk. Utilization of alternate materials to the doped semiconductive material is also contemplated.
摘要翻译：一种电容器结构包括：a）由中间电容器介电层分隔开的第一和第二导电电容器板，所述第一电容器板包括第一和第二容器构件，所述第二容器构件容纳在所述第一容器构件的内部，所述第一和第二容器构件包括相应的环部分和相应的基部; 以及b）位于所述第一容器构件基部和所述第二容器构件基部的正中方的基座盘，以相对于所述第一容器构件间隔并支撑所述第二容器构件。该结构优选通过使用在其中的容器接触开口内的成型层上设置的一系列交替的半导体材料层来制造。第一层和第二层之一具有大于约5×1019离子/ cm3的平均导电性增强掺杂剂浓度，第一和第二层中的另一层具有从0离子/ cm 3至约5×10 19离子/ cm 3的平均导电性增强掺杂剂浓度。第一层和第二层中的至少一层相对于第一层和第二层中的另一层可选择性地蚀刻，以便于容器构造和基座盘的形成。也考虑了对掺杂半导体材料的替代材料的利用。

6. 发明申请

US20050026361A1 Double sided container capacitor for a semiconductor device and method for forming same 有权
标题翻译：用于半导体器件的双面容器电容器及其形成方法
公开(公告)号：US20050026361A1
公开(公告)日：2005-02-03
申请号：US10628994
申请日：2003-07-28
申请人： Thomas Graettinger , Marsela Pontoh , Thomas Figura
发明人： Thomas Graettinger , Marsela Pontoh , Thomas Figura
IPC分类号： H01L21/02 , H01L21/20 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： A method for forming a double sided container capacitor comprises forming a first capacitor top plate layer within a recess in a dielectric layer, then forming a first cell dielectric on the first top plate layer. Next, first and second bottom plate layers are formed on the first cell dielectric layer, and a second cell dielectric layer is formed on the second bottom plate layers. Finally, a second top plate layer is formed on the second cell dielectric layer, and the first and second top plate layers are electrically connected using a conductive plug or conductive spacer. An inventive structure formed using the inventive method is also described.
摘要翻译：一种用于形成双面容器电容器的方法包括在电介质层的凹槽内形成第一电容器顶板层，然后在第一顶板层上形成第一单元电介质。接下来，在第一单元电介质层上形成第一和第二底板层，在第二底板层上形成第二单元电介质层。最后，在第二单元电介质层上形成第二顶板层，并且使用导电插塞或导电间隔件将第一和第二顶板层电连接。还描述了使用本发明方法形成的本发明的结构。

7. 发明申请

US20070049037A1 Methods of forming openings into dielectric material 有权
标题翻译：将开口形成电介质材料的方法
公开(公告)号：US20070049037A1
公开(公告)日：2007-03-01
申请号：US11217905
申请日：2005-09-01
申请人： Thomas Graettinger , John Zahurak , Shane Trapp , Thomas Figura
发明人： Thomas Graettinger , John Zahurak , Shane Trapp , Thomas Figura
IPC分类号： H01B13/00 , H01L21/311 , B44C1/22
CPC分类号： H01L21/31116 , H01L21/31122 , H01L21/31138 , H01L21/31144 , H01L21/76802 , H01L21/76844 , H01L27/10852
摘要： This invention includes methods of forming openings into dielectric material. In one implementation, an opening is partially etched through dielectric material, with such opening comprising a lowest point and opposing sidewalls of the dielectric material. At least respective portions of the opposing sidewalls within the opening are lined with an electrically conductive material. With such electrically conductive material over said respective portions within the opening, plasma etching is conducted into and through the lowest point of the dielectric material of the opening to extend the opening deeper within the dielectric material. Other aspects and implementations are contemplated.
摘要翻译：本发明包括在电介质材料中形成开口的方法。在一个实施方案中，通过电介质材料部分蚀刻开口，其中这种开口包括介电材料的最低点和相对的侧壁。开口内的相对侧壁的至少相应部分衬有导电材料。通过在开口内的所述各个部分上的这种导电材料，等离子体蚀刻被导入并通过开口的电介质材料的最低点，以使电介质材料内的开口更深。考虑了其他方面和实现。

8. 发明申请

US20070001207A1 Double sided container capacitor for a semiconductor device and method for forming same 有权
标题翻译：用于半导体器件的双面容器电容器及其形成方法
公开(公告)号：US20070001207A1
公开(公告)日：2007-01-04
申请号：US11517045
申请日：2006-09-07
申请人： Thomas Graettinger , Marsela Pontoh , Thomas Figura
发明人： Thomas Graettinger , Marsela Pontoh , Thomas Figura
IPC分类号： H01L29/94
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： A method for forming a double sided container capacitor comprises forming a first capacitor top plate layer within a recess in a dielectric layer, then forming a first cell dielectric on the first top plate layer. Next, first and second bottom plate layers are formed on the first cell dielectric layer, and a second cell dielectric layer is formed on the second bottom plate layers. Finally, a second top plate layer is formed on the second cell dielectric layer, and the first and second top plate layers are electrically connected using a conductive plug or conductive spacer. An inventive structure formed using the inventive method is also described.
摘要翻译：一种用于形成双面容器电容器的方法包括在电介质层的凹槽内形成第一电容器顶板层，然后在第一顶板层上形成第一单元电介质。接下来，在第一单元电介质层上形成第一和第二底板层，在第二底板层上形成第二单元电介质层。最后，在第二单元电介质层上形成第二顶板层，并且使用导电插塞或导电间隔件将第一和第二顶板层电连接。还描述了使用本发明方法形成的本发明的结构。

9. 发明授权

US5891768A Method of forming a capacitor 失效
标题翻译：形成电容器的方法
公开(公告)号：US5891768A
公开(公告)日：1999-04-06
申请号：US807562
申请日：1997-02-28
申请人： Thomas Figura , Pierre C. Fazan
发明人： Thomas Figura , Pierre C. Fazan
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： A capacitor construction includes, a) first and second electrically conductive capacitor plates separated by an intervening capacitor dielectric layer, the first capacitor plate comprising first and second container members, the second container member being received inside of the first container member, the first and second container members comprising a respective ring portion and a respective base portion; and b) a pedestal disk positioned elevationally intermediate the first container member base and the second container member base to space and support the second container member relative to the first container member. The structure is preferably produced by using a series of alternating first and second layers of semiconductive material provided over a molding layer within a container contact opening therein. One of the first and second layers has an average conductivity enhancing dopant concentration of greater than about 5.times.10.sup.19 ions/cm.sup.3, with the other of the first and second layers having an average conductivity enhancing dopant concentration from 0 ions/cm.sup.3 to about 5.times.10.sup.19 ions/cm.sup.3. At least one of the first and second layers is selectively etchable relative to the other of the first and second layers to facilitate a container construction and formation of the pedestal disk. Utilization of alternate materials to the doped semiconductive material is also contemplated.
摘要翻译：一种电容器结构包括：a）由中间电容器介电层分隔开的第一和第二导电电容器板，所述第一电容器板包括第一和第二容器构件，所述第二容器构件容纳在所述第一容器构件的内部，所述第一和第二容器构件包括相应的环部分和相应的基部; 以及b）位于所述第一容器构件基部和所述第二容器构件基部的正中方的基座盘，以相对于所述第一容器构件间隔并支撑所述第二容器构件。该结构优选通过使用在其中的容器接触开口内的成型层上设置的一系列交替的半导体材料层来制造。第一层和第二层之一具有大于约5×1019离子/ cm3的平均导电性增强掺杂剂浓度，第一和第二层中的另一层具有从0离子/ cm 3至约5×10 19离子/ cm 3的平均导电性增强掺杂剂浓度。第一层和第二层中的至少一层相对于第一层和第二层中的另一层可选择性地蚀刻，以便于容器构造和基座盘的形成。也考虑了对掺杂半导体材料的替代材料的利用。

10. 发明申请

US20070123048A1 Use of a plasma source to form a layer during the formation of a semiconductor device 失效
公开(公告)号：US20070123048A1
公开(公告)日：2007-05-31
申请号：US11651158
申请日：2007-01-09
申请人： Thomas Figura , Kevin Donohoe , Thomas Dunbar
发明人： Thomas Figura , Kevin Donohoe , Thomas Dunbar
IPC分类号： H01L21/311
CPC分类号： H01L21/312 , H01L21/02129 , H01L21/32139 , H01L21/76865 , H01L28/40 , H01L28/60
摘要： A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.

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