专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090129192A1 DESIGN STRUCTURE FOR LOW OVERHEAD SWITCHED HEADER POWER SAVINGS APPARATUS 失效
标题翻译：低开关开关电源节省设备的设计结构
公开(公告)号：US20090129192A1
公开(公告)日：2009-05-21
申请号：US12116322
申请日：2008-05-07
申请人： John E. Barth, Jr. , Harold Pilo , Vinod Ramadurai
发明人： John E. Barth, Jr. , Harold Pilo , Vinod Ramadurai
IPC分类号： G11C5/14 , G11C8/00
CPC分类号： G11C8/08 , G11C5/147 , G11C5/148 , G11C8/12
摘要： A design structure embodied in a machine readable medium used in a design process includes a tri-state power gating apparatus for reducing leakage current in a memory array. The apparatus includes a first distributed header device coupled to the memory array, the first distributed header device is configured for limiting leakage current through the memory array; and a header driver operatively coupled to the first distributed header device for enabling tri-state operation of the first distributed header device, wherein tri-state operation includes sleep mode, wake mode, and retention mode.
摘要翻译：在设计过程中使用的机器可读介质中体现的设计结构包括用于减少存储器阵列中的漏电流的三态电源门控装置。所述装置包括耦合到所述存储器阵列的第一分配报头装置，所述第一分配报头装置被配置为限制通过所述存储器阵列的泄漏电流; 以及头部驱动器，其可操作地耦合到所述第一分配报头装置，用于实现所述第一分配报头装置的三态操作，其中三态操作包括睡眠模式，唤醒模式和保持模式。

2. 发明授权

US07400546B1 Low overhead switched header power savings apparatus 失效
标题翻译：低开销交换机头节能设备
公开(公告)号：US07400546B1
公开(公告)日：2008-07-15
申请号：US11940642
申请日：2007-11-15
申请人： John E. Barth, Jr. , Harold Pilo , Vinod Ramadurai
发明人： John E. Barth, Jr. , Harold Pilo , Vinod Ramadurai
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C8/12
摘要： A tri-state power gating apparatus for reducing leakage current in a memory array includes a first distributed header device coupled to the memory array, the first distributed header device is configured for limiting leakage current through the memory array; and a header driver operatively coupled to the first distributed header device for enabling tri-state operation of the first distributed header device, wherein tri-state operation includes sleep mode, wake mode, and retention mode.
摘要翻译：用于减少存储器阵列中的漏电流的三态电源门控装置包括耦合到存储器阵列的第一分布式头部装置，第一分配头部装置被配置为限制通过存储器阵列的漏电流; 以及头部驱动器，其可操作地耦合到所述第一分配报头装置，用于实现所述第一分配报头装置的三态操作，其中三态操作包括睡眠模式，唤醒模式和保持模式。

3. 发明授权

US06504766B1 System and method for early write to memory by injecting small voltage signal 失效
标题翻译：通过注入小电压信号来早期写入存储器的系统和方法
公开(公告)号：US06504766B1
公开(公告)日：2003-01-07
申请号：US09896734
申请日：2001-06-29
申请人： Harold Pilo , John E. Barth, Jr.
发明人： Harold Pilo , John E. Barth, Jr.
IPC分类号： G11C1604
CPC分类号： G11C7/062 , G11C7/18 , G11C11/4091 , G11C11/4094
摘要： A system and method is disclosed for writing early within a memory cycle by injecting a small voltage difference signal prior to setting a sense amplifier, and thereafter setting the sense amplifier which amplifies the small voltage signal to predetermined high and low voltage logic levels for writing to the memory cell. In this way, writing can complete in about the same time as reading, without risking corruption of data on adjacent bitlines in the memory. Local bitswitches apply first and second write voltages having a small voltage difference to a true bitline and a reference bitline prior to setting the sense amplifier.
摘要翻译：公开了一种系统和方法，用于在设置感测放大器之前通过注入小电压差信号在存储器周期内早期写入，然后设置将小电压信号放大到预定的高电压和低电压逻辑电平以便写入的读出放大器存储单元。以这种方式，写入可以在读取的同一时间内完成，而不会在存储器中的相邻位线上的数据损坏风险。在设置读出放大器之前，本地位开关将具有小电压差的第一和第二写入电压应用于真位置线和参考位线。

4. 发明授权

US07489582B1 Low overhead switched header power savings apparatus 失效
标题翻译：低开销交换机头节能设备
公开(公告)号：US07489582B1
公开(公告)日：2009-02-10
申请号：US12132005
申请日：2008-06-03
申请人： John E. Barth, Jr. , Harold Pilo , Vinod Ramadurai
发明人： John E. Barth, Jr. , Harold Pilo , Vinod Ramadurai
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C8/12
摘要： A method for reducing leakage current in a memory array comprising: coupling a first distributed header device to the memory array, the first distributed header device is configured for limiting leakage current through the memory array; and coupling a header driver operatively to the first distributed header device for enabling tri-state operation of the first distributed header device, wherein tri-state operation includes sleep mode, wake mode, and retention mode.
摘要翻译：一种用于减少存储器阵列中的漏电流的方法，包括：将第一分配报头装置耦合到存储器阵列，第一分配报头装置被配置为限制通过存储器阵列的泄漏电流; 以及将所述头部驱动器可操作地耦合到所述第一分布式报头装置，以实现所述第一分配报头装置的三态操作，其中三态操作包括睡眠模式，唤醒模式和保持模式。

5. 发明授权

US06400629B1 System and method for early write to memory by holding bitline at fixed potential 有权
标题翻译：通过将位线保持固定电位来提早写入内存的系统和方法
公开(公告)号：US06400629B1
公开(公告)日：2002-06-04
申请号：US09896746
申请日：2001-06-29
申请人： John E. Barth, Jr. , Harold Pilo
发明人： John E. Barth, Jr. , Harold Pilo
IPC分类号： G11C700
CPC分类号： G11C7/22 , G11C7/12 , G11C2207/104
摘要： A system and method is disclosed for writing early within a memory cycle by holding only one of a true bitline and a reference bitline at a fixed potential, e.g. ground, when the sense amplifier is set. The sense amplifier amplifies a small voltage difference between the true bitline and the reference bitline to predetermined high and low voltage logic levels to write a datum to the memory cell. In this way, writing can complete in about the same time as reading, without risking corruption of data on adjacent bitlines in the memory. The bitlines are precharged to a fixed potential in a conduction path through the bitswitches, rather than using local precharge devices at the sense amplifier. To write, bitswitches and write path transistors apply the fixed potential to one of the true bitline and the reference bitline. Bitswitches on such other memory cells not currently being written isolate the bitline pairs coupled to those memory cells when setting the sense amplifiers, such that the stored contents of such memory cells not being written are refreshed (written back) at the time that the selected memory cell is written.
摘要翻译：公开了一种系统和方法，用于通过仅保持固定电位的真正位线和参考位线中的一个，例如在存储器周期内早期写入。当感测放大器被设置时。读出放大器将真实位线和参考位线之间的小电压差放大到预定的高电压和低电压逻辑电平以将数据写入存储器单元。以这种方式，写入可以在读取的同一时间内完成，而不会在存储器中的相邻位线上的数据损坏风险。位线通过位开关预先充电到导通路径中的固定电位，而不是在读出放大器处使用局部预充电器件。要写入，位开关和写入通道晶体管将固定电位施加到真正的位线和参考位线之一。当设置感测放大器时，当前未被写入的其他存储器单元上的开关将隔开存储单元耦合的位线对，使得在所选择的存储器时刷新（回写）未被写入的存储单元的存储内容单元格是写的。

6. 发明授权

US07791977B2 Design structure for low overhead switched header power savings apparatus 失效
标题翻译：低开销交换机头节能设备的设计结构
公开(公告)号：US07791977B2
公开(公告)日：2010-09-07
申请号：US12116322
申请日：2008-05-07
申请人： John E. Barth, Jr. , Harold Pilo , Vinod Ramadurai
发明人： John E. Barth, Jr. , Harold Pilo , Vinod Ramadurai
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C5/147 , G11C5/148 , G11C8/12
摘要： A design structure embodied in a machine readable medium used in a design process includes a tri-state power gating apparatus for reducing leakage current in a memory array. The apparatus includes a first distributed header device coupled to the memory array, the first distributed header device is configured for limiting leakage current through the memory array; and a header driver operatively coupled to the first distributed header device for enabling tri-state operation of the first distributed header device, wherein tri-state operation includes sleep mode, wake mode, and retention mode.
摘要翻译：在设计过程中使用的机器可读介质中体现的设计结构包括用于减少存储器阵列中的漏电流的三态电源门控装置。所述装置包括耦合到所述存储器阵列的第一分配报头装置，所述第一分配报头装置被配置为限制通过所述存储器阵列的泄漏电流; 以及头部驱动器，其可操作地耦合到所述第一分配报头装置，用于实现所述第一分配报头装置的三态操作，其中三态操作包括睡眠模式，唤醒模式和保持模式。

7. 发明授权

US07724565B2 Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices 失效
标题翻译：使用PFET接入器件的SRAM单元中小信号感测的装置和方法
公开(公告)号：US07724565B2
公开(公告)日：2010-05-25
申请号：US11850992
申请日：2007-09-06
申请人： John E. Barth, Jr. , Geordie M. Braceras , Harold Pilo
发明人： John E. Barth, Jr. , Geordie M. Braceras , Harold Pilo
IPC分类号： G11C7/12 , G11C11/41 , G11C11/419 , G11C7/06
CPC分类号： G11C7/12 , G11C7/22 , G11C11/413 , G11C2207/005
摘要： A design structure embodied in a machine readable medium used in a design process for small signal sensing during a read operation of a static random access memory (SRAM) cell includes coupling a pair of complementary sense amplifier data lines to a corresponding pair of complementary bit lines associated with the SRAM cell, and setting a sense amplifier so as to amplify a signal developed on the sense amplifier data lines, wherein the bit line pair remains coupled to the sense amplifier data lines at the time the sense amplifier is set.
摘要翻译：在静态随机存取存储器（SRAM）单元的读取操作期间，在用于小信号感测的设计过程中使用的机器可读介质中的设计结构包括将一对互补读出放大器数据线耦合到相应的一对互补位线与SRAM单元相关联，以及设置读出放大器以放大在读出放大器数据线上产生的信号，其中位线对在读出放大器设置时保持耦合到读出放大器数据线。

8. 发明授权

US07061793B2 Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices 失效
标题翻译：使用PFET接入器件的SRAM单元中小信号感测的装置和方法
公开(公告)号：US07061793B2
公开(公告)日：2006-06-13
申请号：US10708713
申请日：2004-03-19
申请人： John E. Barth, Jr. , George M. Braceras , Harold Pilo
发明人： John E. Barth, Jr. , George M. Braceras , Harold Pilo
IPC分类号： G11C7/12 , G11C11/41 , G11C11/419 , G11C7/06
CPC分类号： G11C11/412
摘要： A method for small signal sensing during a read operation of a static random access memory (SRAM) cell includes coupling a pair of complementary sense amplifier data lines to a corresponding pair of complementary bit lines associated with the SRAM cell, and setting a sense amplifier so as to amplify a signal developed on the sense amplifier data lines, wherein the bit line pair remains coupled to the sense amplifier data lines at the time the sense amplifier is set.
摘要翻译：在静态随机存取存储器（SRAM）单元的读取操作期间用于小信号感测的方法包括将一对互补读出放大器数据线耦合到与SRAM单元相关联的对应的一对互补位线，并且将读出放大器设置为放大在感测放大器数据线上产生的信号，其中位线对在读出放大器设置时保持耦合到读出放大器数据线。

9. 发明授权

US08937345B2 Integrated circuits comprising an active transistor electrically connected to a trench capacitor by an overlying contact 有权
标题翻译：集成电路包括通过上覆触点与沟槽电容器电连接的有源晶体管
公开(公告)号：US08937345B2
公开(公告)日：2015-01-20
申请号：US13454635
申请日：2012-04-24
申请人： John E. Barth, Jr. , Kangguo Cheng , Michael Sperling , Geng Wang
发明人： John E. Barth, Jr. , Kangguo Cheng , Michael Sperling , Geng Wang
IPC分类号： H01L27/108 , H01L21/768 , H01L23/485
CPC分类号： H01L21/76895 , H01L23/485 , H01L27/10867 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; a passive transistor laterally spaced from the active transistor, wherein at least a portion of the trench capacitor is interposed between the active and passive transistors; an interlevel dielectric disposed upon the active and passive transistors; and a first conductive contact extending through the interlevel dielectric to the drain junction of the active transistor and the at least a portion of the trench capacitor between the active and passive transistors, wherein the first conductive contact electrically connects the trench capacitor to the drain junction of the active transistor.
摘要翻译：集成电路包括与形成在半导体衬底中的沟槽电容器横向相邻的有源晶体管，所述有源晶体管包括源极结和漏极结，其中阻挡层沿着所述沟槽电容器的外围设置以隔离所述沟槽电容器; 与有源晶体管横向隔开的无源晶体管，其中所述沟槽电容器的至少一部分插入在所述有源和无源晶体管之间; 布置在有源和无源晶体管上的层间电介质; 以及第一导电接触件，其延伸穿过所述有源晶体管的所述有源晶体管和所述沟槽电容器的所述至少一部分的所述层间电介质的漏极结到所述有源和无源晶体管之间，其中所述第一导电接触将所述沟槽电容器电连接到所述沟道电容器有源晶体管。

10. 发明授权

US08263472B2 Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices 失效
标题翻译：用于绝缘体上硅（SOI）器件的深沟槽静电放电（ESD）保护二极管
公开(公告)号：US08263472B2
公开(公告)日：2012-09-11
申请号：US13324486
申请日：2011-12-13
申请人： John E. Barth, Jr. , Kerry Bernstein
发明人： John E. Barth, Jr. , Kerry Bernstein
IPC分类号： H01L21/76
CPC分类号： H01L29/861 , H01L21/761 , H01L21/76264 , H01L23/535 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.
摘要翻译：半导体包括第一极性类型的体基板，设置在体基板上的掩埋绝缘体层，设置在包括浅沟槽隔离区域和第一极性类型的扩散区域的掩埋绝缘体层的顶部上的有源半导体层，第二极性类型的带区域直接设置在掩埋绝缘体层的正下方并形成导电路径，第二极性类型的阱区域布置在本体衬底中并与带区域接触，填充有导电材料的深沟槽设置在阱区内的第一极性类型和由深沟槽的下部与阱区之间的接合部限定的静电放电（ESD）保护二极管。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式