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1. 发明申请

US20050088286A1 Radio frequency identification system with write broadcast capability 失效
标题翻译：具有写广播能力的射频识别系统
公开(公告)号：US20050088286A1
公开(公告)日：2005-04-28
申请号：US10898888
申请日：2004-07-26
申请人： Harley Heinrich , Christian Cesar , Thomas Cofino , Daniel Friedman , Kenneth Goldman , Sharon Greene , Kevin McAuliffe , Shun-Shing Chan
发明人： Harley Heinrich , Christian Cesar , Thomas Cofino , Daniel Friedman , Kenneth Goldman , Sharon Greene , Kevin McAuliffe , Shun-Shing Chan
IPC分类号： G05B19/042 , G06K7/00 , G06K17/00 , G07C9/00 , G08C17/02 , H04Q5/22
CPC分类号： G06K7/10108 , G05B19/0421 , G05B2219/2231 , G05B2219/25277 , G06K7/0008 , G06K7/10039 , G06K2017/0048 , G07C9/00111 , G08C17/02 , G08C2201/20
摘要： A Write Broadcast system and method uses a base station to write sent data to all or some selected number (sub group) of tags in a base station field simultaneously. By unselecting the tags that have been successfully written to, and requesting a response from the remaining tags in the field (or sub group), the system determines, by receiving a response to the request, that there are tags in the field (sub group) that were unsuccessfully written to. Another Write Broadcast signal is sent to these tags. The system is useful for quickly (simultaneously) “stamping” information on the tag memory of a large number of tags in the field of the base station.
摘要翻译：写广播系统和方法使用基站将发送的数据同时写入基站字段中的所有或某些选定号码（子组）的标签。通过取消选择已成功写入的标签，并请求来自字段（或子组）中的其余标签的响应，系统通过接收对该请求的响应来确定在该字段（子组）中存在标签）没有成功。另一个写广播信号被发送到这些标签。该系统对于在基站领域中的大量标签的标签存储器上快速（同时）“冲压”信息是有用的。

2. 发明申请

US20050001724A1 Diode receiver for radio frequency transponder 有权
标题翻译：射频应答器二极管接收器
公开(公告)号：US20050001724A1
公开(公告)日：2005-01-06
申请号：US10770341
申请日：2004-02-02
申请人： Harley Heinrich , Daniel Friedman
发明人： Harley Heinrich , Daniel Friedman
IPC分类号： G01S13/75 , G06K7/00 , G06K19/07 , H01Q1/22 , H01Q21/29 , G08B13/14
CPC分类号： G06K7/0008 , G01S13/758 , G06K19/0701 , G06K19/0713 , G06K19/0723 , H01Q1/22 , H01Q1/2225 , H01Q21/29
摘要： A passive radio frequency transponder (RF tag) having a diode rectifier receiver circuit outside the tag power rectification circuit, the tag power rectification circuit supplying power to the electronics of the RF tag. An additional innovative low current circuit protect the signal capacitor from overvoltage produced by the signal diode. An innovative circuit also clips the signal and sharpens it. An innovative low current circuit is used as a comparator to sharpen the signal pulses.
摘要翻译：一种在标签电源整流电路外部具有二极管整流器接收器电路的无源射频转发器（RF标签），标签电力整流电路向RF标签的电子设备供电。额外的创新的低电流电路保护信号电容免受信号二极管产生的过压。创新的电路也会剪辑信号并使其变亮。创新的低电流电路用作比较器来锐化信号脉冲。

3. 发明授权

US07913202B2 Wafer level I/O test, repair and/or customization enabled by I/O layer 有权
标题翻译：通过I / O层启用晶圆级I / O测试，修复和/或定制
公开(公告)号：US07913202B2
公开(公告)日：2011-03-22
申请号：US11945308
申请日：2007-11-27
申请人： Kerry Bernstein , Paul Coteus , Ibrahim M. Elfadel , Philip Emma , Daniel Friedman , Ruchir Puri , Mark B. Ritter , Jeannine Trewhella , Albert M. Young
发明人： Kerry Bernstein , Paul Coteus , Ibrahim M. Elfadel , Philip Emma , Daniel Friedman , Ruchir Puri , Mark B. Ritter , Jeannine Trewhella , Albert M. Young
IPC分类号： G06F17/50
CPC分类号： G11C29/006 , G11C29/12 , G11C29/1201 , G11C2029/1206
摘要： A design structure for a 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.
摘要翻译：一种用于3D芯片的设计结构，其具有通过垂直总线连接到其它3D芯片层的至少一个I / O层，使得I / O层可适应保护和片外器件驱动电路，定制电路，平移电路，转换电路和/或能够进行全面芯片或晶片级测试的内置自检电路，其中I / O层用作测试头。 I / O电路或结构的替代可以使用响应于这种测试的电子熔断器等进行。

4. 发明申请

US20080068039A1 Wafer Level I/O Test, Repair and/or Customization Enabled by I/O layer 有权
标题翻译：由I / O层启用的晶片级I / O测试，修复和/或定制
公开(公告)号：US20080068039A1
公开(公告)日：2008-03-20
申请号：US11945308
申请日：2007-11-27
申请人： Kerry Bernstein , Paul Coteus , Ibrahim Elfadel , Philip Emma , Daniel Friedman , Ruchir Puri , Mark Ritter , Jeannine Trewhella , Albert Young
发明人： Kerry Bernstein , Paul Coteus , Ibrahim Elfadel , Philip Emma , Daniel Friedman , Ruchir Puri , Mark Ritter , Jeannine Trewhella , Albert Young
IPC分类号： H03K19/00
CPC分类号： G11C29/006 , G11C29/12 , G11C29/1201 , G11C2029/1206
摘要： A design structure for a 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.
摘要翻译：一种用于3D芯片的设计结构，其具有通过垂直总线连接到其它3D芯片层的至少一个I / O层，使得I / O层可适应保护和片外器件驱动电路，定制电路，平移电路，转换电路和/或能够进行全面芯片或晶片级测试的内置自检电路，其中I / O层用作测试头。 I / O电路或结构的替代可以使用响应于这种测试的电子熔断器等进行。

5. 发明申请

US20070222530A1 HYBRID CURRENT-STARVED PHASE-INTERPOLATION CIRCUIT FOR VOLTAGE-CONTROLLED DEVICES 有权
标题翻译：用于电压控制器件的混合电流相位插值电路
公开(公告)号：US20070222530A1
公开(公告)日：2007-09-27
申请号：US11369475
申请日：2006-03-07
申请人： Woogeun Rhee , Daniel Friedman
发明人： Woogeun Rhee , Daniel Friedman
IPC分类号： H03L7/00 , H03K3/03
CPC分类号： H03L7/0812 , H03K3/0322 , H03K5/133 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208
摘要： A hybrid circuit includes a current-starved voltage-controlled circuit configured to adjust a first type of signal difference, and a phase-interpolated voltage controlled circuit configured to adjust a second type of signal difference. The current-starved circuit and the phase-interpolated circuit cooperate to provide improved operational performance of the hybrid circuit.
摘要翻译：混合电路包括被配置为调整第一类型的信号差的电流饥饿电压控制电路，以及被配置为调整第二类型的信号差的相位插值电压控制电路。当前饥饿电路和相位插值电路协作，以提供混合电路的改进的操作性能。

6. 发明申请

US20070081410A1 WAFER LEVEL I/O TEST AND REPAIR ENABLED BY I/O LAYER 失效
标题翻译：由I / O层启用的WAFER LEVEL I / O测试和维修
公开(公告)号：US20070081410A1
公开(公告)日：2007-04-12
申请号：US11163167
申请日：2005-10-07
申请人： Kerry Bernstein , Paul Coteus , Ibrahim Elfadel , Philip Emma , Daniel Friedman , Ruchir Puri , Mark Ritter , Jeannine Trewhella , Albert Young
发明人： Kerry Bernstein , Paul Coteus , Ibrahim Elfadel , Philip Emma , Daniel Friedman , Ruchir Puri , Mark Ritter , Jeannine Trewhella , Albert Young
IPC分类号： G11C8/00
CPC分类号： G11C29/006 , G11C29/12 , G11C29/1201 , G11C2029/1206
摘要： A 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.
摘要翻译：具有至少一个I / O层的3D芯片，其通过垂直总线连接到其他3D芯片层，使得所述I / O层可适应保护和芯片外设备驱动电路，定制电路，平移电路，转换电路和/或能够进行全面的芯片或晶片级测试的内置自检电路，其中I / O层用作测试头。 I / O电路或结构的替代可以使用响应于这种测试的电子熔断器等进行。

7. 发明申请

US20060238265A1 Method to differentially control LC voltage-controlled oscillators 有权
标题翻译：差分控制LC压控振荡器的方法
公开(公告)号：US20060238265A1
公开(公告)日：2006-10-26
申请号：US11112527
申请日：2005-04-22
申请人： Babak Soltanian , Herschel Ainspan , Daniel Friedman , Woogeun Rhee
发明人： Babak Soltanian , Herschel Ainspan , Daniel Friedman , Woogeun Rhee
IPC分类号： H03B5/08
CPC分类号： H03L7/099 , H03B5/1209 , H03B5/1228 , H03B5/1253 , H03B2201/0208 , H03L2207/06
摘要： A method of differentially controlling an LC voltage controlled oscillator (VCO) includes providing an LC-VCO comprising at least one inductor, measuring an inductor common voltage (CMV) output at a point along the at least one inductor, utilizing the measured inductor CMV as an input to a charge pump, and outputting from the charge pump a plurality of differential control voltages to control an output of the LC-VCO.
摘要翻译：一种差分控制LC压控振荡器（VCO）的方法包括提供包括至少一个电感器的LC-VCO，测量沿着至少一个电感器的点处的电感器公共电压（CMV）输出，利用测量的电感器CMV作为电荷泵的输入，并从电荷泵输出多个差分控制电压以控制LC-VCO的输出。

8. 发明申请

US20170214145A1 TWO-DIMENSIONAL SCANNING CYLINDRICAL REFLECTOR 审中-公开
公开(公告)号：US20170214145A1
公开(公告)日：2017-07-27
申请号：US15005018
申请日：2016-01-25
申请人： Danny Elad , Daniel Friedman , Noam Kaminski , Ofer Markish , Alberto Valdes Garcia
发明人： Danny Elad , Daniel Friedman , Noam Kaminski , Ofer Markish , Alberto Valdes Garcia
IPC分类号： H01Q15/14 , H01Q3/02
CPC分类号： H01Q3/18 , H01Q3/12 , H01Q3/16 , H01Q3/2658 , H01Q19/175
摘要： A parabolic cylindrical reflector antenna that comprises two or more antenna feeds each directed towards a parabolic cylindrical reflector, wherein the antenna feeds are positioned in one or more line-arrays parallel to a focal line of the parabolic cylindrical reflector, and the line-array is substantially centered opposing the reflector. The antenna comprises a controller configured to scan along a straight edge of the reflector by electronically adjusting a phase of each of the antenna feeds, thereby changing the incident angle of an energy beam relative to the reflector. The controller is configured to scan along a curved edge of the reflector by moving, using a mechanical positioning mechanism, the antenna feeds in a direction parallel to a directrix of the reflector while maintaining the positioning or by electronically selecting one of two or more parallel line-arrays.

9. 发明授权

US07953820B2 Method and system for providing enhanced performance of web browsing 有权
标题翻译：提高Web浏览性能的方法和系统
公开(公告)号：US07953820B2
公开(公告)日：2011-05-31
申请号：US10659486
申请日：2003-09-10
申请人： Patrick Stevens , Daniel Friedman , Robert Torres , Vaibhav Kumar
发明人： Patrick Stevens , Daniel Friedman , Robert Torres , Vaibhav Kumar
IPC分类号： G06F15/16
CPC分类号： H04L67/2814 , G06F17/30902 , H04L29/06027 , H04L65/105 , H04L67/02 , H04L67/2804 , H04L67/2847 , H04L67/2876 , H04L69/329
摘要： An approach is provided for supporting retrieval of web content over a meshed communication network (111). A first server (105) receives a request from a browser application (103) for the content resident in the web server (109). The first server (105) includes a downstream proxy (401) configured to modify the request to include information specifying support of a parse and pre-fetch service within an optional header field of the request as to permit handling of the modified request by the web server (109) in absence of an upstream proxy (403) that is communicating with the web server (109). A second server (107) is configured as the upstream proxy (403) to intercept the modified request and pre-fetch the content from the web server (109). The second server (107) forwards the pre-fetched content over the communication network (111) to the first server (105). This approach has particular applicability in relatively high latency networks, such as a satellite communications system.
摘要翻译：提供了一种用于支持通过网状通信网络（111）检索网页内容的方法。第一服务器（105）从用于驻留在web服务器（109）中的内容的浏览器应用（103）接收请求。第一服务器（105）包括下游代理（401），其被配置为修改请求以包括在请求的可选报头字段内指定解析和预取服务的支持的信息，以允许由web处理修改的请求服务器（109）在没有与web服务器（109）通信的上游代理（403）的情况下。第二服务器（107）被配置为上游代理（403），以拦截修改的请求并从网络服务器（109）预取内容。第二服务器（107）通过通信网络（111）将预先获取的内容转发到第一服务器（105）。这种方法在诸如卫星通信系统的相对高延迟的网络中具有特别的适用性。

10. 发明申请

US20090206952A1 DELAY LINE REGULATION USING HIGH-FREQUENCY MICRO-REGULATORS 有权
标题翻译：使用高频微调节器进行延时线路调节
公开(公告)号：US20090206952A1
公开(公告)日：2009-08-20
申请号：US12030946
申请日：2008-02-14
申请人： Daniel Dreps , Daniel Friedman , Seongwon Kim , Hector Saenz , Glen Wiedemeier
发明人： Daniel Dreps , Daniel Friedman , Seongwon Kim , Hector Saenz , Glen Wiedemeier
IPC分类号： H03H7/00
CPC分类号： H03H11/265
摘要： A regulated delay line device includes main regulator coupled to a node, and a plurality of delay branches coupled to the node to receive a voltage output to the node by the main regulator. Each of the plurality of delay branches includes a micro-regulator and a delay line. The delay line is coupled to the micro-regulator such that unfiltered noise is removed locally at each delay branch by a corresponding micro-regulator.
摘要翻译：稳定的延迟线装置包括耦合到节点的主调节器和耦合到节点的多个延迟分支，以通过主调节器接收到节点的电压输出。多个延迟分支中的每一个包括微调节器和延迟线。延迟线耦合到微调节器，使得在每个延迟分支处通过相应的微调节器局部去除未滤波的噪声。

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