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1. 发明授权

US6069082A Method to prevent dishing in damascene CMP process 失效
标题翻译：防止镶嵌CMP工艺中凹陷的方法
公开(公告)号：US6069082A
公开(公告)日：2000-05-30
申请号：US170734
申请日：1998-10-13
申请人： Harianto Wong , John Leonard Sudijono
发明人： Harianto Wong , John Leonard Sudijono
IPC分类号： H01L21/321 , H01L21/768 , H01L21/302
CPC分类号： H01L21/3212 , H01L21/7684 , H01L21/76877
摘要： A method of fabrication of a metal lines without dishing using damascene and chemical-mechanical polish processes. A Key feature is the hard cap layer that is only formed over the trench opening. The hard cap layer prevents dishing of the metal line and also allows faster CMP than blanket polish stop layers. The method includes forming a first dielectric layer having a first trench opening over a semiconductor structure. A metal layer is deposited in the first trench opening. The metal layer has a dimple. The metal layer is preferably composed of Al or Cu. A hard mask is formed having a first opening over the first trench opening. The first opening is at least partially over first trench opening. A hard cap layer (e.g., W or WSi.sub.x) is selectively deposited on the metal layer exposed in the first opening. The hard cap layer, the hard mask, and the metal layer are chemical-mechanical polished to completely remove the hard mask resulting in a metal line having a "dishing free" flat top surface. The chemical-mechanical polish rate of the hard cap is less than the rate of the metal layer.
摘要翻译：使用镶嵌和化学机械抛光工艺制造金属线而不进行凹陷的方法。一个主要特征是仅在沟槽开口形成的硬覆盖层。硬盖层防止金属线的凹陷，并且还允许比橡皮布抛光停止层更快的CMP。该方法包括形成具有在半导体结构上开口的第一沟槽的第一介电层。金属层沉积在第一沟槽开口中。金属层有凹坑。金属层优选由Al或Cu组成。在第一沟槽开口上形成有第一开口的硬掩模。第一开口至少部分地超过第一沟槽开口。在第一开口中暴露的金属层上选择性地沉积硬覆盖层（例如W或WSix）。硬盖层，硬掩模和金属层进行化学机械抛光，以完全去除硬掩模，从而形成具有“无凹槽”的平坦顶表面的金属线。硬帽的化学机械抛光速率小于金属层的速率。

2. 发明申请

US20080108202A1 PRECISION HIGH-FREQUENCY CAPACITOR FORMED ON SEMICONDUCTOR SUBSTRATE 有权
标题翻译：精密高频电容器在半导体衬底上形成
公开(公告)号：US20080108202A1
公开(公告)日：2008-05-08
申请号：US11966965
申请日：2007-12-28
申请人： Haim Goldberger , Sik Lui , Jacek Korec , Y. Kasem , Harianto Wong , Jack Van Den Heuvel
发明人： Haim Goldberger , Sik Lui , Jacek Korec , Y. Kasem , Harianto Wong , Jack Van Den Heuvel
IPC分类号： H01L21/283
CPC分类号： H01G4/33 , H01G4/38 , H01L23/481 , H01L28/40 , H01L29/66181 , H01L29/945 , H01L2224/0401 , H01L2224/05 , H01L2224/13025 , H01L2224/131 , H01L2924/13091 , Y10S438/957 , H01L2924/014 , H01L2924/00
摘要： A method of fabricating a capacitor in a semiconductor substrate. The semiconductor substrate is doped to have a low resistivity. A second electrode, insulated from a first electrode, is formed over a front side surface and connected by a metal-filled via to the back side surface. The via may be omitted and the second electrode may be in electrical contact with the substrate or may be formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor is provided by a pair of oppositely-directed diodes formed in the substrate connected in parallel with the capacitor. Capacitance is increased while maintaining a low effective series resistance. Electrodes include a plurality of fingers, which are interdigitated with the fingers of other electrode. The capacitor is fabricated in a wafer-scale process with other capacitors, where capacitors are separated from each other by a dicing technique.
摘要翻译：一种在半导体衬底中制造电容器的方法。掺杂半导体衬底以具有低电阻率。与第一电极绝缘的第二电极形成在前侧表面上，并且通过金属填充的通孔连接到背侧表面。可以省略通孔，并且第二电极可以与衬底电接触，或者可以形成在介电层的顶部，从而产生一对串联电容器。电容器的ESD保护由形成在与电容器并联连接的衬底中的一对相反方向的二极管提供。电容增加同时保持低有效的串联电阻。电极包括多个指状物，其与另一个电极的指状物交叉指向。电容器采用具有其他电容器的晶片级工艺制造，其中电容器通过切割技术彼此分离。

3. 发明授权

US5869396A Method for forming a polycide gate electrode 失效
标题翻译：多晶硅栅电极的形成方法
公开(公告)号：US5869396A
公开(公告)日：1999-02-09
申请号：US679974
申请日：1996-07-15
申请人： Yang Pan , Harianto Wong
发明人： Yang Pan , Harianto Wong
IPC分类号： H01L21/28 , H01L21/285 , H01L21/4763
CPC分类号： H01L21/28518 , H01L21/28052
摘要： A method for forming within a Field Effect Transistor (FET) for use within an integrated circuit a polycide gate electrode. There is first provided a semiconductor substrate. Formed upon the semiconductor is a patterned polysilicon layer. Formed then upon the semiconductor substrate and the patterned polysilicon layer is a blanket insulator layer. The blanket insulator layer is then patterned through planarizing to form a patterned planarized insulator layer while simultaneously exposing the surface of the patterned polysilicon layer. Finally, there is formed upon the exposed surface of the patterned polysilicon layer a patterned metal silicide layer. The patterned metal silicide layer and the patterned polysilicon layer form a polycide gate electrode. The metal silicide layer within the polycide gate electrode is not susceptible to encroachment upon adjoining insulator spacers or source/drain regions within the Field Effect Transistor (FET) within which is formed the polycide gate electrode.
摘要翻译：一种在场效应晶体管（FET）内形成用于在集成电路内使用多晶硅栅电极的方法。首先提供半导体衬底。在半导体上形成图案化多晶硅层。然后形成在半导体衬底上，并且图案化的多晶硅层是覆盖绝缘体层。然后通过平坦化图案化覆盖绝缘体层以形成图案化的平坦化绝缘体层，同时暴露图案化多晶硅层的表面。最后，在图案化的多晶硅层的暴露的表面上形成图案化的金属硅化物层。图案化的金属硅化物层和图案化的多晶硅层形成多晶硅栅极电极。多晶硅栅极电极内的金属硅化物层不易受到形成多晶硅栅极电极的场效应晶体管（FET）内邻接的绝缘体间隔物或源极/漏极区的侵扰。

4. 外观设计

USD719115S1 Housing for an electronic device 有权
公开(公告)号：USD719115S1
公开(公告)日：2014-12-09
申请号：US29449441
申请日：2013-03-15
申请人： Shixi Louis Liu , Harianto Wong , Paul David , John B. Sauber , Shaun D. Milano , Raguvir Kanda , Bruce Hemenway
设计人： Shixi Louis Liu , Harianto Wong , Paul David , John B. Sauber , Shaun D. Milano , Raguvir Kanda , Bruce Hemenway

5. 发明申请

US20140264678A1 PACKAGING FOR AN ELECTRONIC DEVICE 有权
标题翻译：包装电子设备
公开(公告)号：US20140264678A1
公开(公告)日：2014-09-18
申请号：US13834617
申请日：2013-03-15
申请人： SHIXI LOUIS LIU , Harianto Wong , Paul David , John B. Sauber , Shaun D. Milano , Raguvir Kanda , Bruce Hemenway
发明人： SHIXI LOUIS LIU , Harianto Wong , Paul David , John B. Sauber , Shaun D. Milano , Raguvir Kanda , Bruce Hemenway
IPC分类号： H01L43/04 , H01L23/00 , H01L21/48
CPC分类号： H01L43/14 , G01R15/202 , G01R15/207 , G01R33/0052 , G01R33/09 , H01L21/4828 , H01L23/49548 , H01L24/13 , H01L24/16 , H01L24/81 , H01L43/04 , H01L43/065 , H01L2224/131 , H01L2224/16245 , H01L2224/81801 , H01L2924/15162 , H01L2924/014 , H01L2924/00014
摘要： In one aspect, a method includes processing a metal substrate, performing a first etch on a first surface of the metal substrate to form, for an integrated circuit package, secondary leads and a curved component having two primary leads and performing a second etch, on a second surface of the substrate opposite the first surface, at locations on the secondary leads and locations on the curved component to provide a locking mechanism. Each primary lead located at a respective end of the curved component.
摘要翻译：在一个方面，一种方法包括处理金属衬底，在金属衬底的第一表面上执行第一蚀刻，以形成用于集成电路封装的次级引线和具有两个初级引线并执行第二次蚀刻的弯曲元件所述基板的与所述第一表面相对的第二表面，在所述次级引线上的位置和所述弯曲部件上的位置处，以提供锁定机构。每个主引线位于弯曲部件的相应端部。

6. 发明授权

US08384183B2 Integrated hall effect element having a germanium hall plate 有权
标题翻译：具有锗霍尔板的集成霍尔效应元件
公开(公告)号：US08384183B2
公开(公告)日：2013-02-26
申请号：US12708855
申请日：2010-02-19
申请人： Harianto Wong , William P. Taylor , Ravi Vig
发明人： Harianto Wong , William P. Taylor , Ravi Vig
IPC分类号： H01L21/00
CPC分类号： H01L43/065
摘要： An integrated circuit and a method of making the integrated circuit provide a Hall effect element having a germanium Hall plate. The germanium Hall plate provides an increased electron mobility compared with silicon, and therefore, a more sensitive Hall effect element.
摘要翻译：集成电路和制造集成电路的方法提供具有锗霍尔板的霍尔效应元件。与硅相比，锗霍尔板提供了增加的电子迁移率，因此是更敏感的霍尔效应元件。

7. 发明授权

US6017803A Method to prevent dishing in chemical mechanical polishing 失效
标题翻译：化学机械抛光防止凹陷的方法
公开(公告)号：US6017803A
公开(公告)日：2000-01-25
申请号：US104034
申请日：1998-06-24
申请人： Harianto Wong
发明人： Harianto Wong
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/76
CPC分类号： H01L21/76847 , H01L21/31053 , H01L21/76224
摘要： A method is described for filling trenches in a substrate for shallow trench isolation or for a metal damascene structure which will prevent dishing when the substrate is planarized using chemical mechanical polishing. Trenches are formed in the substrate. A layer of first material is formed on the substrate, sidewalls of the trench, and bottom of the trench. A layer of second material is then formed on the layer of first material. The substrate is then planarized using a chemical mechanical polishing. The first material, second material, and parameters of the chemical mechanical polishing are chosen so that the removal rate of the first material is greater than the removal rate of the second material. The chemical mechanical polishing then results in a planar substrate with no dishing.
摘要翻译：描述了一种用于在用于浅沟槽隔离的衬底中填充沟槽的方法或用于当使用化学机械抛光使衬底平坦化时防止凹陷的金属镶嵌结构的方法。在底物中形成沟槽。在衬底，沟槽的侧壁和沟槽的底部上形成第一材料层。然后在第一材料层上形成第二材料层。然后使用化学机械抛光使基底平坦化。选择化学机械抛光的第一材料，第二材料和参数，使得第一材料的去除速率大于第二材料的去除速率。然后，化学机械抛光产生没有凹陷的平面基板。

8. 发明授权

US08324711B2 Precision high-frequency capacitor formed on semiconductor substrate 有权
标题翻译：精密高频电容器形成于半导体基板上
公开(公告)号：US08324711B2
公开(公告)日：2012-12-04
申请号：US13075752
申请日：2011-03-30
申请人： Haim Goldberger , Sik Lui , Jacek Korec , Y. Mohammed Kasem , Harianto Wong , Jack Van Den Heuvel
发明人： Haim Goldberger , Sik Lui , Jacek Korec , Y. Mohammed Kasem , Harianto Wong , Jack Van Den Heuvel
IPC分类号： H01L21/02
CPC分类号： H01G4/33 , H01G4/38 , H01L23/481 , H01L28/40 , H01L29/66181 , H01L29/945 , H01L2224/0401 , H01L2224/05 , H01L2224/13025 , H01L2224/131 , H01L2924/13091 , Y10S438/957 , H01L2924/014 , H01L2924/00
摘要： A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor. To increase the capacitance of the capacitor while maintaining a low effective series resistance, each of the electrodes may include a plurality of fingers, which are interdigitated with the fingers of the other electrode. The capacitor is preferably fabricated in a wafer-scale process concurrently with numerous other capacitors on the wafer, and the capacitors are then separated from each other by a conventional dicing technique.
摘要翻译：精密高频电容器包括形成在半导体衬底的前侧表面上的电介质层和位于电介质层顶部的第一电极。半导体衬底是重掺杂的，因此具有低电阻率。与第一电极绝缘的第二电极也形成在前侧表面上。在一个实施例中，第二电极通过金属填充的通孔连接到衬底背面上的导电材料层。在替代实施例中，省略通孔，并且第二电极与衬底电接触或者形成在电介质层的顶部，从而产生一对串联电容器。电容器的ESD保护可以由形成在衬底中并与电容器并联连接的一对相反方向的二极管提供。为了在保持低有效串联电阻的同时增加电容器的电容，每个电极可以包括与另一个电极的指状物交叉的多个指状物。电容器优选与晶片上的许多其它电容器同时地以晶片级工艺制造，然后通过常规的切割技术将电容器彼此分离。

9. 发明授权

US5956137A In-line process monitoring using micro-raman spectroscopy 失效
标题翻译：使用微拉曼光谱的在线过程监控
公开(公告)号：US5956137A
公开(公告)日：1999-09-21
申请号：US186389
申请日：1998-11-05
申请人： Eng Hua Lim , Kin-Leong Pey , Harianto Wong , Kong Hean Lee
发明人： Eng Hua Lim , Kin-Leong Pey , Harianto Wong , Kong Hean Lee
IPC分类号： G01J3/44 , H01L21/00
CPC分类号： G01J3/44
摘要： An in-line non-destructive method is described for identifying phases in a micro-structure such as a fine line pattern. This is accomplished by observing the Raman spectrum of the micro-structure. A particular application is a silicide layer, prepared using the SALICIDE process, where the crystal phases before and after Rapid Thermal Anneal are often different. This is reflected by the appearance of different lines in the Raman spectra so that the fraction of each phase can be determined. If the silicide layer agglomerated during the anneal, this is also detected by the Raman spectrum. The method has been used successfully down to line widths of about 0.35 microns.
摘要翻译：描述了用于识别诸如细线图案的微结构中的相位的在线非破坏性方法。这是通过观察微结构的拉曼光谱来实现的。特别的应用是使用SALICIDE工艺制备的硅化物层，其中快速热退火之前和之后的晶相通常是不同的。这反映在拉曼光谱中不同线的出现，从而可以确定每相的分数。如果在退火期间硅化物层凝聚，则这也由拉曼光谱检测。该方法已被成功地应用到约0.35微米的线宽。

10. 发明授权

US5731239A Method of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistance 失效
标题翻译：制造具有低薄层电阻的场效应晶体管的自对准硅化物窄栅电极的方法
公开(公告)号：US5731239A
公开(公告)日：1998-03-24
申请号：US787193
申请日：1997-01-22
申请人： Harianto Wong , Kin Leong Pey , Lap Chan
发明人： Harianto Wong , Kin Leong Pey , Lap Chan
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/66507 , H01L21/28052 , H01L29/665 , H01L29/6659 , H01L29/66545
摘要： A method for making low sheet resistance sub-quarter-micrometer gate electrode lengths on field effect transistors has been achieved. The method involves patterning gate electrodes on a silicon substrate from a conductively doped polysilicon layer having a silicon nitride layer on the surface. After forming the FET lightly doped drains (LDD), the sidewall spacers, and the heavily doped source/drain contact regions with titanium contacts, an insulating layer is chemically/mechanically polished back to the silicon nitride or silicon oxynitride on the gate electrode layer to form a planar self-aligning mask. A pre-amorphizing implantation is carried out, and a titanium silicide is selectively formed on the gate electrodes resulting in small grain sizes and much reduced sheet resistance. The self-aligned mask prevents ion implant damage to the shallow source/drain regions adjacent to the FET gate electrodes. A second embodiment uses the self-aligned mask to form selectively a cobalt silicide on the polysilicon gate electrodes for low sheet resistance, while preventing the cobalt silicide from reacting with the adjacent titanium silicide source/drain regions.
摘要翻译：已经实现了在场效应晶体管上制造低薄层电阻亚四分之一微米栅电极长度的方法。该方法包括从表面上具有氮化硅层的导电掺杂多晶硅层在硅衬底上图案化栅电极。在形成FET轻掺杂漏极（LDD），侧壁间隔物和具有钛触点的重掺杂源极/漏极接触区域之后，绝缘层被化学/机械地抛光回到栅极电极层上的氮化硅或氮氧化硅，至形成平面自对准掩模。进行预非晶化注入，并且在栅电极上选择性地形成硅化钛，导致小的晶粒尺寸和大大降低的薄层电阻。自对准掩模防止离子注入损坏与FET栅电极相邻的浅源/漏区。第二实施例使用自对准掩模在多晶硅栅电极上选择性地形成钴硅化物，用于低电阻，同时防止钴硅化物与相邻的硅化钛源极/漏极区发生反应。

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