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1. 发明授权

US06352896B1 Method of manufacturing DRAM capacitor 失效
标题翻译：制造DRAM电容的方法
公开(公告)号：US06352896B1
公开(公告)日：2002-03-05
申请号：US09618597
申请日：2000-07-17
申请人： Haochieh Liu , Hsi-Chuan Chen , Jung-Ho Chang , Hong-Hsiang Tsai , Li-Ming Wang , Sen-Huan Huang , Bor-Ru Sheu , Wen-Kuei Hsieh
发明人： Haochieh Liu , Hsi-Chuan Chen , Jung-Ho Chang , Hong-Hsiang Tsai , Li-Ming Wang , Sen-Huan Huang , Bor-Ru Sheu , Wen-Kuei Hsieh
IPC分类号： H01L218242
CPC分类号： H01L27/10855 , H01L27/10814 , H01L27/10885 , H01L27/10888
摘要： A method of manufacturing DRAM capacitor. An active region is formed above a substrate. A plurality of parallel word lines is formed above the substrate. A first plug and a second plug are formed between the word lines in locations for forming the desired bit line contact and node contact, respectively. Insulation material is deposited into the remaining space between the word lines. A bit line contact is formed above the first plug. A plurality of parallel bit lines is formed above the substrate. The bit lines are perpendicular to the word lines. The bit line is electrically connected to the substrate through the bit line contact and the first plug. The bit lines are electrically insulated from each other. Furthermore, each bit line is covered on top by a hard material layer. Finally, a node contact is formed over the second plug.
摘要翻译：制造DRAM电容器的方法。在衬底上形成有源区。在基板上方形成多条平行字线。第一插头和第二插头分别形成在用于形成所需位线接触和节点接触的位置之间的字线之间。绝缘材料沉积在字线之间的剩余空间中。在第一插头上形成位线接触。在衬底上形成多个并行位线。位线垂直于字线。位线通过位线接触和第一插头与衬底电连接。位线彼此电绝缘。此外，每个位线由硬材料层覆盖在顶部。最后，在第二插头上形成节点接触。

2. 发明授权

US06423594B1 Method of fabricating deep trench capacitor 失效
标题翻译：制造深沟槽电容器的方法
公开(公告)号：US06423594B1
公开(公告)日：2002-07-23
申请号：US09754459
申请日：2001-01-04
申请人： Hong-Hsiang Tsai , Hsi-Chuan Chen
发明人： Hong-Hsiang Tsai , Hsi-Chuan Chen
IPC分类号： H01L218249
CPC分类号： H01L27/10867
摘要： A method of fabricating a trench capacitor includes forming a trench in a substrate; forming a conductive diffusion region in the substrate surrounding a lower portion of the trench; forming a dielectric layer along an inner surface of the trench; and filling the trench with a first doped polysilicon layer. A first recess is formed to expose an upper portion of the inner sidewall of the trench. A collar dielectric layer is formed on the exposed inner sidewall. The first recess is filled with a second doped polysilicon layer. A second recess is formed to expose a part of the upper portion of the inner sidewall. A gap is formed between the exposed inner sidewall and the second doped polysilicon layer, and filled with a doped polysilicon layer converted from an undoped polysilicon layer.
摘要翻译：制造沟槽电容器的方法包括在衬底中形成沟槽; 在包围沟槽下部的衬底中形成导电扩散区; 沿着所述沟槽的内表面形成电介质层; 以及用第一掺杂多晶硅层填充沟槽。形成第一凹部以暴露沟槽的内侧壁的上部。在暴露的内侧壁上形成轴环电介质层。第一凹部填充有第二掺杂多晶硅层。形成第二凹部以暴露内侧壁的上部的一部分。在暴露的内侧壁和第二掺杂多晶硅层之间形成间隙，并填充由未掺杂的多晶硅层转换的掺杂多晶硅层。

3. 发明授权

US5917748A Multi-level DRAM sensing scheme 失效
标题翻译：多级DRAM感知方案
公开(公告)号：US5917748A
公开(公告)日：1999-06-29
申请号：US045978
申请日：1998-03-17
申请人： Min-Hwa Chi , Hong-Hsiang Tsai
发明人： Min-Hwa Chi , Hong-Hsiang Tsai
IPC分类号： G11C11/56
CPC分类号： G11C11/565 , G11C7/06
摘要： A multilevel DRAM sensing structure to detect the level of charge and interpret the digital data from a DRAM cell is disclosed. The multi-level sense amplifier structure has a first and second bit line each having a first and second section. A pair of isolation switch transistors separate the first section of the first bit line from the second section of the first bit line. The first section of the second bit line is separated from the second section of the second bit line by a second pair of isolation switch transistors. A latching sense amplifier has a first input connected to one of the pairs of isolation switch transistors, a second input connected to the other pair of isolation switch transistors, and an output connected to external circuitry. The output will have the digital data represented by the charge in the DRAM cell. A cross coupling capacitor is connected between the first section of the first bit line and the second section of the second bit line to couple a charge shift between the first section of the first bit line and the second section of the second bit line to distinguish the low order bit of the digital data. A control logic section is connected to the DRAM cells to control selection of each one DRAM cell, to the latching sense amplifier to control activation of the sense amplifier, and to the isolation switch transistors to control activation and deactivation of the isolation switch transistors.
摘要翻译：公开了一种用于检测电荷电平并从DRAM单元解释数字数据的多电平DRAM感测结构。多电平读出放大器结构具有第一和第二位线，每个位线具有第一和第二部分。一对隔离开关晶体管将第一位线的第一部分与第一位线的第二部分分开。第二位线的第一部分通过第二对隔离开关晶体管与第二位线的第二部分分离。闩锁读出放大器具有连接到成对的隔离开关晶体管中的一个的第一输入端，连接到另一对隔离开关晶体管的第二输入端和连接到外部电路的输出端。输出将具有由DRAM单元中的电荷表示的数字数据。交叉耦合电容器连接在第一位线的第一部分和第二位线的第二部分之间，以耦合第一位线的第一部分和第二位线的第二部分之间的电荷位移，以区分第数字数据的低位位。控制逻辑部分连接到DRAM单元以控制每个DRAM单元的选择，锁存读出放大器的控制以控制读出放大器的激活，以及控制隔离开关晶体管来控制隔离开关晶体管的激活和去激活。

4. 发明授权

US5763306A Method of fabricating capacitor over bit line COB structure for a very high density DRAM applications 失效
标题翻译：在非常高密度DRAM应用中，通过位线COB结构制造电容器的方法
公开(公告)号：US5763306A
公开(公告)日：1998-06-09
申请号：US957675
申请日：1997-10-24
申请人： Hong-Hsiang Tsai
发明人： Hong-Hsiang Tsai
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L27/10852
摘要： A method of creating a deep pocket, capacitor over bit line structure, used for high density, DRAM designs, has been developed. The process consists of creating silicon nitride covered, polysilicon bit line structures, on an insulator layer, contacting an underlying source and drain region. A series of layers are next deposited, and patterned, to form the initial phase of a storage node contact hole, terminating at the surface of the silicon nitride covered polysilicon bit line structures. After formation of insulator spacers, protecting the silicon nitride covered, polysilicon bit line structures, the final phase of the storage node contact hole is formed, between polysilicon bit line structures, using RIE procedures. A storage node structure, featuring an HSG silicon layer, is formed on the inside surface of the storage node contact hole, followed by the creation of a capacitor dielectric layer, and an upper electrode structure, resulting in a deep pocket, capacitor over bit line structure.
摘要翻译：已经开发了一种用于高密度DRAM设计的深口袋电容器，位线结构电容器的方法。该工艺包括在绝缘体层上形成氮化硅覆盖的多晶硅位线结构，接触下面的源极和漏极区域。接下来沉积一系列层并图案化以形成存储节点接触孔的初始相，终止于氮化硅覆盖的多晶硅位线结构的表面。在形成绝缘体间隔物之后，使用RIE程序保护覆盖的氮化硅，多晶硅位线结构，存储节点接触孔的最终相，在多晶硅位线结构之间形成。在存储节点接触孔的内表面上形成具有HSG硅层的存储节点结构，随后形成电容器电介质层和上电极结构，从而形成深口袋，位线上的电容器结构体。

5. 发明申请

US20100283146A1 SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20100283146A1
公开(公告)日：2010-11-11
申请号：US12436266
申请日：2009-05-06
申请人： Ming-Chung Chian , Tsan-Yao Cheng , Li-Cheng Lin , Hong-Hsiang Tsai
发明人： Ming-Chung Chian , Tsan-Yao Cheng , Li-Cheng Lin , Hong-Hsiang Tsai
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L23/525 , H01L23/53223 , H01L24/02 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0231 , H01L2224/0239 , H01L2224/024 , H01L2224/0401 , H01L2224/11462 , H01L2224/13024 , H01L2224/13144 , H01L2224/16225 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01044 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01079 , H01L2924/01327 , H01L2924/15788 , H01L2924/3651 , H01L2924/01014 , H01L2924/04941 , H01L2924/01022 , H01L2924/00014 , H01L2924/0496 , H01L2924/0498 , H01L2924/0499 , H01L2924/0494 , H01L2924/04953 , H01L2924/00
摘要： A semiconductor structure including a substrate, an insulating layer, a composite pad structure, a passivation layer, and a bump is provided. A circuit structure is disposed on the substrate. The insulating layer covers the substrate and has a first opening exposing the circuit structure. The composite pad structure includes a first conductive layer, a barrier layer, and a second conductive layer which are sequentially disposed. The composite pad structure is disposed on the insulating layer and fills the first opening to electrically connect to the circuit structure. The passivation layer covers the composite pad structure and has a second opening exposing the composite pad structure. The bump fills the second opening and electrically connects to the composite pad structure.
摘要翻译：提供了包括衬底，绝缘层，复合衬垫结构，钝化层和凸块的半导体结构。电路结构设置在基板上。绝缘层覆盖基板并且具有暴露电路结构的第一开口。复合焊盘结构包括依次布置的第一导电层，阻挡层和第二导电层。复合焊盘结构设置在绝缘层上并填充第一开口以电连接到电路结构。钝化层覆盖复合焊盘结构，并具有露出复合焊盘结构的第二开口。凸块填充第二开口并电连接到复合垫结构。

6. 发明授权

US5691213A Low capacitance input/output integrated circuit 失效
标题翻译：低电容输入/输出集成电路
公开(公告)号：US5691213A
公开(公告)日：1997-11-25
申请号：US529002
申请日：1995-09-15
申请人： Ming-Chien Chang , Hong-Hsiang Tsai
发明人： Ming-Chien Chang , Hong-Hsiang Tsai
IPC分类号： H01L27/02 , H01L21/265
CPC分类号： H01L27/0266
摘要： A low capacitance input/output integrated circuit and a method by which the low capacitance input/output integrated circuit is formed. Formed upon a semiconductor substrate is an input/output integrated circuit which contains a minimum of one integrated circuit device. The integrated circuit device, in turn, possesses at minimum a source electrode and a drain electrode of the same polarity. Coincident with the source electrode and the drain electrode are normally at least one ion implant of polarity opposite to the source electrode and the drain electrode. At least a portion of the drain electrode is masked when the ion implant(s) of polarity opposite to the source electrode and the drain electrode are provided into the source electrode region and the drain electrode region of the integrated circuit device(s).
摘要翻译：低电容输入/输出集成电路和形成低电容输入/输出集成电路的方法。形成在半导体衬底上的是包含至少一个集成电路器件的输入/输出集成电路。集成电路器件又具有相同极性的源电极和漏极电极。与源电极和漏电极重合通常为与源电极和漏电极相反极性的至少一个离子注入。当与源电极和漏电极相反的极性的离子注入被提供到集成电路器件的源电极区域和漏电极区域中时，漏极电极的至少一部分被掩蔽。

7. 发明授权

US08072067B2 Semiconductor structure 有权
标题翻译：半导体结构
公开(公告)号：US08072067B2
公开(公告)日：2011-12-06
申请号：US12436266
申请日：2009-05-06
申请人： Ming-Chung Chian , Tsan-Yao Cheng , Li-Cheng Lin , Hong-Hsiang Tsai
发明人： Ming-Chung Chian , Tsan-Yao Cheng , Li-Cheng Lin , Hong-Hsiang Tsai
IPC分类号： H01L23/48
CPC分类号： H01L23/525 , H01L23/53223 , H01L24/02 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0231 , H01L2224/0239 , H01L2224/024 , H01L2224/0401 , H01L2224/11462 , H01L2224/13024 , H01L2224/13144 , H01L2224/16225 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01044 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01079 , H01L2924/01327 , H01L2924/15788 , H01L2924/3651 , H01L2924/01014 , H01L2924/04941 , H01L2924/01022 , H01L2924/00014 , H01L2924/0496 , H01L2924/0498 , H01L2924/0499 , H01L2924/0494 , H01L2924/04953 , H01L2924/00
摘要： A semiconductor structure including a substrate, an insulating layer, a composite pad structure, a passivation layer, and a bump is provided. A circuit structure is disposed on the substrate. The insulating layer covers the substrate and has a first opening exposing the circuit structure. The composite pad structure includes a first conductive layer, a barrier layer, and a second conductive layer which are sequentially disposed. The composite pad structure is disposed on the insulating layer and fills the first opening to electrically connect to the circuit structure. The passivation layer covers the composite pad structure and has a second opening exposing the composite pad structure. The bump fills the second opening and electrically connects to the composite pad structure.
摘要翻译：提供了包括衬底，绝缘层，复合衬垫结构，钝化层和凸块的半导体结构。电路结构设置在基板上。绝缘层覆盖基板并且具有暴露电路结构的第一开口。复合焊盘结构包括依次布置的第一导电层，阻挡层和第二导电层。复合焊盘结构设置在绝缘层上并填充第一开口以电连接到电路结构。钝化层覆盖复合焊盘结构，并具有露出复合焊盘结构的第二开口。凸块填充第二开口并电连接到复合垫结构。

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