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1. 发明申请

US20150096734A1 TEMPERATURE CONTROL DEVICE 审中-公开
标题翻译：温度控制装置
公开(公告)号：US20150096734A1
公开(公告)日：2015-04-09
申请号：US14486009
申请日：2014-09-15
申请人： MING-CHIEN CHANG
发明人： MING-CHIEN CHANG
IPC分类号： C12M1/00 , C12M1/36 , G01K13/00
CPC分类号： C12M41/14 , C12M41/48 , G05D23/1931
摘要： A temperature control device has a housing, a configuration unit, a microcontroller unit (MCU) and a temperature-sensing unit. After the configuration unit is used to configure a requested temperature and a temperature tolerance, the MCU adds a temperature outside the housing sensed an external temperature-sensing element of the temperature-sensing unit to the temperature tolerance, then determines if the sum is higher or lower than the requested temperature, starts a cooling unit or a heating unit to operate until a temperature inside the housing sensed by an internal temperature-sensing element of the temperature-sensing unit, thereby achieving an thermostatic effect.
摘要翻译：温度控制装置具有壳体，配置单元，微控制器单元（MCU）和温度感测单元。在配置单元用于配置请求的温度和温度容限之后，MCU将外部温度检测到温度感测单元的外部温度感测元件加到温度容差上，然后确定总和是高还是低于所要求的温度，启动冷却单元或加热单元以运行，直到由温度感测单元的内部温度感测元件感测到的壳体内的温度，从而实现恒温效果。

2. 发明授权

US5691213A Low capacitance input/output integrated circuit 失效
标题翻译：低电容输入/输出集成电路
公开(公告)号：US5691213A
公开(公告)日：1997-11-25
申请号：US529002
申请日：1995-09-15
申请人： Ming-Chien Chang , Hong-Hsiang Tsai
发明人： Ming-Chien Chang , Hong-Hsiang Tsai
IPC分类号： H01L27/02 , H01L21/265
CPC分类号： H01L27/0266
摘要： A low capacitance input/output integrated circuit and a method by which the low capacitance input/output integrated circuit is formed. Formed upon a semiconductor substrate is an input/output integrated circuit which contains a minimum of one integrated circuit device. The integrated circuit device, in turn, possesses at minimum a source electrode and a drain electrode of the same polarity. Coincident with the source electrode and the drain electrode are normally at least one ion implant of polarity opposite to the source electrode and the drain electrode. At least a portion of the drain electrode is masked when the ion implant(s) of polarity opposite to the source electrode and the drain electrode are provided into the source electrode region and the drain electrode region of the integrated circuit device(s).
摘要翻译：低电容输入/输出集成电路和形成低电容输入/输出集成电路的方法。形成在半导体衬底上的是包含至少一个集成电路器件的输入/输出集成电路。集成电路器件又具有相同极性的源电极和漏极电极。与源电极和漏电极重合通常为与源电极和漏电极相反极性的至少一个离子注入。当与源电极和漏电极相反的极性的离子注入被提供到集成电路器件的源电极区域和漏电极区域中时，漏极电极的至少一部分被掩蔽。

3. 发明授权

US6072218A Low capacitance input/output integrated circuit 失效
标题翻译：低电容输入/输出集成电路
公开(公告)号：US6072218A
公开(公告)日：2000-06-06
申请号：US912942
申请日：1997-08-18
申请人： Ming-Chien Chang , Hong-Hsiang Tsa
发明人： Ming-Chien Chang , Hong-Hsiang Tsa
IPC分类号： H01L27/02 , H01L23/62
CPC分类号： H01L27/0266
摘要： A low capacitance input/output integrated circuit and a method by which the low capacitance input/output integrated circuit is formed. Formed upon a semiconductor substrate is an input/output integrated circuit which contains a minimum of one integrated circuit device. The integrated circuit device, in turn, possesses at minimum a source elect rode and a drain electrode of the same polarity. Coincident with the source electrode and the drain electrode are normally at least one ion implant of polarity opposite to the source electrode and the drain electrode. At least a portion of the drain electrode is masked when the ion implant(s) of polarity opposite to the source electrode and the drain electrode are provided into the source electrode region and the drain electrode region of the integrated circuit device(s).
摘要翻译：低电容输入/输出集成电路和形成低电容输入/输出集成电路的方法。形成在半导体衬底上的是包含至少一个集成电路器件的输入/输出集成电路。集成电路器件又具有至少一个相同极性的源电极和漏电极。与源电极和漏电极重合通常为与源电极和漏电极相反极性的至少一个离子注入。当与源电极和漏电极相反的极性的离子注入被提供到集成电路器件的源电极区域和漏电极区域中时，漏极电极的至少一部分被掩蔽。

4. 发明授权

US5895959A Input port electrostatic discharge protection circuit for an intergrated circuit 失效
标题翻译：输入端口静电放电保护电路用于集成电路
公开(公告)号：US5895959A
公开(公告)日：1999-04-20
申请号：US770168
申请日：1996-12-19
申请人： Ming-Chien Chang
发明人： Ming-Chien Chang
IPC分类号： H01L27/02 , H01L29/423 , H01L23/60 , H01L29/78
CPC分类号： H01L27/0266 , H01L29/42364
摘要： An input port electrostatic discharge protection circuit is disposed between the input port of an integrated circuit and an input point of an internal circuit of the integrated circuit. The input port electrostatic discharge protection circuit includes a resistor and a field device. The ends of the resistor are connected to the input port of the integrate circuit and the input point of the internal circuit, respectively, and the function of the resistor is to delay ESD pulses for preventing the input port of the internal circuit from a strike directly. The field device has double gates disposed on field oxides. The source and drain of the field device are coupled to the input port of the integrated circuit and a low-voltage source, respectively. The first gate is coupled to the drain of the field device while the second grate is coupled to the source of the field device. The field device mainly provides an ESD path. An additional metal-oxide-semiconductor (MOS) device without a lightly doped drain (LDD) structure can be positioned between the input point of the internal circuit and the low-voltage source to thereby speed-up triggering of the field device to an "on" state. Moreover, an additional field device with the same double gates as the above-referred field device can also be disposed between a high-voltage source of the integrated circuit and the input port of the integrated circuit to enhance ESD protection.
摘要翻译：输入端口静电放电保护电路设置在集成电路的输入端口和集成电路的内部电路的输入点之间。输入端口静电放电保护电路包括电阻器和现场设备。电阻的两端分别连接到集成电路的输入端口和内部电路的输入端，电阻器的功能是延迟ESD脉冲，以防止内部电路的输入端口直接受到罢工。现场设备具有设置在场氧化物上的双门。现场设备的源极和漏极分别耦合到集成电路的输入端口和低电压源。第一栅极耦合到现场设备的漏极，而第二栅极耦合到现场设备的源。现场设备主要提供ESD路径。可以在内部电路的输入点和低电压源之间设置不具有轻掺杂漏极（LDD）结构的附加金属氧化物半导体（MOS）器件，从而将现场设备的触发加速到“ 关于“状态。此外，与集成电路的高电压源和集成电路的输入端口之间也可以设置具有与上述现场设备相同的双门的附加现场设备，以增强ESD保护。

5. 发明授权

US5736415A Method for manufacturing input/output port devices having low body effect 失效
标题翻译：用于制造具有低体效的输入/输出端口装置的方法
公开(公告)号：US5736415A
公开(公告)日：1998-04-07
申请号：US810075
申请日：1997-03-04
申请人： Ming-Chien Chang , Wuu-Larng Laih
发明人： Ming-Chien Chang , Wuu-Larng Laih
IPC分类号： H01L21/762 , H01L21/82 , H01L21/8238 , H01L21/265
CPC分类号： H01L21/82 , H01L21/762 , H01L21/823807
摘要： A method for manufacturing input/output port devices of a semiconductor circuit having low body effect, suitable for use on a semiconductor substrate on which a plurality of pull-up device regions and pull-down device regions are formed. First, when executing a channel implantation, an anti-punchthrough implantation, and a threshold adjustment implantation, a mask which masks PMOS devices in the CMOS process is used to mask pull-up device regions on a semiconductor substrate. Furthermore, when executing a cell implantation, a mask which masks the outside regions of memory cells is used to mask pull-down device regions. In the invention, the body effect of pull-up devices on the input/output port is reduced without using any extra mask and under the original process, thereby lowering the threshold voltage and reducing the output voltage drop.
摘要翻译：一种用于制造具有低体效应的半导体电路的输入/输出端口装置的方法，适用于形成有多个上拉器件区域和下拉器件区域的半导体衬底上。首先，当执行信道注入，抗穿透注入和阈值调整注入时，使用掩蔽CMOS工艺中的PMOS器件的掩模来掩蔽半导体衬底上的上拉器件区域。此外，当执行细胞注入时，使用掩蔽存储单元的外部区域的掩模来屏蔽下拉器件区域。在本发明中，上拉器件在输入/输出端口上的体效降低，而不需要任何额外的掩模，并且在原始工艺下，从而降低阈值电压并降低输出电压降。

6. 发明授权

US5963409A Input/output electrostatic discharge protection circuit for an integrated circuit (IC) 失效
标题翻译：用于集成电路（IC）的输入/输出静电放电保护电路
公开(公告)号：US5963409A
公开(公告)日：1999-10-05
申请号：US770568
申请日：1996-12-19
申请人： Ming-Chien Chang
发明人： Ming-Chien Chang
IPC分类号： H01L27/02 , H02H3/22
CPC分类号： H01L29/7835 , H01L27/0248 , H01L27/0266 , H01L29/0847 , H01L2924/0002
摘要： An input/output electrostatic discharge (ESD) protection circuit for an integrated circuit disposed between an input/output port and the internal circuitry, including an input path protection device and an output path protection device. The output path protection device includes a pair of pull-up and pull-down transistors, two resistors, and a first and a second MOS field effect transistors respectively connected in parallel with the pull-up and the pull-down transistors. The resistors are formed in lightly-doped regions of the source or drain of the pull-up and pull down transistors, respectively, so the series resistance can be reduced efficiently, the driving ability can be prevented from decreasing and the devices can obtain uniform breakdown under intensive layout circumstances. The first and the second MOS field effect transistors are utilized to protect against both positive electrostatic stress and negative electrostatic stress to improve overall ESD protection.
摘要翻译：一种设置在输入/输出端口和内部电路之间的集成电路的输入/输出静电放电（ESD）保护电路，包括输入路径保护装置和输出路径保护装置。输出路径保护装置包括分别与上拉和下拉晶体管并联连接的一对上拉和下拉晶体管，两个电阻器以及第一和第二MOS场效应晶体管。电阻分别形成在上拉和下拉晶体管的源极或漏极的轻掺杂区域中，从而可以有效降低串联电阻，可以防止驱动能力的降低，器件可以获得均匀的击穿在密集布局的情况下。第一和第二MOS场效应晶体管用于保护正静电应力和负静电应力以改善整体ESD保护。

7. 发明授权

US5663678A ESD protection device 失效
标题翻译： ESD保护装置
公开(公告)号：US5663678A
公开(公告)日：1997-09-02
申请号：US595701
申请日：1996-02-02
申请人： Ming-Chien Chang
发明人： Ming-Chien Chang
IPC分类号： H01L27/02 , H02H3/20 , H02H9/04
CPC分类号： H01L27/0266 , H01L27/0259
摘要： An FET with a lightly doped drain is connected between an input/output pad and ground and is protected from ESD at a pad by a structure that includes a resistor formed by the process step for the lightly doped drain. The resistor adjoins and interconnects a diffusion underlying the pad and the diffusion for the drain of the FET. A parasitic bipolar transistor is formed by the pad diffusion, the source diffusion for the FET, and the intervening substrate. When an ESD voltage appears at the pad, the FET conducts in circuit with the resistor and the voltage drop across the resistor helps to protect the FET and to turn on this parasitic bipolar transistor (in preference to a parasitic bipolar transistor otherwise formed by the FET) and thereby hold down the ESD voltage at the pad and at the drain of the FET. The FET and resistor can be formed as a number of parallel connected FETs and resistors located symmetrically on opposite sides of the pad diffusion. Protection for an input inverter circuit is also provided.
摘要翻译：具有轻掺杂漏极的FET连接在输入/输出焊盘和地之间，并通过包括由用于轻掺杂漏极的工艺步骤形成的电阻器的结构在焊盘处被ESD保护。电阻器连接并互连焊盘下方的扩散层和FET的漏极扩散。通过焊盘扩散，FET的源极扩散和中间衬底形成寄生双极晶体管。当焊盘出现ESD电压时，FET与电阻器导通，并且电阻两端的电压降有助于保护FET并导通该寄生双极晶体管（优于另外由FET形成的寄生双极晶体管）），从而压紧焊盘和FET的漏极处的ESD电压。 FET和电阻器可以形成为对称地位于焊盘扩散的相对侧上的多个并联的FET和电阻器。还提供了对输入逆变器电路的保护。

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