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1. 发明申请

US20080138983A1 Method of forming tensile stress films for NFET performance enhancement 审中-公开
标题翻译：形成用于NFET性能提高的拉伸应力膜的方法
公开(公告)号：US20080138983A1
公开(公告)日：2008-06-12
申请号：US11634303
申请日：2006-12-06
申请人： Hao-Ming Lien , Jim Cy Huang , Donald Y. Chao , Ling-Yen Yeh , Hun-Jan Tao
发明人： Hao-Ming Lien , Jim Cy Huang , Donald Y. Chao , Ling-Yen Yeh , Hun-Jan Tao
IPC分类号： H01L21/44
CPC分类号： H01L21/76832 , H01L21/2686 , H01L21/76825 , H01L21/76828 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method of forming tensile stress films for NFET Performance enhancement, comprising the steps of: (a) providing a semiconductor substrate having a gate structure patterned thereon; (b) performing a deposition process to form a first dielectric film overlying the semiconductor substrate and covering the gate structure; (c) performing a curing process on the first dielectric film; (d) successively repeating the step (b) of deposition process and the step (c) of curing process at least once to form at least one second dielectric film on the first dielectric film until the total thickness of the first dielectric film and the at least one second dielectric film reaches a target thickness.
摘要翻译：一种形成用于NFET性能增强的拉伸应力膜的方法，包括以下步骤：（a）提供在其上图案化的栅极结构的半导体衬底; （b）进行沉积工艺以形成覆盖半导体衬底并覆盖栅极结构的第一电介质膜; （c）对所述第一电介质膜进行固化处理; （d）连续重复沉积处理步骤（b）和固化过程的步骤（c）至少一次，以在第一介电膜上形成至少一个第二电介质膜，直到第一介电膜和第至少一个第二介电膜达到目标厚度。

2. 发明申请

US20070148881A1 Hybrid STI stressor with selective re-oxidation anneal 有权
公开(公告)号：US20070148881A1
公开(公告)日：2007-06-28
申请号：US11320221
申请日：2005-12-28
申请人： Kai-Ting Tseng , Yu-Lien Huang , Hao-Ming Lien , Ling-Yen Yeh , Hun-Jan Tao
发明人： Kai-Ting Tseng , Yu-Lien Huang , Hao-Ming Lien , Ling-Yen Yeh , Hun-Jan Tao
IPC分类号： H01L21/336
CPC分类号： H01L21/823878 , H01L21/76224 , H01L21/823807 , H01L29/7846
摘要： A method for forming stressors in a semiconductor substrate is provided. The method includes providing a semiconductor substrate including a first device region and a second device region, forming shallow trench isolation (STI) regions with a high-shrinkage dielectric material in the first and the second device regions wherein the STI regions define a first active region in the first device region and a second active region in the second device region, forming an insulation mask over the STI region and the first active region in the first device region wherein the insulation mask does not extend over the second device region, and performing a stress-tuning treatment to the semiconductor substrate. The first active region and second active region have tensile stress and compressive stress respectively. An NMOS and a PMOS device are formed on the first and second active regions, respectively.

3. 发明授权

US07276417B2 Hybrid STI stressor with selective re-oxidation anneal 有权
标题翻译：混合STI应力选择性再氧化退火
公开(公告)号：US07276417B2
公开(公告)日：2007-10-02
申请号：US11320221
申请日：2005-12-28
申请人： Kai-Ting Tseng , Yu-Lien Huang , Hao-Ming Lien , Ling-Yen Yeh , Hun-Jan Tao
发明人： Kai-Ting Tseng , Yu-Lien Huang , Hao-Ming Lien , Ling-Yen Yeh , Hun-Jan Tao
IPC分类号： H01L21/336
CPC分类号： H01L21/823878 , H01L21/76224 , H01L21/823807 , H01L29/7846
摘要： A method for forming stressors in a semiconductor substrate is provided. The method includes providing a semiconductor substrate including a first device region and a second device region, forming shallow trench isolation (STI) regions with a high-shrinkage dielectric material in the first and the second device regions wherein the STI regions define a first active region in the first device region and a second active region in the second device region, forming an insulation mask over the STI region and the first active region in the first device region wherein the insulation mask does not extend over the second device region, and performing a stress-tuning treatment to the semiconductor substrate. The first active region and second active region have tensile stress and compressive stress respectively. An NMOS and a PMOS device are formed on the first and second active regions, respectively.
摘要翻译：提供了一种在半导体衬底中形成应力源的方法。该方法包括提供包括第一器件区域和第二器件区域的半导体衬底，在第一和第二器件区域中形成具有高收缩介电材料的浅沟槽隔离（STI）区域，其中STI区域限定第一有源区域在所述第一器件区域和所述第二器件区域中的第二有源区域中，在所述STI区域和所述第一器件区域中的所述第一有源区域上形成绝缘掩模，其中所述绝缘掩模不在所述第二器件区域上延伸，并执行对半导体衬底进行应力调谐处理。第一活性区和第二活性区分别具有拉伸应力和压应力。分别在第一和第二有源区上形成NMOS和PMOS器件。

4. 发明申请

US20080308899A1 TRIANGULAR SPACE ELEMENT FOR SEMICONDUCTOR DEVICE 有权
标题翻译：用于半导体器件的三角形空间元件
公开(公告)号：US20080308899A1
公开(公告)日：2008-12-18
申请号：US11763566
申请日：2007-06-15
申请人： Yu-Lien Huang , Yi-Chen Huang , Jim Cy Huang , Weng Chang , Hun-Jan Tao
发明人： Yu-Lien Huang , Yi-Chen Huang , Jim Cy Huang , Weng Chang , Hun-Jan Tao
IPC分类号： H01L29/06 , H01L29/00
CPC分类号： H01L21/823425 , H01L21/823468 , Y10S438/981
摘要： Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first gate and the first spacer. The thickness of the CESL to the width of the first spacer is between approximately 0.625 and 16.
摘要翻译：提供了包括基板的半导体器件。形成在基板上的栅极。门包括侧壁。在衬底上形成并且邻近门的侧壁的间隔物。间隔件具有基本上三角形的几何形状。在第一栅极和第一间隔物上形成接触蚀刻停止层（CESL）。 CESL的厚度与第一间隔件的宽度在大约0.625和16之间。

5. 发明授权

US07834389B2 Triangular space element for semiconductor device 有权
标题翻译：半导体器件三角形空间元件
公开(公告)号：US07834389B2
公开(公告)日：2010-11-16
申请号：US11763566
申请日：2007-06-15
申请人： Yu-Lien Huang , Yi-Chen Huang , Jim Cy Huang , Weng Chang , Hun-Jan Tao
发明人： Yu-Lien Huang , Yi-Chen Huang , Jim Cy Huang , Weng Chang , Hun-Jan Tao
IPC分类号： H01L29/788
CPC分类号： H01L21/823425 , H01L21/823468 , Y10S438/981
摘要： Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first gate and the first spacer. The thickness of the CESL to the width of the first spacer is between approximately 0.625 and 16.
摘要翻译：提供了包括基板的半导体器件。形成在基板上的栅极。门包括侧壁。在衬底上形成并且邻近门的侧壁的间隔物。间隔件具有基本上三角形的几何形状。在第一栅极和第一间隔物上形成接触蚀刻停止层（CESL）。 CESL的厚度与第一间隔件的宽度在大约0.625和16之间。

6. 发明授权

US07579248B2 Resolving pattern-loading issues of SiGe stressor 有权
标题翻译：解决SiGe应激源的模式加载问题
公开(公告)号：US07579248B2
公开(公告)日：2009-08-25
申请号：US11352588
申请日：2006-02-13
申请人： Yu-Lien Huang , Jim Huang , Ling-Yen Yeh , Hun-Jan Tao
发明人： Yu-Lien Huang , Jim Huang , Ling-Yen Yeh , Hun-Jan Tao
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636
摘要： A method for improving uniformity of stressors of MOS devices is provided. The method includes forming a gate dielectric over a semiconductor substrate, forming a gate electrode on the gate dielectric, forming a spacer on respective sidewalls of the gate electrode and the gate dielectric, forming a recess in the semiconductor adjacent the spacer, and depositing SiGe in the recess to form a SiGe stressor. The method further includes etching the SiGe stressor to improve the uniformity of SiGe stressors.
摘要翻译：提供了一种改善MOS器件的应力源均匀性的方法。该方法包括在半导体衬底上形成栅极电介质，在栅极电介质上形成栅电极，在栅电极和栅极电介质的相应侧壁上形成间隔物，在邻近间隔物的半导体中形成凹陷，并将SiGe沉积在凹陷形成SiGe应激源。该方法还包括蚀刻SiGe应力器以改善SiGe应力的均匀性。

7. 发明申请

US20070190730A1 Resolving pattern-loading issues of SiGe stressor 有权
标题翻译：解决SiGe应激源的模式加载问题
公开(公告)号：US20070190730A1
公开(公告)日：2007-08-16
申请号：US11352588
申请日：2006-02-13
申请人： Yu-Lien Huang , Jim Huang , Ling-Yen Yeh , Hun-Jan Tao
发明人： Yu-Lien Huang , Jim Huang , Ling-Yen Yeh , Hun-Jan Tao
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636
摘要： A method for improving uniformity of stressors of MOS devices is provided. The method includes forming a gate dielectric over a semiconductor substrate, forming a gate electrode on the gate dielectric, forming a spacer on respective sidewalls of the gate electrode and the gate dielectric, forming a recess in the semiconductor adjacent the spacer, and depositing SiGe in the recess to form a SiGe stressor. The method further includes etching the SiGe stressor to improve the uniformity of SiGe stressors.
摘要翻译：提供了一种改善MOS器件的应力源均匀性的方法。该方法包括在半导体衬底上形成栅极电介质，在栅极电介质上形成栅电极，在栅电极和栅极电介质的相应侧壁上形成间隔物，在邻近间隔物的半导体中形成凹陷，并将SiGe沉积在凹陷形成SiGe应激源。该方法还包括蚀刻SiGe应力器以改善SiGe应力的均匀性。

8. 发明申请

US20070013070A1 Semiconductor devices and methods of manufacture thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070013070A1
公开(公告)日：2007-01-18
申请号：US11159709
申请日：2005-06-23
申请人： Mong Liang , Hun-Jan Tao , Jim Huang , Ling-Yen Yeh , Yu-Lien Huang
发明人： Mong Liang , Hun-Jan Tao , Jim Huang , Ling-Yen Yeh , Yu-Lien Huang
IPC分类号： H01L23/52
CPC分类号： H01L21/02123 , H01L21/3185 , H01L27/10894 , H01L27/11
摘要： Novel etch stop layers for semiconductor devices and methods of forming thereof are disclosed. In one embodiment, an etch stop layer comprises tensile or compressive stress. In another embodiments, etch stop layers are formed having a first thickness in a first region of a workpiece and at least one second thickness in a second region of a workpiece, wherein the at least one second thickness is different than the first thickness. The etch stop layer may be thicker over top surfaces than over sidewall surfaces. The etch stop layer may be thicker over widely-spaced feature regions and thinner over closely-spaced feature regions.
摘要翻译：公开了用于半导体器件的新型蚀刻停止层及其形成方法。在一个实施例中，蚀刻停止层包括拉伸或压缩应力。在另一个实施例中，在工件的第一区域中形成具有第一厚度并且在工件的第二区域中具有至少一个第二厚度的蚀刻停止层，其中至少一个第二厚度不同于第一厚度。蚀刻停止层可以在顶表面上比在侧壁表面上更厚。蚀刻停止层可以在宽间隔的特征区域上更厚，并且在紧密间隔的特征区域上更薄。

9. 发明授权

US08367563B2 Methods for a gate replacement process 有权
标题翻译：门更换过程的方法
公开(公告)号：US08367563B2
公开(公告)日：2013-02-05
申请号：US12575280
申请日：2009-10-07
申请人： Matt Yeh , Hui Ouyang , Da-Yuan Lee , Kuang Yuan Hsu , Hun-Jan Tao , Xiong-Fei Yu
发明人： Matt Yeh , Hui Ouyang , Da-Yuan Lee , Kuang Yuan Hsu , Hun-Jan Tao , Xiong-Fei Yu
IPC分类号： H01L21/3205
CPC分类号： H01L29/401 , H01L21/823828 , H01L21/823835 , H01L21/823842 , H01L29/66545
摘要： A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process.
摘要翻译：公开了一种制造半导体器件的方法。在一个实施例中，该方法可以包括提供衬底; 在所述衬底上形成包括第一虚拟栅极的栅极结构; 从栅极结构去除第一伪栅极以形成沟槽; 形成界面层，高k电介质层和覆盖层以部分地填充在沟槽中; 在所述覆盖层上形成第二虚拟栅极，其中所述第二伪栅极填充所述沟槽; 并用金属栅极替换第二虚拟栅极。在一个实施例中，该方法可以包括提供衬底; 在衬底上形成界面层; 在界面层上形成高k电介质层; 在所述高k电介质层上形成蚀刻停止层; 在所述蚀刻停止层上形成包括低热预算硅的覆盖层; 在覆盖层上形成虚拟栅极层; 形成栅极结构; 并进行门更换处理。

10. 发明授权

US08299508B2 CMOS structure with multiple spacers 有权
标题翻译：具有多个间隔物的CMOS结构
公开(公告)号：US08299508B2
公开(公告)日：2012-10-30
申请号：US12757517
申请日：2010-04-09
申请人： Bor Chiuan Hsieh , Han-Ping Chung , Chih-Hsin Ko , Bor-Wen Chan , Hun-Jan Tao
发明人： Bor Chiuan Hsieh , Han-Ping Chung , Chih-Hsin Ko , Bor-Wen Chan , Hun-Jan Tao
IPC分类号： H01L29/78 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes a substrate having shallow trench isolation and source/drain regions located therein, a gate stack located on the substrate between the source/drain regions, a first gate spacer on the sidewall of the gate stack, and a second gate spacer on the sidewall of the first gate spacer.
摘要翻译：半导体器件包括具有浅沟槽隔离和位于其中的源极/漏极区的衬底，位于源极/漏极区之间的衬底上的栅极堆叠，栅极堆叠的侧壁上的第一栅极间隔物和位于栅极堆叠的侧壁上的第二栅极间隔第一栅极间隔物的侧壁。

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