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1. 发明申请

US20100090264A1 INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件的互连结构
公开(公告)号：US20100090264A1
公开(公告)日：2010-04-15
申请号：US12249060
申请日：2008-10-10
申请人： Hans-Peter Moll , Gouri Sankar Kar , Martin Popp , Lars Heineck , Peter Lahnor , Arnd Scholz , Stefan Jakschik , Wolfgang Roesner , Gerhard Enders , Werner Graf , Peter Baars , Klaus Muemmler , Bernd Hintze , Andrei Josiek
发明人： Hans-Peter Moll , Gouri Sankar Kar , Martin Popp , Lars Heineck , Peter Lahnor , Arnd Scholz , Stefan Jakschik , Wolfgang Roesner , Gerhard Enders , Werner Graf , Peter Baars , Klaus Muemmler , Bernd Hintze , Andrei Josiek
IPC分类号： H01L27/108 , H01L21/02
CPC分类号： H01L27/10891 , H01L27/10823 , H01L27/10876 , H01L27/10885
摘要： One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.
摘要翻译：一个实施例涉及形成在半导体主体上的集成电路，其具有在第一和第二晶体管的源/漏区之间的互连。互连件包括布置在半导体本体表面下方的金属体。接触元件建立金属体与第一和第二晶体管的源/漏区之间的电接触。接触元件沿着第一和第二晶体管的源极/漏极区域之间的连接路径延伸。还公开了其它方法，装置和系统。

2. 发明授权

US08138538B2 Interconnect structure for semiconductor devices 有权
标题翻译：半导体器件的互连结构
公开(公告)号：US08138538B2
公开(公告)日：2012-03-20
申请号：US12249060
申请日：2008-10-10
申请人： Hans-Peter Moll , Gouri Sankar Kar , Martin Popp , Lars Heineck , Peter Lahnor , Arnd Scholz , Stefan Jakschik , Wolfgang Roesner , Gerhard Enders , Werner Graf , Peter Baars , Klaus Muemmler , Bernd Hintze , Andrei Josiek
发明人： Hans-Peter Moll , Gouri Sankar Kar , Martin Popp , Lars Heineck , Peter Lahnor , Arnd Scholz , Stefan Jakschik , Wolfgang Roesner , Gerhard Enders , Werner Graf , Peter Baars , Klaus Muemmler , Bernd Hintze , Andrei Josiek
IPC分类号： H01L27/108
CPC分类号： H01L27/10891 , H01L27/10823 , H01L27/10876 , H01L27/10885
摘要： One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.
摘要翻译：一个实施例涉及形成在半导体主体上的集成电路，其具有在第一和第二晶体管的源/漏区之间的互连。互连件包括布置在半导体本体表面下方的金属体。接触元件建立金属体与第一和第二晶体管的源/漏区之间的电接触。接触元件沿着第一和第二晶体管的源极/漏极区域之间的连接路径延伸。还公开了其它方法，装置和系统。

3. 发明申请

US20070040202A1 Semiconductor memory cell array having self-aligned recessed gate MOS transistors and method for forming the same 审中-公开
标题翻译：具有自对准凹栅MOS晶体管的半导体存储单元阵列及其形成方法
公开(公告)号：US20070040202A1
公开(公告)日：2007-02-22
申请号：US11206306
申请日：2005-08-18
申请人： Gerhard Enders , Marc Strasser , Peter Voigt , Bjorn Fischer
发明人： Gerhard Enders , Marc Strasser , Peter Voigt , Bjorn Fischer
IPC分类号： H01L29/94 , H01L21/8242
CPC分类号： H01L27/10876 , H01L27/10861
摘要： In a semiconductor memory including an array of memory cells, each memory cell includes a trench capacitor, the trench capacitor including an inner electrode, an outer electrode and a dielectric layer disposed between the inner electrode and the outer electrode, and a selection transistor, the selection transistor including a first source/drain area, a second source/drain area and a channel region disposed between the first source/drain area and the second source/drain area in a recess, the trench capacitor and the selection transistor of each memory cell are disposed side by side, the first source/drain area of the selection transistor being electrically connected to the inner electrode of the trench capacitor, the recess in which the channel region of the selection transistor is formed being located self aligned between the trench capacitor of the memory cell and the trench capacitor of an adjacent memory cell.
摘要翻译：在包括存储单元阵列的半导体存储器中，每个存储单元包括沟槽电容器，所述沟槽电容器包括内电极，外电极和设置在内电极和外电极之间的电介质层，以及选择晶体管，选择晶体管，其包括第一源极/漏极区域，第二源极/漏极区域和设置在凹部中的第一源极/漏极区域和第二源极/漏极区域之间的沟道区域，每个存储器单元的沟槽电容器和选择晶体管并排配置，选择晶体管的第一源极/漏极区域电连接到沟槽电容器的内部电极，形成选择晶体管的沟道区域的凹槽位于沟槽电容器的沟槽电容器之间，存储单元和相邻存储单元的沟槽电容器。

4. 发明授权

US07081392B2 Method for fabricating a gate structure of a FET and gate structure of a FET 失效
标题翻译：用于制造FET的栅极结构和FET的栅极结构的方法
公开(公告)号：US07081392B2
公开(公告)日：2006-07-25
申请号：US10897403
申请日：2004-07-23
申请人： Gerhard Enders , Peter Voigt
发明人： Gerhard Enders , Peter Voigt
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/4966 , H01L29/66492 , H01L29/6653 , H01L29/66545 , H01L29/7833
摘要： A method for fabricating a gate structure of a FET, having: (a) deposition and patterning of a sacrificial layer sequence on a semiconductor substrate and uncovering of a gate section; (b) implantation of a channel doping into the gate section; (c) deposition and patterning of spacers at the sidewalls of the sacrificial layer sequence with the formation of a gate section that is not covered by the spacers; (d) introduction of a mask material into the gate section that is not covered by the spacers; (e) removal of the spacers selectively with respect to the sacrificial layer sequence and mask material); (f) implantation of a halo doping in regions uncovered by the removed spacers; (g) removal of the mask material; (h) formation of a gate on the gate section; and (j) removal of the sacrificial layer sequence selectively with respect to the gate.
摘要翻译：一种用于制造FET的栅极结构的方法，具有：（a）在半导体衬底上沉积和图案化牺牲层序列并露出栅极部分; （b）将沟道掺杂注入到栅极部分中; （c）在牺牲层序列的侧壁处沉积和图案化间隔物，形成未被间隔物覆盖的栅极部分; （d）将掩模材料引入未被间隔物覆盖的栅极部分; （e）相对于牺牲层序列和掩模材料选择性去除间隔物）; （f）在被去除的间隔物覆盖的区域内注入晕圈; （g）去除掩模材料; （h）在栅极部分上形成栅极; 和（j）相对于栅极选择性地去除牺牲层序列。

5. 发明授权

US07009263B2 Field-effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US07009263B2
公开(公告)日：2006-03-07
申请号：US10830675
申请日：2004-04-23
申请人： Gerhard Enders , Bjoern Fischer , Helmut Schneider , Peter Voigt
发明人： Gerhard Enders , Bjoern Fischer , Helmut Schneider , Peter Voigt
IPC分类号： H01L29/76
CPC分类号： H01L29/0649 , H01L29/1033
摘要： A field-effect transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a channel region formed in the semiconductor substrate, wherein the source region is connected to a source terminal electrode and the drain region is connected to a drain terminal electrode, wherein the channel region comprises a first narrow width channel region and a second narrow width channel region connected in parallel regarding the source terminal electrode and the drain terminal electrode, and wherein the first narrow width channel region and/or the second narrow width channel region comprise lateral edges narrowing the width of the narrow width channel region is such a way that a channel formation in the narrow width channel region is influenced by a mutually influencing effect of the lateral edges, and a gate electrode arranged above the first and second narrow width channel regions.
摘要翻译：场效应晶体管包括半导体衬底，形成在半导体衬底中的源极区域，形成在半导体衬底中的漏极区域，形成在半导体衬底中的沟道区域，其中源极区域连接到源极端子电极，漏极区域连接到漏极端子电极，其中沟道区域包括关于源极端子电极和漏极端子电极并联连接的第一窄宽度沟道区域和第二窄度沟道区域，并且其中第一窄宽度沟道区域和/或第二窄宽度沟道区域包括使窄宽度沟道区域的宽度变窄的横向边缘，使得窄宽度沟道区域中的沟道形成受到横向边缘的相互影响的影响，电极，布置在第一和第二窄宽度通道区域的上方。

6. 发明授权

US06503784B1 Double gated transistor 有权
标题翻译：双门控晶体管
公开(公告)号：US06503784B1
公开(公告)日：2003-01-07
申请号：US09670742
申请日：2000-09-27
申请人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
发明人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
IPC分类号： H01L218238
CPC分类号： H01L27/11 , H01L21/823885 , H01L27/092 , H01L27/1104 , H01L27/1203
摘要： A semiconductor body-having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.
摘要翻译：一种具有一对垂直双门控CMOS晶体管的半导体体。在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。每个单元都有一个VDD CONTACT和一个VSS CONTACT。这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

7. 发明授权

US06472767B1 Static random access memory (SRAM) 有权
标题翻译：静态随机存取存储器（SRAM）
公开(公告)号：US06472767B1
公开(公告)日：2002-10-29
申请号：US09302757
申请日：1999-04-30
申请人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
发明人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
IPC分类号： H01L2711
CPC分类号： H01L27/11 , H01L27/1104
摘要： A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.
摘要翻译：具有一对垂直双门控CMOS晶体管的半导体本体。在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。每个单元都有一个VDD CONTACT和一个VSS CONTACT。这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

8. 发明授权

US09159400B2 Semiconductor memory having staggered sense amplifiers associated with a local column decoder 有权
标题翻译：具有与本地列解码器相关联的交错读出放大器的半导体存储器
公开(公告)号：US09159400B2
公开(公告)日：2015-10-13
申请号：US13422697
申请日：2012-03-16
申请人： Richard Ferrant , Gerhard Enders , Carlos Mazure
发明人： Richard Ferrant , Gerhard Enders , Carlos Mazure
IPC分类号： G11C7/06 , G11C11/4091 , G11C11/4097
CPC分类号： G11C11/4091 , G11C7/065 , G11C11/4097
摘要： A semiconductor memory having bit lines and wordlines crossing each other, a memory cell array formed by memory cells arranged in rows and columns on crossover points of the bit lines and wordlines, and sense amplifier banks arranged on opposite sides of the memory cell array. Each sense amplifier bank has staggered sense amplifiers connected to a bit line according to an interleaved arrangement whereby bit lines alternate in the direction of the wordlines between bit lines coupled to different sense amplifiers. This results in interconnect spaces parallel to the bit lines. Also, each sense amplifier bank includes a local column decoder for selecting a sense amplifier and which is staggered with the sense amplifiers and coupled to the sense amplifier by an output line running in an available interconnect space parallel to the bit lines.
摘要翻译：具有彼此交叉的位线和字线的半导体存储器，由位线和字线的交叉点上以列和列排列的存储单元形成的存储单元阵列以及布置在存储单元阵列的相对侧上的读出放大器组。每个读出放大器组具有根据交错布置连接到位线的交错读出放大器，由此位线在耦合到不同读出放大器的位线之间的字线方向上交替。这导致互连空间与位线平行。此外，每个读出放大器组包括本地列解码器，用于选择读出放大器，并与读出放大器交错，并通过在平行于位线的可用互连空间中运行的输出线耦合到读出放大器。

9. 发明授权

US07372093B2 DRAM memory with vertically arranged selection transistors 失效
标题翻译：具有垂直排列的选择晶体管的DRAM存储器
公开(公告)号：US07372093B2
公开(公告)日：2008-05-13
申请号：US10744056
申请日：2003-12-23
申请人： Michael Sommer , Gerhard Enders
发明人： Michael Sommer , Gerhard Enders
IPC分类号： H01L27/108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10891 , H01L29/66181
摘要： The invention relates to a semiconductor memory, particularly a DRAM, in which the memory cells in each case have a trench capacitor arranged in a lower area of a trench hole and a vertical selection transistor which is formed adjoining an upper area of the trench hole and which connects an inner electrode of the trench capacitor to a bit line, a conductive channel being capable of being formed in dependence on the potential of a word line in the channel area, the channel area completely enclosing the trench hole in its upper area, and the associated word line at least partially enclosing the channel area.
摘要翻译：本发明涉及一种半导体存储器，特别是DRAM，其中存储单元在每种情况下具有布置在沟槽孔的下部区域中的沟槽电容器和垂直选择晶体管，该垂直选择晶体管形成为邻接沟槽孔的上部区域;以及其将沟槽电容器的内部电极与位线连接，能够根据沟道区域中的字线的电位形成导电沟道，完全包围其上部区域中的沟槽的沟道区域，以及相关联的字线至少部分地包围通道区域。

10. 发明授权

US06979853B2 DRAM memory cell and memory cell array with fast read/write access 失效
标题翻译： DRAM存储单元和具有快速读/写访问的存储单元阵列
公开(公告)号：US06979853B2
公开(公告)日：2005-12-27
申请号：US10462533
申请日：2003-06-16
申请人： Michael Sommer , Gerhard Enders
发明人： Michael Sommer , Gerhard Enders
IPC分类号： G11C7/00 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10876 , H01L27/10864 , H01L27/10867 , H01L27/10891
摘要： The memory cell according to the invention has a vertical selection transistor, via whose channel region the inner electrode of the trench capacitor can be connected to a bit line. The large extent of the channel region in the bit line direction means that the trench capacitor can be rapidly charged and read. The channel region is led to the bit line through an associated word line, which completely or partially encloses the channel region. A conductive channel can be formed within the channel region depending on the potential of the word line.
摘要翻译：根据本发明的存储单元具有垂直选择晶体管，其通道区域可以将沟槽电容器的内部电极连接到位线。位线方向上的沟道区域的大范围意味着沟槽电容器可以被快速充电和读取。通道区域通过相关联的字线被引导到位线，该字线完全或部分地包围通道区域。取决于字线的电位，可以在通道区域内形成导电沟道。

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