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1. 发明授权

US07009263B2 Field-effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US07009263B2
公开(公告)日：2006-03-07
申请号：US10830675
申请日：2004-04-23
申请人： Gerhard Enders , Bjoern Fischer , Helmut Schneider , Peter Voigt
发明人： Gerhard Enders , Bjoern Fischer , Helmut Schneider , Peter Voigt
IPC分类号： H01L29/76
CPC分类号： H01L29/0649 , H01L29/1033
摘要： A field-effect transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a channel region formed in the semiconductor substrate, wherein the source region is connected to a source terminal electrode and the drain region is connected to a drain terminal electrode, wherein the channel region comprises a first narrow width channel region and a second narrow width channel region connected in parallel regarding the source terminal electrode and the drain terminal electrode, and wherein the first narrow width channel region and/or the second narrow width channel region comprise lateral edges narrowing the width of the narrow width channel region is such a way that a channel formation in the narrow width channel region is influenced by a mutually influencing effect of the lateral edges, and a gate electrode arranged above the first and second narrow width channel regions.
摘要翻译：场效应晶体管包括半导体衬底，形成在半导体衬底中的源极区域，形成在半导体衬底中的漏极区域，形成在半导体衬底中的沟道区域，其中源极区域连接到源极端子电极，漏极区域连接到漏极端子电极，其中沟道区域包括关于源极端子电极和漏极端子电极并联连接的第一窄宽度沟道区域和第二窄度沟道区域，并且其中第一窄宽度沟道区域和/或第二窄宽度沟道区域包括使窄宽度沟道区域的宽度变窄的横向边缘，使得窄宽度沟道区域中的沟道形成受到横向边缘的相互影响的影响，电极，布置在第一和第二窄宽度通道区域的上方。

2. 发明授权

US06797562B2 Method for manufacturing a buried strap contact in a memory cell 失效
公开(公告)号：US06797562B2
公开(公告)日：2004-09-28
申请号：US10607033
申请日：2003-06-26
申请人： Dietrich Bonart , Gerhard Enders , Bjoern Fischer , Peter Voigt
发明人： Dietrich Bonart , Gerhard Enders , Bjoern Fischer , Peter Voigt
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L27/10832
摘要： A method is provided for manufacturing a buried strap contact between a transistor and a trench capacitor in a memory cell, particularly a DRAM memory cell. In this method, the two spacers of the gate electrode lying opposite one another and the gate path applied on the trench insulation of the memory cell serve as part of the mask that is employed for etching the contact trench and in which the buried bridge of the trench capacitor is subsequently generated. As a result, the position of that sidewall of the bridge facing toward the gate electrode is generated in self-aligning fashion relative to the gate electrode. This avoids photolithographic tolerances in the positioning of the bridge relative to the gate electrode.

3. 发明授权

US07045422B2 Semiconductor gate structure and method for fabricating a semiconductor gate structure 有权
标题翻译：半导体栅极结构和半导体栅极结构的制造方法
公开(公告)号：US07045422B2
公开(公告)日：2006-05-16
申请号：US10854772
申请日：2004-05-27
申请人： Gerhard Enders , Helmut Schneider , Peter Voigt
发明人： Gerhard Enders , Helmut Schneider , Peter Voigt
IPC分类号： H01L29/72
CPC分类号： H01L29/66583 , H01L21/28247 , H01L29/66553 , H01L29/6656
摘要： A method for fabricating a semiconductor gate structure including depositing at least one sacrificial layer on a semiconductor substrate; patterning the at least one sacrificial layer to form at least one cutout in the at least one sacrificial layer for uncovering the semiconductor substrate; forming a sidewall spacer over the sidewalls of the at least one sacrificial layer in the at least one cutout; forming a gate dielectric on the semiconductor substrate in the cutout; providing a gate electrode in the at least one cutout in the at lest one sacrificial layer; and removing the at least one sacrificial layer for the uncovering the gate electrode surrounded by the sidewall spacer. A semiconductor device is also provided.
摘要翻译：一种用于制造半导体栅极结构的方法，包括在半导体衬底上沉积至少一个牺牲层; 图案化所述至少一个牺牲层以在所述至少一个牺牲层中形成至少一个切口以露出所述半导体衬底; 在所述至少一个切口中的所述至少一个牺牲层的侧壁上形成侧壁间隔物; 在所述切口中的所述半导体基板上形成栅极电介质; 在所述至少一个牺牲层中的所述至少一个切口中提供栅电极; 以及去除所述至少一个牺牲层以露出由所述侧壁间隔物包围的所述栅电极。还提供了半导体器件。

4. 发明申请

US20070040202A1 Semiconductor memory cell array having self-aligned recessed gate MOS transistors and method for forming the same 审中-公开
标题翻译：具有自对准凹栅MOS晶体管的半导体存储单元阵列及其形成方法
公开(公告)号：US20070040202A1
公开(公告)日：2007-02-22
申请号：US11206306
申请日：2005-08-18
申请人： Gerhard Enders , Marc Strasser , Peter Voigt , Bjorn Fischer
发明人： Gerhard Enders , Marc Strasser , Peter Voigt , Bjorn Fischer
IPC分类号： H01L29/94 , H01L21/8242
CPC分类号： H01L27/10876 , H01L27/10861
摘要： In a semiconductor memory including an array of memory cells, each memory cell includes a trench capacitor, the trench capacitor including an inner electrode, an outer electrode and a dielectric layer disposed between the inner electrode and the outer electrode, and a selection transistor, the selection transistor including a first source/drain area, a second source/drain area and a channel region disposed between the first source/drain area and the second source/drain area in a recess, the trench capacitor and the selection transistor of each memory cell are disposed side by side, the first source/drain area of the selection transistor being electrically connected to the inner electrode of the trench capacitor, the recess in which the channel region of the selection transistor is formed being located self aligned between the trench capacitor of the memory cell and the trench capacitor of an adjacent memory cell.
摘要翻译：在包括存储单元阵列的半导体存储器中，每个存储单元包括沟槽电容器，所述沟槽电容器包括内电极，外电极和设置在内电极和外电极之间的电介质层，以及选择晶体管，选择晶体管，其包括第一源极/漏极区域，第二源极/漏极区域和设置在凹部中的第一源极/漏极区域和第二源极/漏极区域之间的沟道区域，每个存储器单元的沟槽电容器和选择晶体管并排配置，选择晶体管的第一源极/漏极区域电连接到沟槽电容器的内部电极，形成选择晶体管的沟道区域的凹槽位于沟槽电容器的沟槽电容器之间，存储单元和相邻存储单元的沟槽电容器。

5. 发明授权

US07081392B2 Method for fabricating a gate structure of a FET and gate structure of a FET 失效
标题翻译：用于制造FET的栅极结构和FET的栅极结构的方法
公开(公告)号：US07081392B2
公开(公告)日：2006-07-25
申请号：US10897403
申请日：2004-07-23
申请人： Gerhard Enders , Peter Voigt
发明人： Gerhard Enders , Peter Voigt
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/4966 , H01L29/66492 , H01L29/6653 , H01L29/66545 , H01L29/7833
摘要： A method for fabricating a gate structure of a FET, having: (a) deposition and patterning of a sacrificial layer sequence on a semiconductor substrate and uncovering of a gate section; (b) implantation of a channel doping into the gate section; (c) deposition and patterning of spacers at the sidewalls of the sacrificial layer sequence with the formation of a gate section that is not covered by the spacers; (d) introduction of a mask material into the gate section that is not covered by the spacers; (e) removal of the spacers selectively with respect to the sacrificial layer sequence and mask material); (f) implantation of a halo doping in regions uncovered by the removed spacers; (g) removal of the mask material; (h) formation of a gate on the gate section; and (j) removal of the sacrificial layer sequence selectively with respect to the gate.
摘要翻译：一种用于制造FET的栅极结构的方法，具有：（a）在半导体衬底上沉积和图案化牺牲层序列并露出栅极部分; （b）将沟道掺杂注入到栅极部分中; （c）在牺牲层序列的侧壁处沉积和图案化间隔物，形成未被间隔物覆盖的栅极部分; （d）将掩模材料引入未被间隔物覆盖的栅极部分; （e）相对于牺牲层序列和掩模材料选择性去除间隔物）; （f）在被去除的间隔物覆盖的区域内注入晕圈; （g）去除掩模材料; （h）在栅极部分上形成栅极; 和（j）相对于栅极选择性地去除牺牲层序列。

6. 发明申请

US20070002691A1 Buried strap contact for a storage capacitor and method for fabricating it 审中-公开
公开(公告)号：US20070002691A1
公开(公告)日：2007-01-04
申请号：US11503162
申请日：2006-08-14
申请人： Peter Voigt , Gerhard Enders
发明人： Peter Voigt , Gerhard Enders
IPC分类号： G04C21/00
CPC分类号： H01L27/10867 , H01L27/10829 , H01L29/66181 , H01L29/945
摘要： A buried strap contact between a trench capacitor of a memory cell and the subsequently formed selection transistor of the memory cell is fabricated such that the inner capacitor electrode layer is etched back in the trench of the trench capacitor and the uncovered insulator layer is then removed at the trench wall in order to define the region of the buried strap contact area. A liner layer is subsequently deposited in order to cover the inner capacitor electrode layer in the trench and the uncovered trench wall and thus to form a barrier layer. A spacer layer with the material of the inner electrode layer is then formed on the liner layer at the trench wall. Finally, the uncovered liner layer is removed above the inner electrode layer and the trench is filled with the material of the inner electrode layer in order to fabricate the buried strap contact.

7. 发明申请

US20050026359A1 Buried strap contact for a storage capacitor and method for fabricating it 有权
标题翻译：用于存储电容器的埋地带接触器及其制造方法
公开(公告)号：US20050026359A1
公开(公告)日：2005-02-03
申请号：US10875787
申请日：2004-06-25
申请人： Peter Voigt , Gerhard Enders
发明人： Peter Voigt , Gerhard Enders
IPC分类号： H01L21/334 , H01L21/82 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10867 , H01L27/10829 , H01L29/66181 , H01L29/945
摘要： A buried strap contact between a trench capacitor of a memory cell and the subsequently formed selection transistor of the memory cell is fabricated such that the inner capacitor electrode layer is etched back in the trench of the trench capacitor and the uncovered insulator layer is then removed at the trench wall in order to define the region of the buried strap contact area. A liner layer is subsequently deposited in order to cover the inner capacitor electrode layer in the trench and the uncovered trench wall and thus to form a barrier layer. A spacer layer with the material of the inner electrode layer is then formed on the liner layer at the trench wall. Finally, the uncovered liner layer is removed above the inner electrode layer and the trench is filled with the material of the inner electrode layer in order to fabricate the buried strap contact.
摘要翻译：制造存储器单元的沟槽电容器和随后形成的存储单元的选择晶体管之间的掩埋带接触，使得在沟槽电容器的沟槽中回蚀刻内部电容器电极层，然后将未覆盖的绝缘体层去除沟槽壁为了限定埋地带的接触区域。随后沉积衬里层以覆盖沟槽中的内部电容器电极层和未覆盖的沟槽壁，从而形成阻挡层。然后在沟槽壁上的衬垫层上形成具有内部电极层的材料的间隔层。最后，在内部电极层上方移除未覆盖的衬垫层，并且用内部电极层的材料填充沟槽，以便制造掩埋带接触。

8. 发明申请

US20060148178A1 Method for producing a vertical transistor 审中-公开
标题翻译：垂直晶体管的制造方法
公开(公告)号：US20060148178A1
公开(公告)日：2006-07-06
申请号：US11367217
申请日：2006-03-03
申请人： Dietrich Bonart , Gerhard Enders , Peter Voigt
发明人： Dietrich Bonart , Gerhard Enders , Peter Voigt
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L27/10876 , H01L27/10841 , H01L29/78642
摘要： The present invention relates to a method for producing a vertical transistor, and to a vertical transistor. A sacrificial gate oxide and a sacrificial gate electrode are used during the production of the vertical transistor to makes it possible to considerably reduce or entirely avoid negative effects that normally result from the production of insulation structures between the vertical transistors. In particular, broadening of the gate oxide at the edge of the gate electrode can be prevented, and the edge of the gate electrode can be influenced deliberately. This allows vertical transistors to be produced having a current/voltage characteristic that can be adjusted specifically. In particular, vertical transistors can be produced having a pronounced corner effect.
摘要翻译：本发明涉及垂直晶体管的制造方法和垂直晶体管。在制造垂直晶体管期间使用牺牲栅极氧化物和牺牲栅电极，使得可以显着地减少或完全避免通常由垂直晶体管之间的绝缘结构的产生产生的负面影响。特别地，可以防止在栅电极的边缘处的栅极氧化物的扩大，并且栅电极的边缘可能被故意地影响。这允许产生具有能够被特别调整的电流/电压特性的垂直晶体管。特别地，可以产生具有显着角落效应的垂直晶体管。

9. 发明授权

US06838335B2 Method for fabricating a vertical transistor, and semiconductor memory cell having a trench capacitor and an associated vertical selection transistor 有权
标题翻译：用于制造垂直晶体管的方法，以及具有沟槽电容器和相关联的垂直选择晶体管的半导体存储单元
公开(公告)号：US06838335B2
公开(公告)日：2005-01-04
申请号：US10626956
申请日：2003-07-25
申请人： Dietrich Bonart , Gerhard Enders , Peter Voigt
发明人： Dietrich Bonart , Gerhard Enders , Peter Voigt
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10876 , H01L29/945
摘要： A semiconductor memory is fabricated with a vertical transistor situated in an upper section of a trench above a trench capacitor. First, an auxiliary insulation layer is applied to the conductive material of an inner electrode or to a connecting material of the trench capacitor. The connecting material is situated on the inner electrode, so that, during an epitaxial deposition, semiconductor material grows only on the uncovered sidewalls in the upper section of the trench. A nitride layer, is deposited conformally and the residual cavity between the inner electrode and the epitaxial semiconductor layer is filled with a doped further conductive material. The nitride layer isolates the epitaxial semiconductor layer from the further conductive material, so that no crystal lattice defects can propagate from there into the epitaxial semiconductor layer. Dopants are outdiffused from the further conductive material into the epitaxial semiconductor layer to form a doping region.
摘要翻译：制造半导体存储器，其具有位于沟槽电容器上方的沟槽的上部中的垂直晶体管。首先，将辅助绝缘层施加到内部电极的导电材料或沟槽电容器的连接材料。连接材料位于内部电极上，使得在外延沉积期间，半导体材料仅在沟槽上部的未覆盖侧壁上生长。氮化物层被共形沉积，并且内部电极和外延半导体层之间的残余腔填充有掺杂的另外的导电材料。氮化物层将外延半导体层与另外的导电材料隔离，使得没有晶格缺陷可以从那里传播到外延半导体层。掺杂剂从另外的导电材料向外扩散到外延半导体层中以形成掺杂区域。

10. 发明授权

US07163857B2 Buried strap contact for a storage capacitor and method for fabricating it 有权
标题翻译：用于存储电容器的埋地带接触器及其制造方法
公开(公告)号：US07163857B2
公开(公告)日：2007-01-16
申请号：US10875787
申请日：2004-06-25
申请人： Peter Voigt , Gerhard Enders
发明人： Peter Voigt , Gerhard Enders
IPC分类号： H01L21/8242
CPC分类号： H01L27/10867 , H01L27/10829 , H01L29/66181 , H01L29/945
摘要： A buried strap contact between a trench capacitor of a memory cell and the subsequently formed selection transistor of the memory cell is fabricated such that the inner capacitor electrode layer is etched back in the trench of the trench capacitor and the uncovered insulator layer is then removed at the trench wall in order to define the region of the buried strap contact area. A liner layer is subsequently deposited in order to cover the inner capacitor electrode layer in the trench and the uncovered trench wall and thus to form a barrier layer. A spacer layer with the material of the inner electrode layer is then formed on the liner layer at the trench wall. Finally, the uncovered liner layer is removed above the inner electrode layer and the trench is filled with the material of the inner electrode layer in order to fabricate the buried strap contact.
摘要翻译：制造存储器单元的沟槽电容器和随后形成的存储单元的选择晶体管之间的掩埋带接触，使得在沟槽电容器的沟槽中回蚀刻内部电容器电极层，然后将未覆盖的绝缘体层去除沟槽壁为了限定埋地带的接触区域。随后沉积衬里层以覆盖沟槽中的内部电容器电极层和未覆盖的沟槽壁，从而形成阻挡层。然后在沟槽壁上的衬垫层上形成具有内部电极层的材料的间隔层。最后，在内部电极层上方移除未覆盖的衬垫层，并且用内部电极层的材料填充沟槽，以便制造掩埋带接触。

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