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1. 发明授权

US06608771B2 Low-power circuit structures and methods for content addressable memories and random access memories 失效
标题翻译：用于内容可寻址存储器和随机存取存储器的低功率电路结构和方法
公开(公告)号：US06608771B2
公开(公告)日：2003-08-19
申请号：US09933189
申请日：2001-08-20
申请人： Hans M. Jacobson , Prabhakar N. Kudva , Stanley Everett Schuster , Peter W. Cook
发明人： Hans M. Jacobson , Prabhakar N. Kudva , Stanley Everett Schuster , Peter W. Cook
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A method is provided for associating an address with data. The method includes precharging a matchline connected to a plurality of tag match functions to a first potential, wherein each tag match function comprises one or more match logic devices, discharging two tag lines for a first tag bit to ground, and reading a plurality of tag bits and corresponding data bits onto a plurality of tag lines and a plurality of data lines respectively. The method further includes determining a match between the tag bits and data bits, and pulling the matchline to a second potential upon determining a match for each of the tag bits.
摘要翻译：提供了一种用于将地址与数据相关联的方法。该方法包括将连接到多个标签匹配功能的匹配线预先充电到第一电位，其中每个标签匹配功能包括一个或多个匹配逻辑器件，将用于第一标签位的两个标签行放电到地，以及读取多个标签位和相应的数据位分别分配到多个标签行和多条数据线上。该方法还包括确定标签位和数据位之间的匹配，并且在确定每个标签位的匹配时，将匹配线拉到第二电位。

2. 发明授权

US06512397B1 Circuit structures and methods for high-speed low-power select arbitration 失效
标题翻译：用于高速低功耗选择仲裁的电路结构和方法
公开(公告)号：US06512397B1
公开(公告)日：2003-01-28
申请号：US09933188
申请日：2001-08-20
申请人： Hans M. Jacobson , Prabhakar N. Kudva , Peter W. Cook , Stanley Everett Schuster
发明人： Hans M. Jacobson , Prabhakar N. Kudva , Peter W. Cook , Stanley Everett Schuster
IPC分类号： H03K1720
CPC分类号： G06F13/14 , Y02D10/14
摘要： A method is provided for selecting a participant to issue. The method includes signaling a domino OR gate arbitration device upon a ready request of a participant having a priority, determining within the domino OR gate arbitration device the relative priority of the participant, signaling the domino OR gate arbitration device through an any-request device upon the ready request of a higher priority participant, and issuing the higher priority participant upon determining the higher priority participant to have a priority highest among participants ready for issue. The method includes gating one of a precharge signal and an evaluate signal of the precharged domino OR gate arbitration device by the ready request of the participant. The method further includes latching a result of the domino OR gate arbitration device and a clock signal, and gating the clock signal by the ready signal of the participant.
摘要翻译：提供了一种用于选择参与者发行的方法。该方法包括在具有优先权的参与者的就绪请求之后发信号通知多米诺骨牌或门仲裁装置，在多米诺诺或门仲裁装置内确定参与者的相对优先级，通过任何请求装置向多米诺骨牌或门仲裁装置发信号确定较高优先权的参与者的准备好的请求，并且在确定较高优先权的参与者之后发出优先权较高的参与者以便在准备发行的参与者中具有最高优先权。该方法包括通过参与者的就绪请求选通预充电多米诺OR门仲裁装置的预充电信号和评估信号之一。该方法还包括锁存多米诺OROR仲裁装置的结果和时钟信号，并通过参与者的就绪信号门控时钟信号。

3. 发明授权

US06946869B2 Method and structure for short range leakage control in pipelined circuits 失效
标题翻译：流水线电路短程泄漏控制的方法和结构
公开(公告)号：US06946869B2
公开(公告)日：2005-09-20
申请号：US10685863
申请日：2003-10-15
申请人： Hans M. Jacobson , Pradip Bose , Alper Buyuktosunoglu , Peter William Cook , Philip George Emma , Prabhakar N. Kudva , Stanley Everett Schuster
发明人： Hans M. Jacobson , Pradip Bose , Alper Buyuktosunoglu , Peter William Cook , Philip George Emma , Prabhakar N. Kudva , Stanley Everett Schuster
IPC分类号： H03K5/00 , H03K17/16 , H03K19/00
CPC分类号： H03K19/0016
摘要： Leakage current control devices include a circuit having one or more functions in a data path where the functions are executed in a sequence. Each of the functions has power reduction logic to energize each respective function. A leakage control circuit interacts with the power reduction logic, so that the functions are energized or deenergized in a control sequence such that the functions where the data is resident are energized and at least one of the other functions is not energized.
摘要翻译：泄漏电流控制装置包括在序列中执行功能的数据路径中具有一个或多个功能的电路。每个功能具有功率降低逻辑以激励每个相应的功能。泄漏控制电路与功率降低逻辑相互作用，使得功能在控制序列中被激励或断电，使得数据驻留的功能被激励，并且其他功能中的至少一个没有通电。

4. 发明授权

US06087225A Method for dual gate oxide dual workfunction CMOS 失效
标题翻译：双栅氧化双功函数CMOS方法
公开(公告)号：US06087225A
公开(公告)日：2000-07-11
申请号：US18939
申请日：1998-02-05
申请人： Gary Bela Bronner , Badih El-Kareh , Stanley Everett Schuster
发明人： Gary Bela Bronner , Badih El-Kareh , Stanley Everett Schuster
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L27/088 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10873 , H01L21/823842
摘要： A method of forming integrated circuit chips including two dissimilar type NFETs and/or two dissimilar type PFETs on the same chip, such as both thick and thin gate oxide FETs. A DRAM array may be constructed of the thick oxide FETs and logic circuits may be constructed of the thin oxide FETs on the same chip. First, a gate stack including a first, thick gate SiO.sub.2 layer is formed on a wafer. The stack includes a doped polysilicon layer on the gate oxide layer, a silicide layer on the polysilicon layer and a nitride layer on the silicide layer. Part of the stack is selectively removed to re-expose the wafer where logic circuits are to be formed. A thinner gate oxide layer is formed on the re-exposed wafer. Next, gates are formed on the thinner gate oxide layer and thin oxide NFETs and PFETs are formed at the gates. After selectively siliciding thin oxide device regions, gates are etched from the stack in the thick oxide device regions. Finally, source and drain regions are implanted and diffused for the thick gate oxide devices.
摘要翻译：在同一芯片上形成包括两个不同类型的NFET和/或两个不同类型的PFET的集成电路芯片的方法，例如厚和薄栅极氧化物FET。 DRAM阵列可以由厚氧化物FET构成，并且逻辑电路可以由同一芯片上的薄氧化物FET构成。首先，在晶片上形成包括第一厚栅极SiO 2层的栅极堆叠。堆叠包括栅极氧化物层上的掺杂多晶硅层，多晶硅层上的硅化物层和硅化物层上的氮化物层。选择性地去除堆叠的一部分以重新暴露将要形成逻辑电路的晶片。在再曝光的晶片上形成更薄的栅氧化层。接下来，在较薄的栅极氧化物层上形成栅极，并且在栅极处形成薄氧化物NFET和PFET。在选择性硅化薄氧化物器件区域之后，在厚氧化物器件区域中从堆叠中蚀刻栅极。最后，源极和漏极区域被注入并扩散用于厚栅极氧化物器件。

5. 发明授权

US5805494A Trench capacitor structures 失效
公开(公告)号：US5805494A
公开(公告)日：1998-09-08
申请号：US846603
申请日：1997-04-30
申请人： Badih El-Kareh , Richard Leo Kleinhenz , Stanley Everett Schuster
发明人： Badih El-Kareh , Richard Leo Kleinhenz , Stanley Everett Schuster
IPC分类号： H01L27/108 , H01L27/11 , H01L29/94 , G11C11/24
CPC分类号： H01L29/945 , H01L27/10829 , H01L27/1104 , Y10S257/903
摘要： An optimized trench capacitor structure which is useful as a decoupling capacitor or a storage capacitor can be manufactured without added process complexity. As an on-chip decoupling trench capacitor structure, the structure reduces the series resistance to outer and inner plates and results in an acceptable RC delay, while maintaining a high capacitance per unit area. As a storage capacitor with a buried shield, the trench capacitor structure exhibits high immunity to alpha particle and cosmic radiation induced failures. The trench capacitor structure which includes a buried n-well in a silicon substrate. A trench is formed in the substrate and extends through the buried n-well. A dielectric film is formed on an inner surface of the trench, and an inner plate formed as a polysilicon fill within the trench is connected to a surface n+ film formed during definition of peripheral source/drain contacts of the integrated circuit. An outer plate of the capacitor in the form of an out diffusion from the trench provides a low resistance electrical contact with the substrate. A number of these capacitors can be combined in a very efficient X-Y array of decoupling capacitors.

6. 发明授权

US06182233B2 Interlocked pipelined CMOS 有权
标题翻译：联锁流水线CMOS
公开(公告)号：US06182233B2
公开(公告)日：2001-01-30
申请号：US09196985
申请日：1998-11-20
申请人： Stanley Everett Schuster , Peter William Cook
发明人： Stanley Everett Schuster , Peter William Cook
IPC分类号： G06F112
CPC分类号： G06F9/3869
摘要： An interlocked pipelined CMOS (IPCMOS) family of logic circuits provides extremely high performance pipelined operation and guarantees error free operation where variations in timing are compensated for automatically by the circuits. The IPCMOS logic circuits also provide a standard interface that makes it possible to interface different macro types easily. The IPCMOS logic circuits feature interlocking in both the forward and reverse directions. This “handshaking” guarantees error free timing and makes it possible to eliminate the need for a global clock at the macro level. Timing signals are generated locally at the macro level from the handshaking signals between macros. This makes it possible for the local circuits to deal with global timing variations caused by power supply noise, ACLV, and parameter variations. The macros operate in a pipelined mode with data advancing automatically from macro to macro with the timing controlled by the local handshaking signals. This pipelined operation results in an extremely fast cycle time. Another feature of IPCMOS is that the data inputs to a macro are only sampled when the data is in a valid state. making the concept of a standard macro interface possible. With this standard interface, different logic types such as static and dynamic circuits can be easily interconnected and the concept of reusable macros becomes a reality.
摘要翻译：联锁流水线CMOS（IPCMOS）逻辑电路系列提供极高性能的流水线操作，并保证无错误运行，其中时序的变化由电路自动补偿。 IPCMOS逻辑电路还提供了一个标准接口，可以轻松地接口不同的宏类型。 IPCMOS逻辑电路在正向和反向方向均互锁。这种“握手”保证了无错误的定时，并且可以消除在宏观级别对全局时钟的需要。定时信号是从宏之间的握手信号在宏观级别本地生成的。这使得本地电路可以处理由电源噪声，ACLV和参数变化引起的全局时序变化。宏以流水线模式运行，数据由宏到宏自动提前，由本地握手信号控制。这种流水线操作导致极快的循环时间。 IPCMOS的另一个特点是仅当数据处于有效状态时才对宏进行数据输入。使得标准宏接口的概念成为可能。使用这种标准接口，可以轻松地将不同的逻辑类型（如静态和动态电路）互连起来，并且可重用宏的概念成为现实。

7. 发明授权

US6081872A Cache reloading performance improvement through the use of early select techniques with and without pipelining 失效
标题翻译：通过使用具有和不具有流水线的早期选择技术来缓存重新加载性能改进
公开(公告)号：US6081872A
公开(公告)日：2000-06-27
申请号：US888730
申请日：1997-07-07
申请人： Richard Edward Matick , Stanley Everett Schuster
发明人： Richard Edward Matick , Stanley Everett Schuster
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0897
摘要： A DRAM for L2 cache is used in a computer memory hierarchy without compromising overall system performance. By proper organization and design, the DRAM L2 cache is many times larger than a SRAM implementation in the same technology, but without compromising overall system performance. The larger DRAM capacity compared to a SRAM gives a substantially better HIT ratio which compensates for any small degradation due to access time. To achieve this, it is essential to minimize the total DRAM access time as much as possible by the use of early select techniques and pipelining.
摘要翻译：用于L2缓存的DRAM用于计算机存储器层次结构，而不会影响整个系统性能。通过适当的组织和设计，DRAM L2缓存比相同技术中的SRAM实现大很多倍，但不会影响整体系统性能。与SRAM相比，更大的DRAM容量提供了显着更好的HIT比，其补偿由于访问时间导致的任何小的劣化。为了实现这一点，必须通过使用早期选择技术和流水线尽可能地尽可能地最小化DRAM的总访问时间。

8. 发明授权

US5770969A Controllable decoupling capacitor 失效
标题翻译：可控去耦电容
公开(公告)号：US5770969A
公开(公告)日：1998-06-23
申请号：US518083
申请日：1995-08-22
申请人： Lloyd Andre Walls , Byron Lee Krauter , Stanley Everett Schuster
发明人： Lloyd Andre Walls , Byron Lee Krauter , Stanley Everett Schuster
IPC分类号： G05F3/24 , H03K17/16
CPC分类号： H02H7/16 , Y10T307/852
摘要： A decoupling capacitor and protection circuit is provided that will assist the power supply network in stabilizing the voltage near circuits that demand short rapid transitions in electrical current. The protection circuit also significantly reduces the amount of electrical current drawn by defective large area decoupling capacitors. An inverter stage controls a switching circuit connected in series with a decoupling capacitor. A feedback circuit is provided from the output of the capacitor to the switching circuit. If the capacitor goes bad, then a voltage is present on the feedback circuit and the switching circuit ensures that the output of the failed capacitor is presented with an open circuit so that the short circuit current flow through the capacitor is eliminated. In this manner, the integrity of the other circuits located near the failed capacitor will operate appropriately.
摘要翻译：提供去耦电容器和保护电路，其将帮助电源网络稳定电路附近的电压，从而要求电流中的快速快速转换。保护电路还显着减少了由大面积去耦电容器引起的电流量。逆变器级控制与去耦电容串联连接的开关电路。从电容器的输出到开关电路提供反馈电路。如果电容变坏，则反馈电路上存在电压，开关电路确保故障电容器的输出呈开路状态，从而消除短路电流流过电容器。以这种方式，位于故障电容器附近的其它电路的完整性将适当地运行。

9. 发明授权

US4001601A Two bit partitioning circuit for a dynamic, programmed logic array 失效
标题翻译：用于动态，编程逻辑阵列的双位分区电路
公开(公告)号：US4001601A
公开(公告)日：1977-01-04
申请号：US616734
申请日：1975-09-25
申请人： Stanley Everett Schuster
发明人： Stanley Everett Schuster
IPC分类号： H03K19/096 , H03K19/0185 , H03K19/173 , H03K19/177 , H03K19/08 , H03K17/10 , H03K17/56 , H03K19/34
CPC分类号： H03K19/1772 , H03K19/01855
摘要： A two bit partitioning circuit for a dynamic programmed logic array which introduces two stages of delay in the signal path in one clock cycle, with minimum power dissipation. The circuit has two primary inputs and four outputs which serve as inputs to a bootstrap driver which produces an output signal to the programmed logic array. A basic path through the circuit consists of two stages, the first stage comprising two active devices (FET) and a first capacitive means, while the second stage comprises three active devices and a second capacitive means. The major portion of the capacitance of the second stage is provided by the capacitance of the bootstrap driver. The stages are dynamic with the discharge speed of the first stage being much faster than that of the second stage thereby enabling a signal to propagate through the two stages in one clock cycle, with the only power dissipation being that required to charge the two capacitive means.

10. 发明授权

US5895487A Integrated processing and L2 DRAM cache 失效
标题翻译：集成处理和L2 DRAM缓存
公开(公告)号：US5895487A
公开(公告)日：1999-04-20
申请号：US748300
申请日：1996-11-13
申请人： William Todd Boyd , Thomas James Heller, Jr. , Michael Ignatowski , Richard Edward Matick , Stanley Everett Schuster
发明人： William Todd Boyd , Thomas James Heller, Jr. , Michael Ignatowski , Richard Edward Matick , Stanley Everett Schuster
IPC分类号： G06F12/08 , G06F15/78
CPC分类号： G06F12/0817 , G06F12/0897 , G06F15/7846 , G06F12/0851 , Y02B60/1225
摘要： An integrated processor and level two (L2) dynamic random access memory (DRAM) are fabricated on a single chip. As an extension of this basic structure, the invention also contemplates multiprocessor "node" chips in which multiple processors are integrated on a single chip with L2 cache. By integrating the processor and L2 DRAM cache on a single chip, high on-chip bandwidth, reduced latency and higher performance are achieved. A multiprocessor system can be realized in which a plurality of processors with integrated L2 DRAM cache are connected in a loosely coupled multiprocessor system. Alternatively, the single chip technology can be used to implement a plurality of processors integrated on a single chip with an L2 DRAM cache which may be either private or shared. This approach overcomes a number of issues which limit the performance and cost of a memory hierarchy. When the L2 DRAM cache is placed on the same chip as the processor, the time needed for two chip-to-chip crossings is eliminated. Since these crossings require off-chip drivers and receivers and must be synchronized with the system clock, the time involved is substantial. This means that with the integrated L2 DRAM cache, latency is reduced.
摘要翻译：在单个芯片上制造集成处理器和二级（L2）动态随机存取存储器（DRAM）。作为该基本结构的扩展，本发明还考虑了多处理器“节点”芯片，其中多个处理器集成在具有L2高速缓存的单个芯片上。通过将处理器和L2 DRAM缓存集成在单个芯片上，可实现高片上带宽，降低延迟和更高性能。可以实现多处理器系统，其中具有集成的L2 DRAM高速缓存的多个处理器连接在松散耦合的多处理器系统中。或者，单芯片技术可以用于实现集成在单个芯片上的多个处理器，其可以是私有的或共享的L2 DRAM缓存。这种方法克服了一些限制内存层次结构的性能和成本的问题。当L2 DRAM缓存放置在与处理器相同的芯片上时，消除了两个芯片到芯片交叉所需的时间。由于这些交叉点需要片外驱动器和接收器，并且必须与系统时钟同步，所涉及的时间是相当大的。这意味着使用集成的L2 DRAM高速缓存，延迟会降低。

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