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1. 发明授权

US4760518A Bi-directional databus system for supporting superposition of vector and scalar operations in a computer 失效
标题翻译：用于支持计算机中矢量和标量运算叠加的双向数据总线系统
公开(公告)号：US4760518A
公开(公告)日：1988-07-26
申请号：US835129
申请日：1986-02-28
申请人： Hanan Potash , Erick M. Cook , Andrew E. Phelps , Mark A. Haakmeester , Jennifer S. Schuh , William B. Thompson
发明人： Hanan Potash , Erick M. Cook , Andrew E. Phelps , Mark A. Haakmeester , Jennifer S. Schuh , William B. Thompson
IPC分类号： G06F13/36 , G06F9/38 , G06F15/78 , G06F17/16 , G06F3/00 , G06F13/00 , G06F13/40 , G06F15/347
CPC分类号： G06F15/8084 , G06F9/3885
摘要： A bi-directional databusing system is used in a computer that superposes vector and scalar operations. The computer consists of a main memory, a plurality of pipelined functional units, and a buffer for staging scalar and vector data objects between the main memory and the functional units. The busing system supports two-way data transfer during each of a succession of bus transfer cycles in which data is transferred to the buffer during one phase of a cycle, and from the buffer during a second cycle phase. The busing system includes three sets of bi-directional memory databuses, one for transferring scalar data objects between the main memory and buffer unit, and the other two for transferring vector data objects between the main memory and the buffer. The bus system also includes a set of bi-directional function buses, each for transferring scalar and vector data objects between the buffer and the functional units, with the ratio of the number of data objects transferred to the functional units during a transfer cycle to the number of data objects transferred to the buffer during the same cycle corresponding to a predetermined parametric value.
摘要翻译：双向数据处理系统用于叠加向量和标量运算的计算机中。计算机由主存储器，多个流水线功能单元和用于在主存储器和功能单元之间分级标量和向量数据对象的缓冲器组成。在一系列总线传输周期中，每个循环中的数据传输到缓冲区，在一个周期的一个阶段，以及在第二个循环阶段从缓冲区，这个传输系统支持双向数据传输。传播系统包括三组双向存储器数据总线，一组用于在主存储器和缓冲器单元之间传送标量数据对象，另外两个用于在主存储器和缓冲器之间传送矢量数据对象。总线系统还包括一组双向功能总线，每个用于在缓冲器和功能单元之间传送标量和向量数据对象，在传送周期期间传送到功能单元的数据对象的数量与在对应于预定参数值的相同周期内传送到缓冲器的数据对象的数量。

2. 发明授权

US4837730A Linking scalar results directly to scalar operation inputs on a bidirectional databus in a computer which superpositions vector and scalar operations 失效
标题翻译：将标量结果直接连接到计算机中的双向数据总线上的标量运算输入，该数据总线叠加向量和标量运算
公开(公告)号：US4837730A
公开(公告)日：1989-06-06
申请号：US11759
申请日：1987-02-06
申请人： Erick M. Cook , Andrew E. Phelps , Hanan Potash
发明人： Erick M. Cook , Andrew E. Phelps , Hanan Potash
IPC分类号： G06F9/38 , G06F15/78
CPC分类号： G06F9/3836 , G06F15/8084 , G06F9/3013 , G06F9/3824 , G06F9/3828 , G06F9/3838
摘要： In a computer which superpositions vector and scalar operations and in which operation results and operands are conducted between buffer registers and functional units on a bidirectional databus system, the result of one or more currently-executing scalar operations can be routed directly to the input of one or more functional units, bypassing the buffer registers and saving computer operational time. A scalar result is routed through a linking apparatus which directly connects a bidirectional databus path on which the scalar result is being conducted to a databus path on which a scalar operand is to be conducted. The routing is conditioned upon identity between the scalar result and operand and upon availability of a databus path to support the scalar operation. If the conditions are not met, the scalar result is conducted to the buffer registers, where it is held until needed or until a databus path is available.
摘要翻译：在重叠矢量和标量运算并且在双向数据总线系统的缓冲寄存器和功能单元之间进行操作结果和操作数的计算机中，一个或多个当前执行的标量运算的结果可以直接路由到一个或更多功能单元，绕过缓冲寄存器并节省计算机操作时间。标量结果通过链接设备进行路由，该链接设备直接将正在传导标量结果的双向数据总线路径连接到要在其上进行标量操作数的数据总线路径。路由是根据标量结果和操作数之间的标识，以及数据总线路径的可用性来支持标量运算。如果不满足条件，则标量结果被传送到缓冲寄存器，直到需要或直到数据总线路径可用为止。

3. 发明授权

US4538241A Address translation buffer 失效
标题翻译：地址转换缓冲区
公开(公告)号：US4538241A
公开(公告)日：1985-08-27
申请号：US513660
申请日：1983-07-14
申请人： Burton L. Levin , Andrew E. Phelps , Hanan Potash
发明人： Burton L. Levin , Andrew E. Phelps , Hanan Potash
IPC分类号： G06F12/10 , G06F13/00
CPC分类号： G06F12/1027
摘要： An apparatus is disclosed that translates virtual memory addresses into physical memory addresses. In particular, this apparatus comprises a plurality of rows of content addressable memory cells, a corresponding plurality of random access memory cells and another corresponding plurality of control circuits. The content addressable memory cells store the virtual memory addresses and the random access memory cells store the physical memory addresses. The control circuits are coupled to both the content addressable and the random access memory cells and are disposed for controlling the operation of the apparatus.
摘要翻译：公开了将虚拟存储器地址转换为物理存储器地址的装置。特别地，该装置包括多行内容可寻址存储单元，相应的多个随机存取存储单元和另一对应的多个控制电路。内容可寻址存储器单元存储虚拟存储器地址，并且随机存取存储器单元存储物理存储器地址。控制电路耦合到内容可寻址存储单元和随机存取存储单元两者，并被设置用于控制设备的操作。

4. 发明授权

US5706490A Method of processing conditional branch instructions in scalar/vector processor 失效
标题翻译：在标量/向量处理器中处理条件分支指令的方法
公开(公告)号：US5706490A
公开(公告)日：1998-01-06
申请号：US484103
申请日：1995-06-07
申请人： Douglas R. Beard , Andrew E. Phelps , Michael A. Woodmansee , Richard G. Blewett , Jeffrey A. Lohman , Alexander A. Silbey , George A. Spix , Frederick J. Simmons , Don A. Van Dyke
发明人： Douglas R. Beard , Andrew E. Phelps , Michael A. Woodmansee , Richard G. Blewett , Jeffrey A. Lohman , Alexander A. Silbey , George A. Spix , Frederick J. Simmons , Don A. Van Dyke
IPC分类号： G06F12/06 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/16 , G06F15/173 , G06F15/78 , G06F15/80 , G06F17/16 , G06F9/42
CPC分类号： G06F9/30087 , G06F11/3632 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/3004 , G06F9/30094 , G06F9/3013 , G06F9/30138 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3816 , G06F9/3828 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3846 , G06F9/3855 , G06F9/3857 , G06F9/3875 , G06F9/3885
摘要： A delayed branch mechanism maintains the flow of an instruction pipeline in a scalar/vector processor having an instruction cache and including instruction fetch means, a program counter, and instruction decode/issue means coupled to the instruction cache by means of the instruction pipeline. Conditional branch instructions are rated as likely conditional branch instructions or unlikely conditional branch instructions based on a probability that their branch conditions will be met. A number of pipeline clock periods required for testing the branch conditions are determined. The likely conditional branch instructions are issued and executed including transferring a branch-to-address to the program counter during the number of pipeline clock periods irrespective of a successful meeting of the branch conditions. A number of useful instructions sufficient to issue within the number of pipeline clock periods are placed into the instruction stream following the likely conditional branch instructions. A conditional branch instruction is canceled and returned to an instruction which would have followed the conditional branch instruction if the branch is not taken. No gap occurs in the instruction stream if the corresponding branch is successfully taken.
摘要翻译：延迟分支机制维持具有指令高速缓存的标量/向量处理器中的指令流水线的流程，并且包括通过指令流水线连接到指令高速缓存的指令提取装置，程序计数器和指令解码/发布装置。条件分支指令根据其分支条件将被满足的概率被评为可能的条件分支指令或不可能的条件分支指令。确定测试分支条件所需的多个流水线时钟周期。发出和执行可能的条件分支指令，包括在流水线时钟周期的数量内将分支到地址传送到程序计数器，而不管分支条件的成功满足。在可能的条件分支指令之后，将足以在流水线时钟周期内发出的许多有用指令放入指令流中。条件分支指令被取消并返回到如果不采用分支时将遵循条件分支指令的指令。如果相应的分支成功获取，则在指令流中不会发生间隙。

5. 发明授权

US5623650A Method of processing a sequence of conditional vector IF statements 失效
标题翻译：处理条件向量IF语句序列的方法
公开(公告)号：US5623650A
公开(公告)日：1997-04-22
申请号：US484124
申请日：1995-06-07
申请人： Douglas R. Beard , Andrew E. Phelps , Michael A. Woodmansee , Richard G. Blewett , Jeffrey A. Lohman , Alexander A. Silbey , George A. Spix , Frederick J. Simmons , Don A. Van Dyke
发明人： Douglas R. Beard , Andrew E. Phelps , Michael A. Woodmansee , Richard G. Blewett , Jeffrey A. Lohman , Alexander A. Silbey , George A. Spix , Frederick J. Simmons , Don A. Van Dyke
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/173 , G06F15/78 , G06F15/80 , G06F9/00
CPC分类号： G06F9/30101 , G06F11/3632 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30087 , G06F9/30094 , G06F9/3013 , G06F9/30138 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3816 , G06F9/3828 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3846 , G06F9/3857 , G06F9/3875 , G06F9/3885
摘要： A sequence of conditional vector IF statements is processed by employing a mask register and a condition register. Each conditional vector IF statement is typically performed on two vector registers, each having vector elements. A first conditional vector IF statement in the sequence is processed for those vector elements corresponding to set bits in the mask register. Bits are set in the condition register to reflect those vector elements which correspond to the set bits in the mask register for which the conditional vector IF statement is satisfied. The contents of the condition register are then moved into the mask register. A next conditional vector IF statement in the sequence is then processed for those vector elements corresponding to the new set bits in the mask register. Bits are then set in the condition register to reflect those vector elements which correspond to the new set bits in the mask register for which the conditional vector IF statement is satisfied.
摘要翻译：通过采用掩码寄存器和条件寄存器来处理条件向量IF语句的序列。每个条件向量IF语句通常在两个向量寄存器上执行，每个向量寄存器都有向量元素。对于与掩码寄存器中的设置位相对应的那些向量元素，处理序列中的第一个条件向量IF语句。在条件寄存器中设置比特，以反映对应于满足条件向量IF语句的掩码寄存器中的设置位的那些向量元素。然后将条件寄存器的内容移入掩码寄存器。然后对于与掩码寄存器中的新设置位相对应的那些向量元素，处理序列中的下一个条件向量IF语句。然后将比特设置在条件寄存器中以反映对应于满足条件向量IF语句的掩码寄存器中的新的设置位的那些向量元素。

6. 发明授权

US5499356A Method and apparatus for a multiprocessor resource lockout instruction 失效
标题翻译：多处理器资源锁定指令的方法和装置
公开(公告)号：US5499356A
公开(公告)日：1996-03-12
申请号：US173923
申请日：1993-12-28
申请人： Roger E. Eckert , Richard E. Hessel , Andrew E. Phelps , George A. Spix , Jimmie R. Wilson
发明人： Roger E. Eckert , Richard E. Hessel , Andrew E. Phelps , George A. Spix , Jimmie R. Wilson
IPC分类号： G06F9/30 , G06F9/312 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F9/46 , G06F11/36 , G06F15/173 , G06F15/78 , G06F15/80 , G06F12/14
CPC分类号： G06F15/8076 , G06F15/17381 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/3004 , G06F9/30069 , G06F9/30087 , G06F9/30094 , G06F9/30101 , G06F9/3012 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3824 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/526 , G06F2209/521
摘要： A method and apparatus for providing a resource lockout mechanism in a shared memory, multiprocessor system that is capable of performing both a read and write operation during the same memory operation. The load and flag instruction of the present invention can execute a read operation, followed by a write operation of a preselected flag value to the same memory location during the same memory operation. The load and flag instruction is particularly useful as a resource lockout mechanism for use in Monte Carlo applications.
摘要翻译：一种用于在共享存储器中提供资源锁定机制的方法和装置，该多处理器系统能够在同一存储器操作期间同时执行读取和写入操作。本发明的加载和标志指令可以在相同的存储器操作期间执行读取操作，随后将预选标志值写入同一个存储器位置。加载和标志指令特别适用于在蒙特卡罗应用程序中使用的资源锁定机制。

7. 发明授权

US06961827B2 Victim invalidation 有权
标题翻译：受害者无效
公开(公告)号：US06961827B2
公开(公告)日：2005-11-01
申请号：US10011115
申请日：2001-11-13
申请人： Patricia Shanahan , Andrew E. Phelps , Nicholas E. Aneshansley
发明人： Patricia Shanahan , Andrew E. Phelps , Nicholas E. Aneshansley
IPC分类号： G06F12/08 , G06F12/12 , G06F12/00
CPC分类号： G06F12/082 , G06F12/0808 , G06F12/0826 , G06F12/12
摘要： The present invention provides a method and apparatus for invalidating a victimized entry. The apparatus comprises a directory cache adapted to store one or more cache entries, and a control unit. The control unit is adapted to determine whether it is desirable to remove a shared cache entry from the directory cache, and invalidate the shared cache entry in response to determining that it is desirable to remove the shared cache entry from the directory cache.
摘要翻译：本发明提供一种使受害条目无效的方法和装置。该装置包括适于存储一个或多个高速缓存条目的目录缓存器和控制单元。控制单元适于确定是否期望从目录高速缓存中移除共享高速缓存条目，并且响应于确定希望从目录高速缓存中移除共享高速缓存条目而使共享高速缓存条目无效。

8. 发明授权

US06915450B2 Method and apparatus for arbitrating transactions between domains in a computer system 有权
标题翻译：用于仲裁计算机系统中的域之间的事务的方法和装置
公开(公告)号：US06915450B2
公开(公告)日：2005-07-05
申请号：US10034919
申请日：2001-11-01
申请人： Andrew E. Phelps , Thomas P. Van Wormer , Gary L. Riddle
发明人： Andrew E. Phelps , Thomas P. Van Wormer , Gary L. Riddle
IPC分类号： G06F11/10 , G06F11/00 , G06F15/173
CPC分类号： G06F11/2023 , H04L1/0061
摘要： A method for communicating transactions includes providing an interconnect having a plurality of ports for communicating transactions between a plurality of domains in a computing system is provided. Each port is associated with a subset of the domains. The interconnect includes a first signal path for transmitting a first portion of the transaction and a second signal path for transmitting a second portion of the transaction. A transaction issued from a port associated with more than one of the domains is identified. An error in one of the first and second portions of the transaction is identified. The transaction is canceled responsive to identifying the error. A computing system for communicating transactions includes first and second devices. The first device is adapted to receive a first portion of a transaction. The second device is adapted to receive a second portion of the transaction in lockstep with respect to the first device. The first and second devices are further configured to identify an error in one of the first and second portions of the transaction, respectively, and the one of the first and second devices that identifies the error is further configured to send a notification signal to the device associated with the other of the first and second portions of the transaction responsive to identifying the error.
摘要翻译：用于通信交易的方法包括提供具有用于在计算系统中的多个域之间传送交易的多个端口的互连。每个端口与域的子集相关联。互连包括用于发送交易的第一部分的第一信号路径和用于发送交易的第二部分的第二信号路径。识别从与多个域相关联的端口发出的事务。识别事务的第一和第二部分之一的错误。响应于识别错误而取消交易。用于通信交易的计算系统包括第一和第二设备。第一设备适于接收事务的第一部分。第二设备适于在锁定步骤中相对于第一设备接收交易的第二部分。第一和第二设备还被配置为分别在事务的第一和第二部分之一中识别错误，并且识别错误的第一和第二设备中的一个设备进一步被配置为向设备发送通知信号与交易的第一和第二部分中的另一个相关联，以响应于识别错误。

9. 发明授权

US06408409B1 Method and apparatus for ring buffer flow error detection 有权
标题翻译：环形缓冲流量误差检测方法及装置
公开(公告)号：US06408409B1
公开(公告)日：2002-06-18
申请号：US09418624
申请日：1999-11-15
申请人： Emrys J. Williams , Andrew E. Phelps
发明人： Emrys J. Williams , Andrew E. Phelps
IPC分类号： G11C2900
CPC分类号： G06F5/10
摘要： A system for detecting underflow and overflow errors arising within a ring buffer. When the system receives a data word to be transferred through the ring buffer, the system generates a flow indicator value to be stored with the data word in the ring buffer. This flow indicator value contains information that facilitates determining if an underflow has occurred while reading from the ring buffer, or if an overflow has occurred while writing to the ring buffer. Next, the system writes the data word along with the flow indicator value into an entry in the ring buffer. At a later time, the system reads the entry from the ring buffer and generates a predicted flow indicator value. The system compares the flow indicator value read from the ring buffer with the predicted flow indicator value. If the flow indicator value differs from the predicted flow indicator value, the system generates an error signal indicating that an underflow or an overflow has occurred. In one embodiment of the present invention, the flow indicator value periodically changes, so that a predictably different flow indicator value is written into the entry in the ring buffer upon successive write operations to the entry. This predictably different flow indicator value allows the system to detect an underflow condition or an overflow condition by comparing the flow indicator value with the predicted flow indicator value. If the flow indicator value read from the ring buffer differs from the predicted flow indicator value, an underflow condition or overflow condition has occurred.
摘要翻译：用于检测环形缓冲区内出现的下溢和溢出错误的系统。当系统接收到要通过环形缓冲区传输的数据字时，系统将生成与数据字一起存储在环形缓冲区中的流量指示器值。此流程指示器值包含有助于确定在从环形缓冲区读取时是否发生下溢，或者在写入环形缓冲区时是否发生溢出的信息。接下来，系统将数据字与流量指示器值一起写入环形缓冲区中的条目。稍后，系统从环形缓冲器读取条目并生成预测的流量指示器值。系统将从环形缓冲器读取的流量指示器值与预测的流量指示器值进行比较。如果流量指示器值与预测的流量指示器值不同，则系统产生指示发生下溢或溢出的错误信号。在本发明的一个实施例中，流量指示器值周期性地变化，使得在对该条目的连续写入操作时，可预测地不同的流量指示器值被写入环形缓冲器中的条目。这种可预测的不同的流量指示器值允许系统通过将流量指示器值与预测的流量指示器值进行比较来检测下溢条件或溢出状况。如果从环形缓冲器读取的流量指示器值与预测的流量指示器值不同，则发生下溢条件或溢出条件。

10. 发明授权

US5524255A Method and apparatus for accessing global registers in a multiprocessor system 失效
标题翻译：用于在多处理器系统中访问全局寄存器的方法和装置
公开(公告)号：US5524255A
公开(公告)日：1996-06-04
申请号：US379123
申请日：1995-01-27
申请人： Douglas R. Beard , George A. Spix , Edward C. Miller , Robert E. Strout, II , Anthony R. Schooler , Alexander A. Silbey , Brian D. Vanderwarn , Jimmie R. Wilson , Richard E. Hessel , Andrew E. Phelps
发明人： Douglas R. Beard , George A. Spix , Edward C. Miller , Robert E. Strout, II , Anthony R. Schooler , Alexander A. Silbey , Brian D. Vanderwarn , Jimmie R. Wilson , Richard E. Hessel , Andrew E. Phelps
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/17 , G06F15/173 , G06F15/78 , G06F15/80 , G06F15/163
CPC分类号： G06F9/3004 , G06F15/17 , G06F15/17375 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/30043 , G06F9/30087 , G06F9/30094 , G06F9/30101 , G06F9/3012 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： A global register system provides communication and coordination among a plurality of processors sharing a common memory in a multiprocessor system which access one or more registers within a shared resource circuit that is separate from the common memory and is symmetrically accessible by the plurality of processors in the multiprocessor system. The global register system is accessed by direct addresses determined by the processor from a previously assigned indirect address and an instruction accessing the data stored in global registers. Arithmetic or logic operation on a data value stored in a selected one of the registers are performed by the global register system independent from the processors or the common memory in order to modify the data value in the selected global register as part of an atomic operation performed in response to a single read-and-modify instruction received from one of the processors.
摘要翻译：全局注册系统提供在多处理器系统中共享公共存储器的多个处理器之间的通信和协调，多处理器系统访问共享资源电路内的一个或多个与公共存储器分离的寄存器，并且可由多个处理器对称地访问多处理器系统全局寄存器系统由处理器从先前分配的间接地址确定的直接地址和访问存储在全局寄存器中的数据的指令访问。存储在所选择的一个寄存器中的数据值的算术或逻辑运算由独立于处理器或公共存储器的全局寄存器系统执行，以便修改所选择的全局寄存器中的数据值，作为执行的原子操作的一部分响应于从一个处理器接收的单个读取和修改指令。

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