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1. 发明授权

US5430884A Scalar/vector processor 失效
标题翻译：标量/矢量处理器
公开(公告)号：US5430884A
公开(公告)日：1995-07-04
申请号：US536409
申请日：1990-06-11
申请人： Douglas R. Beard , Andrew E. Phelps , Michael A. Woodmansee , Richard G. Blewett , Jeffrey A. Lohman , Alexander A. Silbey , George A. Spix , Frederick J. Simmons , Don A. Van Dyke
发明人： Douglas R. Beard , Andrew E. Phelps , Michael A. Woodmansee , Richard G. Blewett , Jeffrey A. Lohman , Alexander A. Silbey , George A. Spix , Frederick J. Simmons , Don A. Van Dyke
IPC分类号： G06F12/06 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/16 , G06F15/173 , G06F15/78 , G06F15/80 , G06F17/16
CPC分类号： G06F9/30087 , G06F11/3632 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/3004 , G06F9/30094 , G06F9/3013 , G06F9/30138 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3816 , G06F9/3828 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3846 , G06F9/3855 , G06F9/3857 , G06F9/3875 , G06F9/3885
摘要： The present invention is an improved high performance scalar/vector processor. In the preferred embodiment, the scalar/vector processor is used in a multiprocessor system. The scalar/vector processor is comprised of a scalar processor for operating on scalar and logical instructions, including a plurality of independent functional units operably connected to the scalar processor, a vector processor for operating on vector instructions, including a plurality of independent functional units operably connected to the vector processor, and an instruction control mechanism for fetching both the scalar and vector instructions from an instruction cache and controlling the operation of those instructions in both the scalar and vector processor. The instruction control mechanism is designed to enhance the performance of the scalar/vector processor by keeping a multiplicity of pipelines substantially filled with a minimum number of gaps.
摘要翻译：本发明是一种改进的高性能标量/向量处理器。在优选实施例中，在多处理器系统中使用标量/向量处理器。标量/矢量处理器包括用于对标量和逻辑指令进行操作的标量处理器，包括可操作地连接到标量处理器的多个独立功能单元，用于在矢量指令上操作的矢量处理器，包括多个独立的功能单元，连接到向量处理器，以及指令控制机制，用于从指令高速缓存取出标量和向量指令，并控制标量和向量处理器中的这些指令的操作。指令控制机制旨在通过保持基本上填充有最小数量的间隙的多个管线来增强标量/向量处理器的性能。

2. 发明授权

US5428803A Method and apparatus for a unified parallel processing architecture 失效
标题翻译：统一并行处理架构的方法和装置
公开(公告)号：US5428803A
公开(公告)日：1995-06-27
申请号：US912964
申请日：1992-07-10
申请人： Steve S. Chen , Douglas R. Beard , George A. Spix , Edward C. Priest , John M. Wastlick , James M. VanDyke
发明人： Steve S. Chen , Douglas R. Beard , George A. Spix , Edward C. Priest , John M. Wastlick , James M. VanDyke
IPC分类号： G06F9/38 , G06F1/10 , G06F12/06 , G06F13/16 , G06F15/173 , G06F3/60
CPC分类号： G06F13/1657 , G06F1/10 , G06F13/1663 , G06F15/17337 , G06F15/17381
摘要： A unified parallel processing architecture connects together an extendible number of clusters of multiple numbers of processors to create a high performance parallel processing computer system. Multiple processors are grouped together into four or more physically separable clusters, each cluster having a common cluster shared memory that is symmetrically accessible by all of the processors in that cluster; however, only some of the clusters are adjacently interconnected. Clusters are adjacently interconnected to form a floating shared memory if certain memory access conditions relating to relative memory latency and relative data locality can create an effective shared memory parallel programming environment. A shared memory model can be used with programs that can be executed in the cluster shared memory of a single cluster, or in the floating shared memory that is defined across an extended shared memory space comprised of the cluster shared memories of any set of adjacently interconnected clusters. A distributed memory model can be used with any programs that are to be executed in the cluster shared memories of any non-adjacently interconnected clusters. The adjacent interconnection of multiple clusters of processors to a create a floating shared memory effectively combines all three type of memory models, pure shared memory, extended shared memory and distributed shared memory, into a unified parallel processing architecture.
摘要翻译：统一的并行处理架构将多个处理器的可扩展数量的集群连接在一起，以创建高性能并行处理计算机系统。多个处理器被分组到四个或更多个物理上可分离的群集中，每个群集具有由该群集中的所有处理器对称地访问的公共群集共享存储器; 然而，只有一些集群是相互关联的。如果与相对存储器延迟和相对数据局部性相关的某些存储器访问条件可以创建有效的共享存储器并行编程环境，则群集相互互连以形成浮动共享存储器。共享存储器模型可以与可以在单个集群的集群共享存储器中执行的程序一起使用，或者在由包括相邻互连的任何集合的集群共享存储器的扩展共享存储器空间中定义的浮动共享存储器中使用集群。分布式存储器模型可以与要在任何非相邻互连的集群的集群共享存储器中执行的任何程序一起使用。处理器的多个集群的相邻互连以创建浮动共享存储器有效地将所有三种类型的存储器模型，纯共享存储器，扩展共享存储器和分布式共享存储器组合成统一的并行处理架构。

3. 发明授权

US5197130A Cluster architecture for a highly parallel scalar/vector multiprocessor system 失效
标题翻译：高分辨率/矢量多媒体系统的集群架构
公开(公告)号：US5197130A
公开(公告)日：1993-03-23
申请号：US459083
申请日：1989-12-29
申请人： Steve S. Chen , Frederick J. Simmons , George A. Spix , Jimmie R. Wilson , Edward C. Miller , Roger E. Eckert , Douglas R. Beard
发明人： Steve S. Chen , Frederick J. Simmons , George A. Spix , Jimmie R. Wilson , Edward C. Miller , Roger E. Eckert , Douglas R. Beard
IPC分类号： G06F12/06 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/16 , G06F15/173 , G06F15/78 , G06F15/80 , G06F17/16
CPC分类号： G06F9/30087 , G06F11/3632 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/3004 , G06F9/30094 , G06F9/3013 , G06F9/30138 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3816 , G06F9/3828 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3846 , G06F9/3855 , G06F9/3857 , G06F9/3875 , G06F9/3885
摘要： A cluster architecture for a highly parallel multiprocessor computer processing system is comprised of one or more clusters of tightly-coupled, high-speed processors capable of both vector and scalar parallel processing that can symmetrically access shared resources associated with the cluster, as well as the shared resources associated with other clusters.
摘要翻译：用于高度并行多处理器计算机处理系统的集群架构由一个或多个紧密耦合的高速处理器群组成，能够对向地访问与集群相关联的共享资源的向量和标量并行处理，以及与其他集群相关联的共享资源。

4. 发明授权

US5717881A Data processing system for processing one and two parcel instructions 失效
标题翻译：用于处理一个和两个包裹指令的数据处理系统
公开(公告)号：US5717881A
公开(公告)日：1998-02-10
申请号：US481060
申请日：1995-06-07
申请人： Douglas R. Beard , Andrew E. Phelps , Michael A. Woodmansee , Richard G. Blewett , Jeffrey A. Lohman , Alexander A. Silbey , George A. Spix , Frederick J. Simmons , Don A. Van Dyke
发明人： Douglas R. Beard , Andrew E. Phelps , Michael A. Woodmansee , Richard G. Blewett , Jeffrey A. Lohman , Alexander A. Silbey , George A. Spix , Frederick J. Simmons , Don A. Van Dyke
IPC分类号： G06F12/06 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/16 , G06F15/173 , G06F15/78 , G06F15/80 , G06F17/16
CPC分类号： G06F9/30087 , G06F11/3632 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/3004 , G06F9/30094 , G06F9/3013 , G06F9/30138 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3816 , G06F9/3828 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3846 , G06F9/3855 , G06F9/3857 , G06F9/3875 , G06F9/3885
摘要： An improved high performance hardwired supercomputer data processing apparatus includes instruction means adpated to issue one and two parcel instructions. Instruction fetch means provides an instruction stream of two parcel items in sequence. Instruction decode means is responsive to each two parcel item for determining in one clock cycle whether the two parcel item is a single two parcel instruction or two one parcel instructions, for issuing each two parcel instruction for execution during the one clock cycle, and for issuing one then the other of the two one parcel instructions for execution in sequence during the one clock cycle and the next succeeding clock cycle.
摘要翻译：改进的高性能硬连线超级计算机数据处理装置包括用于发出一个和两个包裹指令的指令装置。指令提取装置依次提供两个包裹项目的指令流。指令解码装置响应于每个两个宗地项目，以在一个时钟周期内确定两个宗地项目是否是单个两个宗地指令或两个一个包裹指令，用于在一个时钟周期内发出每个两个宗地指令以执行，并发出一个是两个一个包裹指令中的另一个，用于在一个时钟周期和下一个后续时钟周期期间依次执行。

5. 发明授权

US5659706A Vector/scalar processor with simultaneous processing and instruction cache filling 失效
标题翻译：矢量/标量处理器，同时处理和指令缓存填充
公开(公告)号：US5659706A
公开(公告)日：1997-08-19
申请号：US486612
申请日：1995-06-07
申请人： Douglas R. Beard , Andrew E. Phelps , Michael A. Woodmansee , Richard G. Blewett , Jeffrey A. Lohman , Alexander A. Silbey , George A. Spix , Frederick J. Simmons , Don A. Van Dyke
发明人： Douglas R. Beard , Andrew E. Phelps , Michael A. Woodmansee , Richard G. Blewett , Jeffrey A. Lohman , Alexander A. Silbey , George A. Spix , Frederick J. Simmons , Don A. Van Dyke
IPC分类号： G06F12/06 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/16 , G06F15/173 , G06F15/78 , G06F15/80 , G06F17/16 , G06F13/00
CPC分类号： G06F9/30087 , G06F11/3632 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/3004 , G06F9/30094 , G06F9/3013 , G06F9/30138 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3816 , G06F9/3828 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3846 , G06F9/3855 , G06F9/3857 , G06F9/3875 , G06F9/3885
摘要： The present invention is an improved high performance scalar/vector processor. In the preferred embodiment, the scalar/vector processor is used in a multiprocessor system. The scalar/vector processor is comprised of a scalar processor for operating on scalar and logical instructions, including a plurality of independent functional units operably connected to the scalar processor, a vector processor for operating on vector instructions, including a plurality of independent functional units operably connected to the vector processor, and an instruction control mechanism for fetching both the scalar and vector instructions from an instruction cache and controlling the operation of those instructions in both the scalar and vector processor. The instruction control mechanism is designed to enhance the performance of the scalar/vector processor by keeping a multiplicity of pipelines substantially filled with a minimum number of gaps.
摘要翻译：本发明是一种改进的高性能标量/向量处理器。在优选实施例中，在多处理器系统中使用标量/向量处理器。标量/矢量处理器包括用于对标量和逻辑指令进行操作的标量处理器，包括可操作地连接到标量处理器的多个独立功能单元，用于在矢量指令上操作的矢量处理器，包括多个独立的功能单元，连接到向量处理器，以及指令控制机制，用于从指令高速缓存取出标量和向量指令，并控制标量和向量处理器中的这些指令的操作。指令控制机制旨在通过保持基本上填充有最小数量的间隙的多个管线来增强标量/向量处理器的性能。

6. 发明授权

US5544337A Vector processor having registers for control by vector resisters 失效
标题翻译：矢量处理器具有寄存器用于通过矢量寄存器进行控制
公开(公告)号：US5544337A
公开(公告)日：1996-08-06
申请号：US487952
申请日：1995-06-07
申请人： Douglas R. Beard , Andrew E. Phelps , Michael A. Woodmansee , Richard G. Blewett , Jeffrey A. Lohman , Alexander A. Silbey , George A. Spix , Frederick J. Simmons , Don A. Van Dyke
发明人： Douglas R. Beard , Andrew E. Phelps , Michael A. Woodmansee , Richard G. Blewett , Jeffrey A. Lohman , Alexander A. Silbey , George A. Spix , Frederick J. Simmons , Don A. Van Dyke
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/173 , G06F15/78 , G06F15/80
CPC分类号： G06F9/3013 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/30094 , G06F9/30101 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3816 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3846 , G06F9/3857 , G06F9/3875 , G06F9/3885
摘要： The present invention is an improved high performance scalar/vector processor. In the preferred embodiment, the scalar/vector processor is used in a multiprocessor system. The scalar/vector processor is comprised of a scalar processor for operating on scalar and logical instructions, including a plurality of independent functional units operably connected to the scalar processor, a vector processor for operating on vector instructions, including a plurality of independent functional units operably connected to the vector processor, and an instruction control mechanism for fetching both the scalar and vector instructions from an instruction cache and controlling the operation of those instructions in both the scalar and vector processor. The instruction control mechanism is designed to enhance the performance of the scalar/vector processor by keeping a multiplicity of pipelines substantially filled with a minimum number of gaps.
摘要翻译：本发明是一种改进的高性能标量/向量处理器。在优选实施例中，在多处理器系统中使用标量/向量处理器。标量/矢量处理器包括用于对标量和逻辑指令进行操作的标量处理器，包括可操作地连接到标量处理器的多个独立功能单元，用于在矢量指令上操作的矢量处理器，包括多个独立的功能单元，连接到向量处理器，以及指令控制机制，用于从指令高速缓存取出标量和向量指令，并控制标量和向量处理器中的这些指令的操作。指令控制机制旨在通过保持基本上填充有最小数量的间隙的多个管线来增强标量/向量处理器的性能。

7. 发明授权

US5253359A Control and maintenance subsystem network for use with a multiprocessor computer system 失效
标题翻译：用于多处理器计算机系统的控制和维护子系统网络
公开(公告)号：US5253359A
公开(公告)日：1993-10-12
申请号：US535901
申请日：1990-06-11
申请人： George A. Spix , Glen L. Collier , G. Joseph Throop , David L. Clounch , Cris J. Rhea , Douglas R. Beard
发明人： George A. Spix , Glen L. Collier , G. Joseph Throop , David L. Clounch , Cris J. Rhea , Douglas R. Beard
IPC分类号： G06F11/20 , G06F11/22 , G06F11/273 , G06F11/34 , H04L29/00 , G06F11/00
CPC分类号： G06F11/2041 , G06F11/2736 , H04L29/00 , G06F11/2046 , G06F11/22 , G06F11/2205 , G06F11/2294 , G06F11/3476
摘要： Methods and apparatus for a maintenance and control system for sensing and controlling the numerous sections of a highly parallel multiprocessor system. The control and maintenance system communicates with all processors, all peripheral systems, all user interfaces to the multiprocessor system, a system console, and the power and environmental control subsystems.
摘要翻译：用于感测和控制高度并行多处理器系统的许多部分的维护和控制系统的方法和装置。控制和维护系统与所有处理器，所有外设系统，与多处理器系统的所有用户界面，系统控制台以及电源和环境控制子系统进行通信。

8. 发明授权

US5239629A Dedicated centralized signaling mechanism for selectively signaling devices in a multiprocessor system 失效
标题翻译：专用集中式信令机制，用于在多处理器系统中选择性地发信号通知设备
公开(公告)号：US5239629A
公开(公告)日：1993-08-24
申请号：US536192
申请日：1990-06-11
申请人： Edward C. Miller , George A. Spix , Anthony R. Schooler , Douglas R. Beard , Alexander A. Silbey , Andrew E. Phelps
发明人： Edward C. Miller , George A. Spix , Anthony R. Schooler , Douglas R. Beard , Alexander A. Silbey , Andrew E. Phelps
IPC分类号： G06F13/14 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/16 , G06F15/173 , G06F15/177 , G06F15/78 , G06F15/80
CPC分类号： G06F15/17375 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/30094 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： A signaling mechanism for sending and receiving signals to and from any one of all of a plurality of devices, including peripheral controllers and processors, in a multiprocessor system. The signaling mechanism includes two switches, a first switch routing a signal command generated by the device to a signal dispatch logic and a second switch for receiving signals generated by the signal dispatch logic and routing the signals to the selected device. The signal dispatch logic receiving the signal command, decodes the destination select value and generates a signal to be sent to the selected device. The signal command includes a destination select value representing a device selectably determined by the device. The signaling mechanism also includes an arbitration mechanism connected to the signal dispatch logic and the first switch for resolving simultaneous conflicting signal commands issued by two or more devices. The signal generated by the signal dispatch logic may include a plurality of bits representing one or more types of predefined signals to be acted upon by the device.
摘要翻译：一种用于在多处理器系统中向包括外围控制器和处理器的多个设备中的任何一个设备发送和接收信号的信令机制。信令机制包括两个交换机，第一交换机将由设备产生的信号命令路由到信号调度逻辑，以及第二开关，用于接收由信号调度逻辑产生的信号并将信号路由到所选设备。信号调度逻辑接收信号命令，对目的地选择值进行解码，并生成要发送给所选设备的信号。信号命令包括表示由该设备可选地确定的设备的目的地选择值。信令机制还包括连接到信号调度逻辑的仲裁机制和用于解决由两个或更多个设备发出的同时冲突的信号命令的第一交换机。由信号调度逻辑产生的信号可以包括表示一个或多个类型的预定义信号的多个位，以被该设备作用。

9. 发明授权

US5175862A Method and apparatus for a special purpose arithmetic boolean unit 失效
标题翻译：专用算术布尔单位的方法和装置
公开(公告)号：US5175862A
公开(公告)日：1992-12-29
申请号：US536197
申请日：1990-06-11
申请人： Andrew E. Phelps , Douglas R. Beard , Michael A. Woodsmansee
发明人： Andrew E. Phelps , Douglas R. Beard , Michael A. Woodsmansee
IPC分类号： G06F7/38 , G06F7/00 , G06F7/483 , G06F7/527 , G06F7/53 , G06F9/30 , G06F9/302 , G06F9/308 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/173 , G06F15/78 , G06F15/80 , G06F17/16
CPC分类号： G06F15/8053 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F17/16 , G06F7/00 , G06F8/433 , G06F8/45 , G06F9/3001 , G06F9/30018 , G06F9/30021 , G06F9/30029 , G06F9/30094 , G06F9/3013 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3885
摘要： A special purpose arithmetic boolean unit is capable of performing extremely parallel bit-level boolean operations, particularly bit matrix manipulations. The special purpose arithmetic boolean unit is especially adapted for use in traditional vector processors, thereby enabling a vector processor to effectively solve extremely parallel MIMD or SIMD boolean problems without requiring an array processor or massively parallel supercomputer.
摘要翻译：特殊用途算术布尔单元能够执行极其平行的位级布尔运算，特别是位矩阵操作。专用算术布尔单元特别适用于传统的矢量处理器，从而使矢量处理器能够有效地解决非常平行的MIMD或SIMD布尔问题，而无需阵列处理器或大规模并行超级计算机。

10. 发明授权

US06351797B1 Translation look-aside buffer for storing region configuration bits and method of operation 有权
标题翻译：用于存储区域配置位的翻译后备缓冲区和操作方法
公开(公告)号：US06351797B1
公开(公告)日：2002-02-26
申请号：US09192122
申请日：1998-11-13
申请人： Douglas R. Beard, Sr. , Darren Bensley , Daniel W. Green
发明人： Douglas R. Beard, Sr. , Darren Bensley , Daniel W. Green
IPC分类号： G06F1210
CPC分类号： G06F12/1027
摘要： There is disclosed, for use in an x86-compatible processor, a translation look-aside buffer (TLB) that stores region configuration bits (or attribute bits) associated with each physical address stored in the TLB and that makes the region configuration bits available at the same time that the physical address is generated/translated by the TLB. The TLB comprises: 1) a tag array capable of storing an untranslated address in one of N tag entries in the tag array; 2) a data array capable of storing a translated physical address corresponding to the untranslated address in one of N data entries in the data array; and 3) a region configuration array capable of storing region configuration bits associated with the translated physical address in one of N region configuration entries in the region configuration array.
摘要翻译：公开了在x86兼容处理器中使用的翻译后备缓冲器（TLB），其存储与存储在TLB中的每个物理地址相关联的区域配置位（或属性位），并使区域配置位可用于物理地址由TLB生成/翻译的同时。 TLB包括：1）能够在标签阵列中的N个标签条目之一中存储非翻译地址的标签阵列; 2）数据阵列，其能够将对应于未翻译地址的翻译物理地址存储在数据阵列中的N个数据条目之一中; 以及3）区域配置阵列，其能够在所述区域配置阵列中的N个区域配置条目之一中存储与所转换的物理地址相关联的区域配置位。

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