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1. 发明授权

US08934311B2 Semiconductor memory device capable of screening a weak bit and repairing the same 有权
标题翻译：半导体存储器能够筛选弱点并进行修复
公开(公告)号：US08934311B2
公开(公告)日：2015-01-13
申请号：US13604308
申请日：2012-09-05
申请人： Hak-soo Yu , Uk-song Kang , Chul-woo Park , Joo-sun Choi , Hong-Sun Hwang
发明人： Hak-soo Yu , Uk-song Kang , Chul-woo Park , Joo-sun Choi , Hong-Sun Hwang
IPC分类号： G11C29/44 , G11C29/50 , G11C29/00 , G11C29/04 , G11C11/41
CPC分类号： G11C29/50 , G11C11/41 , G11C29/783 , G11C2029/0409 , G11C2029/4402
摘要： A semiconductor device includes a first memory region including a plurality of memory cells; a test unit configured to test the first memory region, and detect a weak bit from among the plurality of memory cells; and a second memory region configured to store a weak bit address (WBA) of the first memory region, and data intended to be stored in the weak bit, wherein the first memory region and the second memory region include different types of memory cells.
摘要翻译：半导体器件包括包括多个存储单元的第一存储区域; 测试单元，被配置为测试所述第一存储器区域，并且从所述多个存储器单元中检测弱位; 以及第二存储器区域，被配置为存储所述第一存储器区域的弱位地址（WBA）以及要存储在所述弱位中的数据，其中所述第一存储器区域和所述第二存储器区域包括不同类型的存储器单元。

2. 发明授权

US08693269B2 Memory device for managing timing parameters 有权
标题翻译：用于管理时序参数的存储器
公开(公告)号：US08693269B2
公开(公告)日：2014-04-08
申请号：US13569636
申请日：2012-08-08
申请人： Uk-song Kang , Chul-woo Park , Hak-soo Yu , Hong-sun Hwang
发明人： Uk-song Kang , Chul-woo Park , Hak-soo Yu , Hong-sun Hwang
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G11C7/1009 , G11C11/40611 , G11C11/4093
摘要： A method of performing write operations in a memory device including a plurality of bank is performed. Each bank includes two or more sub-banks including at least a first sub-bank and a second sub-bank. The method comprises: performing a first row cycle for writing to a first word line of the first sub-bank, the first row cycle including a plurality of first sub-periods, each sub-period for performing a particular action; and performing a second row cycle for writing to a first word line of the second sub-bank, the second row cycle including a plurality of second sub-periods of the same type as the plurality of first sub-periods. The first row cycle overlaps with the second row cycle, and a first type sub-period of the first sub-periods overlaps with a second type sub-period of the second sub-periods, the first type and second type being different types.
摘要翻译：执行在包括多个存储体的存储器件中执行写入操作的方法。每个银行包括至少包括第一子银行和第二子银行的两个或多个子行。该方法包括：执行第一行周期以写入第一子行的第一字线，第一行周期包括多个第一子周期，用于执行特定动作的每个子周期; 以及执行第二行周期以写入所述第二子行的第一字线，所述第二行周期包括与所述多个第一子周期相同类型的多个第二子周期。第一行周期与第二行周期重叠，第一子周期的第一类型子周期与第二子周期的第二类型子周期重叠，第一类型和第二类型是不同类型。

3. 发明申请

US20150248329A1 Method and Apparatus for Refreshing and Data Scrubbing Memory Device 审中-公开
标题翻译：刷新和数据清理存储器件的方法和装置
公开(公告)号：US20150248329A1
公开(公告)日：2015-09-03
申请号：US14699201
申请日：2015-04-29
申请人： Uk-song Kang , Hak-soo Yu , Chul-woo Park
发明人： Uk-song Kang , Hak-soo Yu , Chul-woo Park
IPC分类号： G06F11/10 , G11C29/52 , G06F3/06 , G11C11/406
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/0644 , G06F3/0652 , G06F3/0679 , G06F11/106 , G11C11/40 , G11C11/406 , G11C11/40611 , G11C11/40618 , G11C11/40622 , G11C29/52 , G11C2029/0409 , G11C2029/0411
摘要： At least one refresh without scrubbing is performed on a corresponding portion of the memory device with a first frequency. In addition, at least one refresh with scrubbing is performed on a corresponding portion of the memory device with a second frequency less than the first frequency. Accordingly, refresh operations with data scrubbing are performed to prevent data error accumulation. Furthermore, refresh operations without data scrubbing are also performed to reduce undue power consumption from the data scrubbing.
摘要翻译：在具有第一频率的存储器件的相应部分上执行至少一次不进行擦洗的刷新。此外，具有小于第一频率的第二频率对存储器件的相应部分执行至少一次刷洗刷新。因此，执行具有数据擦除的刷新操作以防止数据错误累积。此外，还执行没有数据擦除的刷新操作，以减少数据擦除的不必要的功耗。

4. 发明授权

US08638621B2 Semiconductor memory device having a hierarchical bit line scheme 有权
标题翻译：具有分层位线方案的半导体存储器件
公开(公告)号：US08638621B2
公开(公告)日：2014-01-28
申请号：US13413938
申请日：2012-03-07
申请人： Jong-pil Son , Chul-woo Park , Young-hyun Jun , Hong-sun Hwang , Hak-soo Yu
发明人： Jong-pil Son , Chul-woo Park , Young-hyun Jun , Hong-sun Hwang , Hak-soo Yu
IPC分类号： G11C7/00 , G11C11/419
CPC分类号： G11C11/419 , G11C11/4091 , G11C11/4094 , G11C11/4097
摘要： A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell.
摘要翻译：一种半导体存储器件，包括连接到存储单元的位线和被配置为响应于位线的电压电平驱动全局位线的电压电平的读出放大器。感测放大器提供与存储在存储器单元中的数据互补的数据到全局位线，并且在存储器单元的有效操作期间将全局位线的互补数据提供给存储单元。

5. 发明授权

US08553445B2 Semiconductor memory device having stacked structure including resistor-switched based logic circuit and method of manufacturing the same 有权
标题翻译：具有堆叠结构的半导体存储器件，包括基于电阻开关的逻辑电路及其制造方法
公开(公告)号：US08553445B2
公开(公告)日：2013-10-08
申请号：US13224410
申请日：2011-09-02
申请人： In-gyu Baek , Hong-sun Hwang , Hak-soo Yu , Chul-woo Park
发明人： In-gyu Baek , Hong-sun Hwang , Hak-soo Yu , Chul-woo Park
IPC分类号： G11C11/00
CPC分类号： H01L45/147 , G11C5/025 , G11C13/0002 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/14
摘要： Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.
摘要翻译：具有包括基于电阻器开关的逻辑电路的堆叠结构的半导体存储器件。半导体存储器件包括第一导线，其包括第一线部分和第二线部分，其中第一线部分和第二线部分通过布置在第一线部分和第二线部分之间的中间区域彼此电分离，连接到第一线部分并存储数据的第一可变电阻材料膜和控制第一线部分和第二线部分之间的电连接的第二可变电阻材料膜。

6. 发明申请

US20120230139A1 SEMICONDUCTOR MEMORY DEVICE HAVING A HIERARCHICAL BIT LINE SCHEME 有权
标题翻译：具有分层位线方案的半导体存储器件
公开(公告)号：US20120230139A1
公开(公告)日：2012-09-13
申请号：US13413938
申请日：2012-03-07
申请人： Jong-pil Son , Chul-woo Park , Young-hyun Jun , Hong-sun Hwang , Hak-soo Yu
发明人： Jong-pil Son , Chul-woo Park , Young-hyun Jun , Hong-sun Hwang , Hak-soo Yu
IPC分类号： G11C7/06 , G11C7/12
CPC分类号： G11C11/419 , G11C11/4091 , G11C11/4094 , G11C11/4097
摘要： A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell.
摘要翻译：一种半导体存储器件，包括连接到存储单元的位线和被配置为响应于位线的电压电平驱动全局位线的电压电平的读出放大器。感测放大器提供与存储在存储器单元中的数据互补的数据到全局位线，并且在存储器单元的有效操作期间将全局位线的互补数据提供给存储单元。

7. 发明授权

US08705297B2 Semiconductor memory devices and semiconductor memory systems 有权
标题翻译：半导体存储器件和半导体存储器系统
公开(公告)号：US08705297B2
公开(公告)日：2014-04-22
申请号：US13282830
申请日：2011-10-27
申请人： Sua Kim , Chul-woo Park , Hong-sun Hwang , Hak-soo Yu
发明人： Sua Kim , Chul-woo Park , Hong-sun Hwang , Hak-soo Yu
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/06 , G11C2207/002 , G11C2207/005
摘要： A semiconductor memory device includes at least one memory cell block and at least one connection unit. The at least one memory cell block has a first region including at least one first memory cell connected to a first bit line, and a second region including at least one second memory cell connected to a second bit line. The at least one connection unit is configured to selectively connect the first bit line to a corresponding bit line sense amplifier based on a first control signal, and configured to selectively connect the second bit line to the corresponding bit line sense amplifier via a corresponding global bit line based on a second control signal.
摘要翻译：半导体存储器件包括至少一个存储单元块和至少一个连接单元。所述至少一个存储单元块具有包括连接到第一位线的至少一个第一存储单元的第一区域和包括连接到第二位线的至少一个第二存储器单元的第二区域。所述至少一个连接单元被配置为基于第一控制信号选择性地将第一位线连接到对应的位线读出放大器，并且被配置为经由对应的全局位选择性地将第二位线连接到对应的位线读出放大器基于第二控制信号。

8. 发明授权

US08588017B2 Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same 有权
标题翻译：用于执行DRAM刷新操作的存储器电路，系统和模块及其操作方法
公开(公告)号：US08588017B2
公开(公告)日：2013-11-19
申请号：US13236972
申请日：2011-09-20
申请人： Chul-woo Park , Young-hyun Jun , Joo-sun Choi , Hong-sun Hwang
发明人： Chul-woo Park , Young-hyun Jun , Joo-sun Choi , Hong-sun Hwang
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G06F2213/0038 , G11C11/40618 , G11C11/40622 , G11C11/40626 , G11C2211/4062
摘要： A memory module can include a plurality of dynamic memory devices that each can include a dynamic memory cell array with respective regions therein, where the plurality of dynamic memory devices can be configured to operate the respective regions responsive to a command. A DRAM management unit can be on the module and coupled to the plurality of dynamic memory devices, and can include a memory device operational parameter storage circuit that is configured to store memory device operational parameters for the respective regions to affect operation of the respective regions responsive to the command.
摘要翻译：存储器模块可以包括多个动态存储器设备，每个动态存储器设备可以包括其中具有其中各自区域的动态存储器单元阵列，其中多个动态存储器设备可被配置为响应于命令操作相应的区域。 DRAM管理单元可以在模块上并且耦合到多个动态存储器设备，并且可以包括存储器设备操作参数存储电路，其被配置为存储用于各个区域的存储器设备操作参数以影响相应区域的操作命令。

9. 发明申请

US20130051114A1 DATA READ CIRCUIT, A NON-VOLATILE MEMORY DEVICE HAVING THE SAME, AND A METHOD OF READING DATA FROM THE NON-VOLATILE MEMORY DEVICE 有权
标题翻译：数据读取电路，具有该数据读取电路的非易失性存储器件以及从非易失性存储器件读取数据的方法
公开(公告)号：US20130051114A1
公开(公告)日：2013-02-28
申请号：US13562871
申请日：2012-07-31
申请人： Chan-kyung Kim , Hong-sun Hwang , Chul-woo Park , Sang-beom Kang , Hyung-rok Oh
发明人： Chan-kyung Kim , Hong-sun Hwang , Chul-woo Park , Sang-beom Kang , Hyung-rok Oh
IPC分类号： G11C5/14 , G11C11/00 , G11C11/16 , G11C11/22
CPC分类号： G11C13/0033 , G11C7/062 , G11C7/067 , G11C7/08 , G11C7/14 , G11C11/1673 , G11C11/1693 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0061 , G11C2013/0042 , G11C2013/0054
摘要： A non-volatile memory device including a cell array, which includes a plurality of memory cells, and a sense amplification circuit. The sense amplification circuit is configured to receive a data voltage of a memory cell, a first reference voltage and a second reference voltage during a data read operation of the memory cell, generate differential output signals based on a voltage level difference between the data voltage and the first and second reference voltages, and output the differential output signals as data read from the memory cell.
摘要翻译：包括具有多个存储单元的单元阵列和读出放大电路的非易失性存储器件。感测放大电路被配置为在存储单元的数据读取操作期间接收存储单元的数据电压，第一参考电压和第二参考电压，基于数据电压和数据电压之间的电压电平差产生差分输出信号第一和第二参考电压，并将差分输出信号作为从存储单元读取的数据输出。

10. 发明授权

US09042152B2 Data read circuit, a non-volatile memory device having the same, and a method of reading data from the non-volatile memory device 有权
标题翻译：数据读取电路，具有该数据读出电路的非易失性存储器件以及从非易失性存储器件读取数据的方法
公开(公告)号：US09042152B2
公开(公告)日：2015-05-26
申请号：US13562871
申请日：2012-07-31
申请人： Chan-kyung Kim , Hong-sun Hwang , Chul-woo Park , Sang-beom Kang , Hyung-rok Oh
发明人： Chan-kyung Kim , Hong-sun Hwang , Chul-woo Park , Sang-beom Kang , Hyung-rok Oh
IPC分类号： G11C11/00 , G11C13/00 , G11C11/16 , G11C7/06 , G11C7/08 , G11C7/14 , G11C11/56
CPC分类号： G11C13/0033 , G11C7/062 , G11C7/067 , G11C7/08 , G11C7/14 , G11C11/1673 , G11C11/1693 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0061 , G11C2013/0042 , G11C2013/0054
摘要： A non-volatile memory device including a cell array, which includes a plurality of memory cells, and a sense amplification circuit. The sense amplification circuit is configured to receive a data voltage of a memory cell, a first reference voltage and a second reference voltage during a data read operation of the memory cell, generate differential output signals based on a voltage level difference between the data voltage and the first and second reference voltages, and output the differential output signals as data read from the memory cell.
摘要翻译：包括具有多个存储单元的单元阵列和读出放大电路的非易失性存储器件。感测放大电路被配置为在存储单元的数据读取操作期间接收存储单元的数据电压，第一参考电压和第二参考电压，基于数据电压和数据电压之间的电压电平差产生差分输出信号第一和第二参考电压，并将差分输出信号作为从存储单元读取的数据输出。

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