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1. 发明授权

US08929496B2 Receiver with enhanced clock and data recovery 有权
标题翻译：接收机具有增强的时钟和数据恢复功能
公开(公告)号：US08929496B2
公开(公告)日：2015-01-06
申请号：US12812720
申请日：2009-01-30
申请人： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
发明人： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
IPC分类号： H04L7/00 , H04L7/033 , H04L25/06 , H04L25/03 , H04L27/00
CPC分类号： H04L7/0016 , G06Q10/06312 , G06Q10/103 , H04L7/0004 , H04L7/0062 , H04L7/033 , H04L7/0331 , H04L7/0334 , H04L25/062 , H04L2025/0349 , H04L2027/004 , H04L2027/0067 , H04L2027/0069
摘要： A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
摘要翻译：接收机设备利用基于边缘的时钟和数据恢复来实现增强的数据接收，例如使用闪存模数转换器架构。在示例实施例中，设备实现第一相位调节控制回路，例如，一个爆炸相位检测器，其通过调整边沿时钟的相位来检测数据转换以便在边缘采样器的最优边缘时间调整采样的采样器。该循环可以通过调整诸如闪存ADC的数据采样器的数据时钟的相位来进一步调整接收数据间隔中的采样以实现最佳数据接收。该装置还可以实现具有例如波特率相位检测器的第二相位调整控制回路，波形率相位检测器检测数据间隔以便在数据采样器的最佳数据时间进一步调整采样。

2. 发明申请

US20100289544A1 Receiver With Enhanced Clock And Data Recovery 有权
标题翻译：接收机具有增强的时钟和数据恢复功能
公开(公告)号：US20100289544A1
公开(公告)日：2010-11-18
申请号：US12812720
申请日：2009-01-30
申请人： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
发明人： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
IPC分类号： H03L7/06
CPC分类号： H04L7/0016 , G06Q10/06312 , G06Q10/103 , H04L7/0004 , H04L7/0062 , H04L7/033 , H04L7/0331 , H04L7/0334 , H04L25/062 , H04L2025/0349 , H04L2027/004 , H04L2027/0067 , H04L2027/0069
摘要： A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
摘要翻译：接收机设备利用基于边缘的时钟和数据恢复来实现增强的数据接收，例如使用闪存模数转换器架构。在示例实施例中，设备实现第一相位调节控制回路，例如，一个爆炸相位检测器，其通过调整边沿时钟的相位来检测数据转换以便在边缘采样器的最优边缘时间调整采样的采样器。该循环可以通过调整诸如闪存ADC的数据采样器的数据时钟的相位来进一步调整接收数据间隔中的采样以实现最佳数据接收。该装置还可以实现具有例如波特率相位检测器的第二相位调整控制回路，波形率相位检测器检测数据间隔以便在数据采样器的最佳数据时间进一步调整采样。

3. 发明授权

US08289032B2 Integrated circuit having receiver jitter tolerance (“JTOL”) measurement 有权
标题翻译：具有接收机抖动容限（JTOL）测量的集成电路
公开(公告)号：US08289032B2
公开(公告)日：2012-10-16
申请号：US12529320
申请日：2008-03-19
申请人： Hae-Chang Lee , Jaeha Kim , Brian Leibowitz
发明人： Hae-Chang Lee , Jaeha Kim , Brian Leibowitz
IPC分类号： G01R29/26
CPC分类号： G01R29/26 , G01R31/31709 , G01R31/31725
摘要： An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
摘要翻译：能够进行片上抖动容限测量的集成电路包括：抖动发生器电路，用于产生被注入到至少一个时钟信号中的受控量的抖动;以及接收电路，用于根据至少一个时钟信号对输入信号进行采样。从接收器输出的采样数据值用于评估集成电路的抖动容限。

4. 发明申请

US20100097071A1 Integrated Circuit Having Receiver Jitter Tolerance ("JTOL") Measurement 有权
标题翻译：具有接收机抖动容限（“JTOL”）测量的集成电路
公开(公告)号：US20100097071A1
公开(公告)日：2010-04-22
申请号：US12529320
申请日：2008-03-19
申请人： Hae-Chang Lee , Jaeha Kim , Brian Leibowitz
发明人： Hae-Chang Lee , Jaeha Kim , Brian Leibowitz
IPC分类号： G01R31/02 , G06F1/04 , G06F11/00
CPC分类号： G01R29/26 , G01R31/31709 , G01R31/31725
摘要： An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
摘要翻译：能够进行片上抖动容限测量的集成电路包括：抖动发生器电路，用于产生被注入到至少一个时钟信号中的受控量的抖动;以及接收电路，用于根据至少一个时钟信号对输入信号进行采样。从接收器输出的采样数据值用于评估集成电路的抖动容限。

5. 发明授权

US09423441B2 Integrated circuit having receiver jitter tolerance (“JTOL”) measurement 有权
标题翻译：具有接收机抖动容限（“JTOL”）测量的集成电路
公开(公告)号：US09423441B2
公开(公告)日：2016-08-23
申请号：US13621783
申请日：2012-09-17
申请人： Hae-Chang Lee , Jaeha Kim , Brian Leibowitz
发明人： Hae-Chang Lee , Jaeha Kim , Brian Leibowitz
IPC分类号： G01R29/26 , G01R31/317
CPC分类号： G01R29/26 , G01R31/31709 , G01R31/31725
摘要： An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
摘要翻译：能够进行片上抖动容限测量的集成电路包括：抖动发生器电路，用于产生被注入到至少一个时钟信号中的受控量的抖动;以及接收电路，用于根据至少一个时钟信号对输入信号进行采样。从接收器输出的采样数据值用于评估集成电路的抖动容限。

6. 发明申请

US20130093433A1 Integrated Circuit Having Receiver Jitter Tolerance ("JTOL") Measurement 有权
标题翻译：具有接收机抖动容限（“JTOL”）测量的集成电路
公开(公告)号：US20130093433A1
公开(公告)日：2013-04-18
申请号：US13621783
申请日：2012-09-17
申请人： Hae-Chang Lee , Jaeha Kim , Brian Leibowitz
发明人： Hae-Chang Lee , Jaeha Kim , Brian Leibowitz
IPC分类号： G01R29/26
CPC分类号： G01R29/26 , G01R31/31709 , G01R31/31725
摘要： An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
摘要翻译：能够进行片上抖动容限测量的集成电路包括：抖动发生器电路，用于产生被注入到至少一个时钟信号中的受控量的抖动;以及接收电路，用于根据至少一个时钟信号对输入信号进行采样。从接收器输出的采样数据值用于评估集成电路的抖动容限。

7. 发明授权

US08548110B2 Receiver with clock recovery circuit and adaptive sample and equalizer timing 有权
公开(公告)号：US08548110B2
公开(公告)日：2013-10-01
申请号：US12523042
申请日：2007-12-13
申请人： Qi Lin , Brian Leibowitz , Hae-Chang Lee , Jihong Ren , Kyung Suk Oh , Jared Zerbe
发明人： Qi Lin , Brian Leibowitz , Hae-Chang Lee , Jihong Ren , Kyung Suk Oh , Jared Zerbe
IPC分类号： H04L7/00
CPC分类号： H04L25/03254 , H04L7/0025 , H04L7/0054 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/03057 , H04L25/03885 , H04L43/028 , H04L2025/03617
摘要： A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

8. 发明申请

US20120218001A1 Techniques for Phase Detection 审中-公开
标题翻译：相位检测技术
公开(公告)号：US20120218001A1
公开(公告)日：2012-08-30
申请号：US13505714
申请日：2010-10-31
申请人： Brian Leibowitz , Hae-Chang Lee , Farshid Aryanfar , Kun-Yung Chang , Jie Shen
发明人： Brian Leibowitz , Hae-Chang Lee , Farshid Aryanfar , Kun-Yung Chang , Jie Shen
IPC分类号： H03D13/00
CPC分类号： H03D13/00 , H03L7/08 , H03L7/0814 , H03L7/0816 , H03L7/085
摘要： A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase.
摘要翻译：相位检测电路可以包括两个相位检测器，每个相位检测器响应于同相对准的输入信号而产生非零输出。输入信号基于两个周期信号。相位检测电路从另一相位检测器的输出信号中减去一相位检测器的输出信号，当周期信号同相时产生具有零值的信号。或者，相位检测器产生指示周期信号之间的相位差的相位比较信号。相位比较信号响应于相位检测器的相位输入信号具有非零值。输入信号基于周期信号。输出电路接收相位比较信号，并响应于同相对齐的周期信号产生具有零值的输出。

9. 发明申请

US20100135378A1 Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing 有权
标题翻译：具有时钟恢复电路和自适应采样和均衡器时序的接收器
公开(公告)号：US20100135378A1
公开(公告)日：2010-06-03
申请号：US12523042
申请日：2007-12-13
申请人： Qi Lin , Brian Leibowitz , Hae-Chang Lee , Jihong Ren , Kyung Suk Oh , Jared Zerbe
发明人： Qi Lin , Brian Leibowitz , Hae-Chang Lee , Jihong Ren , Kyung Suk Oh , Jared Zerbe
IPC分类号： H04L27/01 , H04L7/00
CPC分类号： H04L25/03254 , H04L7/0025 , H04L7/0054 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/03057 , H04L25/03885 , H04L43/028 , H04L2025/03617
摘要： A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
摘要翻译：接收器配备有自适应相位偏移控制器和相关联的定时校准电路，其一起移动数据采样器和数字均衡器的定时。样本和均衡器定时被转移到具有相对于当前符号的残余符号间干扰（ISI）能量较少的位置。可以使用信号质量的测量（诸如接收机比特错误率或滤波器抽头值的比较）来计算移位的位置，以优化数据恢复的定时。

10. 发明授权

US08618869B2 Fast power-on bias circuit 有权
标题翻译：快速上电偏置电路
公开(公告)号：US08618869B2
公开(公告)日：2013-12-31
申请号：US13341483
申请日：2011-12-30
申请人： Wayne Dettloff , John Wilson , Lei Luo , Brian Leibowitz , Jared Zerbe , Pravin Kumar Venkatesan
发明人： Wayne Dettloff , John Wilson , Lei Luo , Brian Leibowitz , Jared Zerbe , Pravin Kumar Venkatesan
IPC分类号： G05F1/10
CPC分类号： G06F1/26 , G06F1/3203 , H03K17/223
摘要： Conventional bias circuits exhibit a number of limitations, including the time required to power-up a bias circuit following a low-power state. Large current surges in the supply network induce ringing, further complicating a power-up process. Example embodiments reduce power-up time and minimize current surges in the supply by selectively charging and discharging capacitance to the circuit during power-up and power-down of the bias circuit.
摘要翻译：常规偏置电路表现出许多限制，包括在低功率状态之后上电偏置电路所需的时间。供电网络中的大电流浪涌引起振铃，进一步使上电过程复杂化。示例性实施例通过在偏置电路的加电和掉电期间选择性地对电路充电和放电电容来减小上电时间并最小化电源中的电流浪涌。

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