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1. 发明专利

JP2010020880A Programming method of nonvolatile memory device 审中-公开
标题翻译：非易失性存储器件的编程方法
公开(公告)号：JP2010020880A
公开(公告)日：2010-01-28
申请号：JP2009015711
申请日：2009-01-27
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： WANG JONG HYUN
IPC分类号： G11C16/02
CPC分类号： G11C16/10
摘要： PROBLEM TO BE SOLVED: To provide a programming method of a nonvolatile memory device which reduces programming time while applying dummy program pulses. SOLUTION: The programming method of the nonvolatile memory device includes steps of: performing program operation by applying a dummy program pulses having a pulse width wider than that of a program start pulse; performing a program operation by applying the program start pulses; and verifying whether the program is completed by the program operation. The programming method of the nonvolatile memory device further includes steps of: performing a program operation by applying stepwise dummy program pulses having a second pulse width and increasing the program pulses by a second step voltage; performing a program operation by applying program pulses having a first step voltage and a first pulse width; and verifying whether the program is completed by the program operation. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种在应用虚拟编程脉冲的同时减少编程时间的非易失性存储器件的编程方法。解决方案：非易失性存储器件的编程方法包括以下步骤：通过施加具有比程序起始脉冲宽的脉冲宽度的虚拟编程脉冲来执行编程操作; 通过应用程序开始脉冲执行编程操作; 并通过程序操作来验证程序是否完成。非易失性存储器件的编程方法还包括以下步骤：通过施加具有第二脉冲宽度的逐步虚拟编程脉冲并通过第二步进电压来增加编程脉冲来执行编程操作; 通过应用具有第一阶梯电压和第一脉冲宽度的编程脉冲来执行编程操作; 并通过程序操作来验证程序是否完成。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2008204591A Read-out method of memory element 审中-公开
标题翻译：存储元件的读出方法
公开(公告)号：JP2008204591A
公开(公告)日：2008-09-04
申请号：JP2007186799
申请日：2007-07-18
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： WANG JONG HYUN , CHUNG JUN SEOP , JOO SEOK JIN
IPC分类号： G11C16/02 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/28 , G06F11/1072 , G11C11/5642 , G11C29/00
摘要： PROBLEM TO BE SOLVED: To provide a read-out method of a memory element by which cell information can be read out accurately even when cell voltage is varied due to a cell keeping property in, especially, a multilevel cell (MLC).
SOLUTION: The read-out method of the memory element including the multi-level cell, includes a process for reading out data by a first read-out instruction, a process for judging propriety of error correction of the read out data, a process for performing read-out of data by a second read-out instruction when error correction is judged as hard, a process for judging propriety of error correction of the read out data based on the second read-out instruction, and a process for reading out data by the Nth (N≥3, integer) read-out instruction when error correction is judged as hard.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种存储元件的读出方法，即使当由于特别是多电平单元（MLC）中的单元保持特性而使单元电压变化时，也能准确地读出单元信息，。解决方案：包括多级单元的存储元件的读出方法包括通过第一读出指令读出数据的处理，用于判断读出数据的纠错的适当性的处理，当错误校正被判断为硬时，通过第二读出指令执行读出数据的处理，基于第二读出指令判断读出数据的纠错的适当性的处理，以及当判断错误校正时，通过第N（N≥3，整数）读出指令读出数据。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2009151910A Page buffer of volatile memory device and its programming method 审中-公开
标题翻译：挥发性存储器件的缓冲器及其编程方法
公开(公告)号：JP2009151910A
公开(公告)日：2009-07-09
申请号：JP2008148977
申请日：2008-06-06
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： YANG CHANG WON , WANG JONG HYUN , PARK SE CHUN
IPC分类号： G11C16/06 , G11C16/02
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/10 , G11C2211/5621 , G11C2216/14
摘要： PROBLEM TO BE SOLVED: To classify a register in charge of an upper side memory and a register in charge of a lower side memory by locating a page buffer to a center part of a plane according to the necessity. SOLUTION: The page buffer includes: a first register for provisionally storing data programming to a cell which is included in a first memory cell block group, or reading and storing data of an applicable memory cell; a second register for provisionally storing data programming to a cell which is included in a second memory cell block group, or reading and storing the data of the applicable memory cell; and a data input/output section for making specific data input to the first and second registers or output the data stored in the first and second registers to the outside. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：根据需要，通过将页面缓冲器定位到平面的中心部分来分类负责上侧存储器的寄存器和下侧存储器的寄存器。页面缓冲器包括：用于临时存储数据编程到第一存储器单元块组中的单元的第一寄存器，或读取和存储适用的存储单元的数据; 第二寄存器，用于将数据编程临时存储到包括在第二存储单元块组中的单元，或读取和存储适用的存储单元的数据; 以及用于使特定数据输入到第一和第二寄存器或将存储在第一和第二寄存器中的数据输出到外部的数据输入/输出部分。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2008165953A Nonvolatile memory device and multilevel cell programming method using the same 审中-公开
标题翻译：非易失性存储器件和使用其的多单元格编程方法
公开(公告)号：JP2008165953A
公开(公告)日：2008-07-17
申请号：JP2007178049
申请日：2007-07-06
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： WANG JONG HYUN , PARK SE CHUN , PARK SEONG HUN
IPC分类号： G11C16/02
CPC分类号： G11C11/5628 , G11C2211/5642
摘要： PROBLEM TO BE SOLVED: To provide a multilevel cell nonvolatile memory device equipped with a page buffer for improving efficiency in high-order bit program for a specific cell, and a programming method thereof.
SOLUTION: The page buffer is provided with a bit line selection part 100 for selectively connecting a specific bit line BLe with a sense node SO. A data comparison part 130 compares data stored in a first register 110 with data stored in a second register 120, and transmits the comparison result to the sense node SO. A first bit line voltage control unit 160 applies a voltage of a low level to a bit line according to the voltage level of the data stored in the first register 110. A second bit line voltage control unit 170 applies a selected first high-level voltage to the bit line according to the voltage level of the data stored in the second register 120.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种配备有用于提高特定小区的高阶比特程序的效率的页面缓冲器的多级单元非易失性存储器件及其编程方法。解决方案：页缓冲器设置有位线选择部分100，用于选择性地将特定位线BLe与感测节点SO连接。数据比较部分130将存储在第一寄存器110中的数据与存储在第二寄存器120中的数据进行比较，并将比较结果发送到感测节点SO。第一位线电压控制单元160根据存储在第一寄存器110中的数据的电压电平向位线施加低电平的电压。第二位线电压控制单元170将所选择的第一高电平电压根据存储在第二寄存器120中的数据的电压电平到位线。版权所有：（C）2008，JPO＆INPIT

5. 发明专利

JP2008204598A Memory element and program verifying method 审中-公开
标题翻译：记忆元素和程序验证方法
公开(公告)号：JP2008204598A
公开(公告)日：2008-09-04
申请号：JP2008005591
申请日：2008-01-15
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： WANG JONG HYUN , KIN TOKUCHU , PARK SEONG HUN , YANG CHANG WON
IPC分类号： G11C16/02
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： PROBLEM TO BE SOLVED: To provide a memory element and a program verifying method in which a programming time can be decreased by decreasing a verifying time in program operation of a multi-level cell. SOLUTION: The memory element including a multi-level cell is provided with a memory cell array in which many cell strings 211 connected respectively to respective bit lines and a common ground line are included and positive voltage is supplied to the common ground line during verification of the program, a page buffer for programming the multi-level cell through respective bit lines and reading out data to the memory cell, and a verification control part which makes the page buffer verify a program state of the memory cell by connecting the bit line and the page buffer in accordance with a voltage level pre-charged to the bit line when program verification of the memory cell or read-out operation of data is performed. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种存储元件和程序验证方法，其中可以通过减少多级单元的编程操作中的验证时间来减少编程时间。解决方案：包括多电平单元的存储元件设置有存储单元阵列，其中包括分别连接到各个位线和公共接地线的许多单元串211，并且正电压被提供给公共接地线在验证程序期间，用于通过各个位线对多电平单元进行编程并将数据读出到存储单元的页缓冲器，以及通过连接所述页缓冲器来验证存储单元的程序状态的验证控制部分当执行存储器单元的程序验证或数据的读出操作时，根据在位线预充电的电压电平进行位线和页缓冲器。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2008181630A Method of programming in flash memory device 审中-公开
标题翻译：闪存存储器件编程方法
公开(公告)号：JP2008181630A
公开(公告)日：2008-08-07
申请号：JP2007225527
申请日：2007-08-31
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： WANG JONG HYUN
IPC分类号： G11C16/02 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454 , G11C2211/5621
摘要： PROBLEM TO BE SOLVED: To reduce program time by setting a program start voltage according to the moving path of a cell voltage. SOLUTION: In a multi-value flash memory device, the method includes performing a program from a first start voltage set for the cell of a first voltage level (to S407), determining whether the program has been passed for the cell of the first voltage level based on a first verifying voltage (S411), performing the program again by sequentially increasing voltages if the program has not been passed, comparing a current program voltage with a second start voltage set for the cell of the second voltage level in step S417 and after if the program has been passed, performing the program from the current program voltage or the second start voltage, determining whether the program has been passed for the cell of the second voltage level based on a second verifying voltage (S425), and performing the program again by sequentially increasing voltages if the program has not been passed. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：通过根据单元电压的移动路径设置程序启动电压来减少编程时间。解决方案：在多值闪速存储器件中，该方法包括从针对第一电压电平的单元设置的第一启动电压执行程序（至S407），确定程序是否已通过基于第一验证电压的第一电压电平（S411），如果程序尚未通过，则通过依次增加电压来再次执行程序，将当前编程电压与为第二电压电平的单元设置的第二启动电压进行比较步骤S417，然后如果程序已经通过，则从当前编程电压或第二起始电压执行程序，基于第二验证电压确定程序是否已经通过了第二电压电平的单元（S425）并且如果节目没有通过，则通过依次增加电压来再次执行该程序。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2010020881A Programming method of nonvolatile memory device 审中-公开
标题翻译：非易失性存储器件的编程方法
公开(公告)号：JP2010020881A
公开(公告)日：2010-01-28
申请号：JP2009017621
申请日：2009-01-29
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： WANG JONG HYUN
IPC分类号： G11C16/02
CPC分类号： G11C16/10 , G11C16/30
摘要： PROBLEM TO BE SOLVED: To provide a programming method and a multilevel cell programming method of a nonvolatile memory device, which attain variable setting according to a programming state without fixing a program start voltage to a specific value. SOLUTION: The programming method of the nonvolatile memory device includes steps of: receiving a first program operation instruction; performing a program operation according to a program start voltage stored in a program start voltage storage part; and updating the program start voltage with a program voltage applied when a memory cell programmed at a verify voltage or higher during the program operation is first generated. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供非易失性存储器件的编程方法和多电平单元编程方法，其根据编程状态获得可变设置，而不将程序启动电压固定为特定值。非易失性存储器件的编程方法包括以下步骤：接收第一程序操作指令; 根据存储在程序启动电压存储部分中的程序启动电压执行编程操作; 以及在编程操作期间以验证电压或更高的编程的存储器单元首先产生施加的编程电压来更新程序启动电压。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2009134849A Flash memory device and its programming method 审中-公开
标题翻译：闪存存储器件及其编程方法
公开(公告)号：JP2009134849A
公开(公告)日：2009-06-18
申请号：JP2008158714
申请日：2008-06-18
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： PARK SEONG HUN , WANG JONG HYUN
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
CPC分类号： G06F11/1068 , G11C16/3454 , G11C2216/14
摘要： PROBLEM TO BE SOLVED: To provide a flash memory device capable of increasing its efficiency, and a method for programming the flash memory device.
SOLUTION: The flash memory device includes: a memory cell array including a large number of memory cells, wherein the large number of memory cells are connected by a string structure; a page buffer unit including a large number of page buffers connected to a bit line of the memory cell array and transmitting program data to one of the memory cells after temporarily storing the program data during a program operation; a data line max unit which is coupled between the page buffer unit and a data line and outputs the program data to a page buffer selected from the page buffer unit during the program operation, and receives transmission of verification data via the page buffer during a verification operation; and a fail bit counter unit which counts the verification data, and compares counted fail bits with an ECC allowable number of bits to output a pass or fail signal of the program operation. The flash memory device and its programming method are disclosed.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供能够提高其效率的闪存器件以及用于对闪速存储器件进行编程的方法。解决方案：闪速存储器件包括：包括大量存储器单元的存储单元阵列，其中大量存储器单元通过串结构连接; 页面缓冲单元，包括连接到存储单元阵列的位线的大量页缓冲器，并且在程序操作期间临时存储程序数据之后将程序数据发送到存储单元之一; 数据线最大单元，其耦合在页缓冲器单元和数据线之间，并且在程序操作期间将程序数据输出到从页缓冲器单元中选择的页缓冲器，并且在验证期间经由页缓冲器接收验证数据的发送操作; 以及故障比特计数器单元，其对验证数据进行计数，并将计数的故障比特与ECC允许的比特数进行比较，以输出程序操作的通过或失败信号。公开了闪速存储器件及其编程方法。版权所有（C）2009，JPO＆INPIT

9. 发明专利

DE102007031027A1 未知
公开(公告)号：DE102007031027A1
公开(公告)日：2008-09-04
申请号：DE102007031027
申请日：2007-07-04
申请人： HYNIX SEMICONDUCTOR INC
发明人： WANG JONG HYUN , CHUNG JUN SEOP , JOO SEOK JIN
IPC分类号： G11C16/34
摘要： A read method of a memory device including a MLC includes the steps of performing a data read operation according to a first read command; determining whether error correction of the read data is possible; if, as a result of the determination, error correction is difficult, performing a data read operation according to a second read command; determining whether error correction of read data is possible according to the second read command; and if, as a result of the determination, error correction is difficult, performing a data read operation according to a Nth (N≧3, N is an integer) read command.

10. 发明专利

DE102007026856A1 Non-volatile memory component has memory cell array for storing data , page buffer having bitline selection device, which is configured for selectively coupling bit lines on scanning node 未知
公开(公告)号：DE102007026856A1
公开(公告)日：2008-07-03
申请号：DE102007026856
申请日：2007-06-11
申请人： HYNIX SEMICONDUCTOR INC
发明人： WANG JONG HYUN , PARK SE CHUN , PARK SEONG HUN
IPC分类号： G11C11/56 , G11C16/26
摘要： The memory component has a memory cell array for storing data , a page buffer , which is coupled on the memory cell array over two bit lines . The page buffer has a bitline selection device, which is configured for selectively coupling the bit lines on a scanning node. The two registers are configured to store given data. A data comparison device is configured for comparing the data stored in former register with the data stored in the later register and for transmitting a comparison result to the scanning node. An independent claim is also included for a method for programing a multi level cell (MLC) memory cell in a non volatile memory element.

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