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1. 发明申请

WO2010111832A1 SUBSTRATE WARPAGE-REDUCING STRUCTURE 审中-公开
标题翻译：基板保温结构
公开(公告)号：WO2010111832A1
公开(公告)日：2010-10-07
申请号：PCT/CN2009/071115
申请日：2009-03-31
申请人： HONG KONG APPLIED SCIENCE AND TECHNOLOGY RESEARCH INSTITUTE CO. LTD , LIN, Jyh-Rong , XIE, Bin , YEUNG, Yeung , SHI, Xunqing , CHUNG, Chang Hwa
发明人： LIN, Jyh-Rong , XIE, Bin , YEUNG, Yeung , SHI, Xunqing , CHUNG, Chang Hwa
IPC分类号： H01L21/00 , B32B5/00
CPC分类号： H05K1/0271 , H05K1/0306 , H05K2201/068 , H05K2201/09136 , H05K2201/09909
摘要： A method to provide warpage control of a substrate and an apparatus designed to perform this method are disclosed The method comprises arranging a first surface-modifying material on a first surface of a substrate, wherein the first surface-modifying material has a first pattern comprising one or more thickness to control warpage of the substrate.
摘要翻译：公开了一种提供基板的翘曲控制的方法和设计用于执行该方法的装置。该方法包括在基板的第一表面上布置第一表面改性材料，其中第一表面改性材料具有包括一个的第一图案或更大的厚度以控制基底的翘曲。

2. 发明申请

WO2010057339A1 SEMICONDUCTOR CHIP WITH THROUGH-SILICON-VIA AND SIDEWALL PAD 审中-公开
标题翻译：半导体芯片，通过硅和透明片
公开(公告)号：WO2010057339A1
公开(公告)日：2010-05-27
申请号：PCT/CN2008/073100
申请日：2008-11-19
申请人： HONG KONG APPLIED SCIENCE AND TECHNOLOGY RESEARCH INSTITUTE CO. LTD , SHI, Xunqing , XIE, Bin , CHUNG, Chang Hwa
发明人： SHI, Xunqing , XIE, Bin , CHUNG, Chang Hwa
IPC分类号： H01L25/065 , H01L23/049 , H01L23/053
CPC分类号： H01L23/16 , H01L21/76898 , H01L23/3128 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/06188 , H01L2224/16145 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2924/1433
摘要： Subject matter disclosed herein may re late to packaging for multi-chip semiconductor devices as may be used, fo r example, in flash memory devices. In an example embodiment, a semiconduc tor chip may comprise a through- silicon via and a sidewall pad.
摘要翻译：例如，在闪存设备中可以使用的用于多芯片半导体器件的封装可能会延迟到本文公开的主题。在示例性实施例中，半导体芯片可以包括硅通孔和侧壁衬垫。

3. 发明申请

WO2009117882A1 PULSE-LASER BONDING METHOD FOR THROUGH-SILICON-VIA BASED STACKING OF ELECTRONIC COMPONENTS 审中-公开
标题翻译：脉冲激光焊接方法，用于基于硅的电子组件的堆叠
公开(公告)号：WO2009117882A1
公开(公告)日：2009-10-01
申请号：PCT/CN2008/072293
申请日：2008-09-08
申请人： HONG KONG APPLIED SCIENCE AND TECHNOLOGY RESEARCH INSTITUTE CO. LTD , SHI, Xunqing , MA, Wei , XIE, Bin , CHUNG, Chang Hwa
发明人： SHI, Xunqing , MA, Wei , XIE, Bin , CHUNG, Chang Hwa
IPC分类号： H01L25/065 , H01L23/488
CPC分类号： H01L21/76898 , H01L21/6835 , H01L24/13 , H01L24/27 , H01L24/29 , H01L24/81 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2221/68359 , H01L2224/0401 , H01L2224/05166 , H01L2224/05171 , H01L2224/0557 , H01L2224/056 , H01L2224/05611 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/13099 , H01L2224/16 , H01L2224/274 , H01L2224/29101 , H01L2224/2919 , H01L2224/8182 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/0106 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/0665 , H01L2924/07802 , H01L2924/10253 , H01L2924/351 , H01L2924/00 , H01L2224/05552 , H01L2924/00014 , H01L2924/013
摘要： There is described a method of forming a through-silicon-via to form an interconnect between two stacked semiconductor components using pulsed laser energy. A hole is formed in each component, and each hole is fill ed with a plug formed of a first metal. One component is then stacked on another component such that the holes are in alignment, and a pulse of laser energy is applied to form a bond between the metal plugs.
摘要翻译：描述了形成穿硅通孔以形成使用脉冲激光能量的两个堆叠的半导体部件之间的互连的方法。在每个部件中形成孔，并且每个孔用由第一金属形成的塞子填充。然后将一个部件堆叠在另一部件上，使得孔对准，并且施加激光能量的脉冲以在金属插塞之间形成结合。

4. 发明申请

WO2008040200A1 STACKED MULTI-CHIP PACKAGE WITH EMI SHIELDING 审中-公开
标题翻译：带EMI屏蔽的堆叠多芯片封装
公开(公告)号：WO2008040200A1
公开(公告)日：2008-04-10
申请号：PCT/CN2007/070614
申请日：2007-09-04
申请人： HONG KONG APPLIED SCIENCE AND TECHNOLOGY RESEARCH INSTITUTE CO. LTD , LEUNG, Lap Wai , CHEN, Yu-Chih , SHAM, Man-Lung , CHUNG, Chang Hwa
发明人： LEUNG, Lap Wai , CHEN, Yu-Chih , SHAM, Man-Lung , CHUNG, Chang Hwa
IPC分类号： H01L23/552 , H01L23/28 , H05K9/00
CPC分类号： H01L23/552 , H01L23/5385 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A stacked multi-chip package with an EMI shielded component has first and second substrates (10,20) mounted together by a grid array of metallic connecting nodes (31), such as a solder Ball Grid Array. Each substrate has a conductive plane (15,25,35) associated with it. An electronic component (13) is mounted between the first and second substrates (10,20) and is surrounded by a group of the metallic connecting nodes (31) that are also electrically connected to the conductive planes (15,25,35) of both substrates to form a conductive Faraday cage about the component (13).
摘要翻译：具有EMI屏蔽部件的堆叠式多芯片封装具有由诸如焊料球栅阵列的金属连接节点（31）的栅格阵列安装在一起的第一和第二基板（10,20）。每个衬底具有与其相关联的导电平面（15,25,35）。电子部件（13）安装在第一和第二基板（10,20）之间，并被一组金属连接节点（31）围绕，金属连接节点（31）也电连接到导电平面（15,25,35）两个基板以形成围绕部件（13）的导电法拉第笼。

5. 发明申请

WO2009100614A1 ELECTRONIC CIRCUIT PACKAGE 审中-公开
标题翻译：电子电路包
公开(公告)号：WO2009100614A1
公开(公告)日：2009-08-20
申请号：PCT/CN2008/070258
申请日：2008-02-03
申请人： HONG KONG APPLIED SCIENCE AND TECHNOLOGY RESEARCH INSTITUTE CO. LTD. , LEUNG, Lap-Wai, Lydia , CHUNG, Chang Hwa , LIU, Jie , LEUNG, Chi Kuen , CHAN, Chiu Lun
发明人： LEUNG, Lap-Wai, Lydia , CHUNG, Chang Hwa , LIU, Jie , LEUNG, Chi Kuen , CHAN, Chiu Lun
IPC分类号： H01L23/02
CPC分类号： H05K1/181 , H01L23/3121 , H01L23/66 , H01L25/16 , H01L2224/48137 , H01L2224/48227 , H01L2924/09701 , H01L2924/3011 , H05K1/0237 , H05K1/0243 , H05K1/189 , H05K3/284 , H05K2201/10045 , H05K2201/1006 , H05K2201/10719 , H05K2203/049 , Y02P70/611
摘要： A electronic circuit package (1) having a flexible substrate (2) with metals layers on one or more of its surface forming a wiring pattern (9) and/or surface mount bonding pads (11, 12). Passive electronic components (6, 7, 8) are integrated onto component package (4) that is mounted on the flexible substrate (2) and electrically connected with the wiring pattern (9) bonding pads (11, 12). An active electronic device (5, 13) is mounted on the flexible substrate (2) or bonding pads (11, 12). The flexible substrate (2), the passive electronic components (6, 7, 8) and the active electronic device (5, 13) are encapsulated by encapsulating material (15).
摘要翻译：一种电子电路封装（1），其具有在形成布线图案（9）和/或表面贴装焊盘（11,12）的一个或多个表面上具有金属层的柔性基板（2）。无源电子部件（6,7,8）被集成到安装在柔性基板（2）上并与布线图案（9）接合焊盘（11,12）电连接的部件封装（4）上。有源电子器件（5,13）安装在柔性基板（2）或接合焊盘（11,12）上。柔性基板（2），无源电子部件（6,7,8）和有源电子器件（5,13）被封装材料（15）封装。

6. 发明申请

WO2009146587A1 BONGDING METHOD FOR THROUGH-SILICON-VIA BASED 3D WAFER STACKING 审中-公开
标题翻译：通过基于硅的3D波形堆叠的封装方法
公开(公告)号：WO2009146587A1
公开(公告)日：2009-12-10
申请号：PCT/CN2008/071193
申请日：2008-06-05
申请人： HONG KONG APPLIED SCIENCE & TECHNOLOGY RESEARCH INSTITUTE CO., LTD , MA, Wei , SHI, Xunqing , CHUNG, Chang Hwa
发明人： MA, Wei , SHI, Xunqing , CHUNG, Chang Hwa
IPC分类号： H01L23/488 , H01L25/00
CPC分类号： H01L25/0657 , H01L21/76898 , H01L24/13 , H01L24/29 , H01L24/30 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/11002 , H01L2224/1146 , H01L2224/1147 , H01L2224/13025 , H01L2224/13099 , H01L2224/131 , H01L2224/14131 , H01L2224/27002 , H01L2224/27618 , H01L2224/29011 , H01L2224/29012 , H01L2224/29015 , H01L2224/2919 , H01L2224/30131 , H01L2224/73103 , H01L2224/73203 , H01L2224/81005 , H01L2224/81815 , H01L2224/83005 , H01L2224/838 , H01L2224/8385 , H01L2224/83856 , H01L2224/83862 , H01L2224/83986 , H01L2224/9205 , H01L2224/92242 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01327 , H01L2924/07811 , H01L2924/10253 , H01L2924/14 , H01L2924/00014 , H01L2224/81 , H01L2924/014 , H01L2924/01028 , H01L2924/00 , H01L2224/05552 , H01L2924/00012
摘要： There is described a hybrid bonding method for through-silicon-via based wafer stacking. Patterned adhesive layers are provided to join together adjacent wafers in the stack, while solder bondng is used to electrically connect the vias. The adhesive layers are patterned to enable outgassing and to provide stress relief.
摘要翻译：描述了用于基于硅通孔的晶片堆叠的混合结合方法。提供图案化的粘合剂层以将堆叠中的相邻晶片连接在一起，而焊接焊接用于电连接通孔。图案化粘合剂层以能够脱气并提供应力消除。

7. 发明申请

WO2009146588A1 BONDING METHOD FOR THROUGH-SILICON-VIA BASED 3D WAFER STACKING 审中-公开
标题翻译：用于基于硅的三维WAFER堆叠的绑定方法
公开(公告)号：WO2009146588A1
公开(公告)日：2009-12-10
申请号：PCT/CN2008/071203
申请日：2008-06-05
申请人： HONG KONG APPLIED SCIENCE AND TECHNOLOGY RESEARCH INSTITUTE CO., LTD.. , LEUNG, Chi Kuen , SUN, Peng , SHI, Xunqing , CHUNG, Chang Hwa
发明人： LEUNG, Chi Kuen , SUN, Peng , SHI, Xunqing , CHUNG, Chang Hwa
IPC分类号： H01L23/488 , H01L25/00
CPC分类号： H01L24/94 , H01L21/6836 , H01L21/76898 , H01L24/11 , H01L24/16 , H01L24/29 , H01L24/742 , H01L24/92 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/6834 , H01L2224/13009 , H01L2224/13099 , H01L2224/83194 , H01L2224/9202 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/07811 , H01L2924/10253 , H01L2224/83 , H01L2224/11 , H01L2924/00
摘要： There is described a bonding method for through-silicon- via bonding of a wafer stack in which the wafers are formed with through-silicon-vias and lateral microchannels that are filled with solder. To fill the vias and channels the wafer stack is placed in a soldering chamber and molten solder is drawn through the vias and channels by vacuum. The wafers are held together by layers of adhesive during the assembly of the wafer stack. Means are provided for local reheating of the solder after it has cooled to soften the solder to enable it to be removed from the soldering chamber.
摘要翻译：描述了通过晶片叠层的硅 - 硅 - 通孔结合的粘合方法，其中晶片形成有穿过硅通孔和填充有焊料的侧向微通道。为了填充通孔和通道，将晶片堆叠放置在焊接室中，并且熔融的焊料通过真空通过通孔和通道。在晶片堆叠的组装期间，晶片通过粘合剂层保持在一起。提供用于在焊料冷却以软化焊料以使其能够从焊接室除去的焊料的局部再加热的装置。

8. 发明申请

WO2010111825A1 ELECTRONIC PACKAGE AND METHOD OF FABRICATION THEREOF 审中-公开
标题翻译：电子封装及其制造方法
公开(公告)号：WO2010111825A1
公开(公告)日：2010-10-07
申请号：PCT/CN2009/071083
申请日：2009-03-30
申请人： HONG KONG APPLIED SCIENCE AND TECHNOLOGY RESEARCH INSTITUTE CO., LTD. , LEUNG, Chi Kuen , SUN, Peng , SHI, Xunqing , CHUNG, Chang Hwa
发明人： LEUNG, Chi Kuen , SUN, Peng , SHI, Xunqing , CHUNG, Chang Hwa
IPC分类号： H01L25/065 , H01L25/07 , H01L23/485 , H01L21/60
CPC分类号： H01L21/6835 , H01L21/568 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L25/0652 , H01L25/18 , H01L2224/04105 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01082 , H01L2924/181 , H01L2924/00
摘要： An electronic package is provided, which comprises at least a first module (2) and a second module (4) arranged on top of the first module (2), wherein the first and second modules (2, 4) are adhesively connected together and in the form of a module stack. Each of the modules (2,4) includes a substrate layer (8) with at least one metal layer (10), at least one die (16, 22) and a plastic package molding compound layer (32) molded over the die or dice (16, 22), wherein the die or dice (16, 22) are bonded on the substrate layer (8) via the metal layer (10), and a plurality of channels (34, 36, 38, 40, 42, 44) are formed generally vertically acting as vias to connect the metal layers (10) in different modules. Some or all the channels (34, 36, 38, 40, 42, 44) are provided with an inner surface coated with a conductive material layer or filled with a conductive material for electrical connection, whereby the dice (16, 22) in the module stack are electrically connected together. At least one module (2) includes a means (46) which is connected to the channels (34, 36, 38, 40, 42, 44) and serves as an intermediary for providing electrical, mechanical and thermal connectivity, and communication externally. A method for fabricating the electronic package is also provided.
摘要翻译：提供了一种电子封装，其包括至少第一模块（2）和布置在第一模块（2）的顶部上的第二模块（4），其中第一和第二模块（2,4）粘合地连接在一起，以模块堆栈的形式。每个模块（2,4）包括具有至少一个金属层（10）的基底层（8），在模具上模制的至少一个模具（16,22）和塑料封装模制化合物层（32），或骰子（16,22），其中所述骰子或骰子（16,22）经由所述金属层（10）接合在所述基底层（8）上，以及多个通道（34,36,38,40,42， 44）通常垂直地形成为通孔以将不同模块中的金属层（10）连接起来。一些或所有通道（34,36,38,40,42,44）设置有涂覆有导电材料层或填充有用于电连接的导电材料的内表面，由此，所述导体（16,22）模块堆叠电连接在一起。至少一个模块（2）包括连接到通道（34,36,38,40,42,44）的装置（46），并且用作用于提供电气，机械和热连接以及外部通信的中介。还提供了一种用于制造电子封装的方法。

9. 发明申请

WO2010111836A1 APPARATUS FOR DETERMINING BLOOD PRESSURE 审中-公开
标题翻译：用于测定血压的装置
公开(公告)号：WO2010111836A1
公开(公告)日：2010-10-07
申请号：PCT/CN2009/071141
申请日：2009-04-02
申请人： HONG KONG APPLIED SCIENCE AND TECHNOLOGY RESEARCH INSTITUTE CO., LTD. , LEUNG, Lap Wai , TO, Kwan Wai , LUK, Chi Tin , CHUNG, Chang Hwa
发明人： LEUNG, Lap Wai , TO, Kwan Wai , LUK, Chi Tin , CHUNG, Chang Hwa
IPC分类号： A61B5/022
CPC分类号： A61B5/0225 , A61B5/0002 , A61B5/02125
摘要： An apparatus for determining the blood pressure of a person, comprises: a blood pressure measuring device that measures a blood pressure value of a person at a first period in time, a storage device that stores the measured blood pressure value, a transmitter device that automatically detects the presence of a blood pressure calculating device and transmits the stored measured blood pressure value to the blood pressure calculating device at a second period in time, and a blood pressure calculating device that includes a mathematical model for estimating blood pressure based on a current change in blood induced by a heart beat and the previously measured blood pressure.
摘要翻译：一种用于确定人的血压的装置，包括：测量人第一时间段的血压值的血压测量装置，存储测量血压值的存储装置，自动地发射的发射装置检测血压计算装置的存在，并且将所存储的测量血压值在第二时间段内传送到血压计算装置，以及血压计算装置，其包括基于电流变化估计血压的数学模型在由心跳引起的血液中和先前测得的血压。

10. 发明申请

WO2009052683A1 ELECTRONIC CIRCUIT PACKAGE 审中-公开
标题翻译：电子电路包
公开(公告)号：WO2009052683A1
公开(公告)日：2009-04-30
申请号：PCT/CN2007/070954
申请日：2007-10-25
申请人： HONG KONG APPLIED SCIENCE AND TECHNOLOGY RESEARCH INSTITUTE CO., LTD. , LEUNG, Lap-Wai Lydia , CHEN, Yu-Chih , LEUNG, Chi Kuen , CHUNG, Chang Hwa
发明人： LEUNG, Lap-Wai Lydia , CHEN, Yu-Chih , LEUNG, Chi Kuen , CHUNG, Chang Hwa
IPC分类号： H01L23/15
CPC分类号： H01L23/15 , H01L27/13 , H01L2224/48091 , H01L2224/48227 , H01L2924/09701 , H01L2924/19041 , H01L2924/3011 , H01L2924/00014
摘要： An electronic circuit package(1) has a thin-film circuit(3) integrated with the ceramic substrate(2). The thin-film circuit(3) includes at least two passive circuit elements joined by an integrated electrical interconnect. At least one active electronic component(4) is mounted on the ceramic substrate(2) without any dielectric material between the active electronic component(4) and the ceramic substrate, and is electrically connected with the integrated thin-film circuit(3).
摘要翻译：电子电路封装（1）具有与陶瓷基板（2）成一体的薄膜电路（3）。薄膜电路（3）包括通过集成电互连连接的至少两个无源电路元件。至少一个有源电子部件（4）安装在陶瓷基片（2）上，而在有源电子部件（4）和陶瓷基片之间没有任何电介质材料，并与集成薄膜电路（3）电连接。

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