专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO03021636B1 ELECTRONIC DEVICES AND METHODS OF MANUFACTURE 审中-公开
标题翻译：电子设备及其制造方法
公开(公告)号：WO03021636B1
公开(公告)日：2003-12-04
申请号：PCT/US0226780
申请日：2002-08-23
申请人： HONEYWELL INT INC , ENDISCH DENIS , LEVERT JOSEPH
发明人： ENDISCH DENIS , LEVERT JOSEPH
IPC分类号： H01L21/76 , H01L21/312 , H01L21/316 , H01L21/762 , H01L29/00
CPC分类号： H01L21/76224 , H01L21/02126 , H01L21/02282 , H01L21/3121 , H01L21/316 , H01L21/31612
摘要： An electronic device (110B) comprises a substrate (110B) with a trench (120B) having a lower (121B) portion and a top portion (122B). The lower portion (121B) of the trench (120B) is filled with a cured spin-on compound (130B), while the top portion (122B) is filled with a chemical vapor-deposited compound (140B). Preferably, the chemical vapor-deposited compound (140B) has a surface (141B) that is substantially coplanar with the surface (111B) of the substrate (110B).
摘要翻译：电子设备（110B）包括具有下部（121B）部分和顶部部分（122B）的沟槽（120B）的衬底（110B）。沟槽（120B）的下部（121B）填充有固化的旋涂化合物（130B），而顶部（122B）填充有化学气相沉积化合物（140B）。优选地，化学气相沉积化合物（140B）具有与基底（110B）的表面（111B）基本上共面的表面（141B）。

2. 发明申请

WO02059966A8 PLANARIZERS FOR SPIN ETCH PLANARIZATION OF ELECTRONIC COMPONENTS AND METHODS OF USE THEREOF 审中-公开
标题翻译：用于电子元件的旋转计划平面图的计算机及其使用方法
公开(公告)号：WO02059966A8
公开(公告)日：2003-10-16
申请号：PCT/US0201861
申请日：2002-01-22
申请人： HONEYWELL INT INC , MUKHERJEE SHYAMA , LEVERT JOSEPH , DEBEAR DONALD
发明人： MUKHERJEE SHYAMA , LEVERT JOSEPH , DEBEAR DONALD
IPC分类号： H01L21/3205 , C23F3/06 , H01L21/321 , H01L21/3213 , H01L21/768 , H01L23/52 , H01L23/532 , H01L23/48
CPC分类号： H01L21/32115 , C23F3/06 , H01L21/32134 , H01L21/7684 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An electronic component contemplated comprises a substrate layer (110), a dielectric layer (120) coupled to the substrate layer (110), a barrier layer (130) coupled to the dielectric layer (120), a conductive layer (140) coupled to the barrier layer (130), and a protective layer (150) coupled to the conductive layer (140). A method of making the electronic component comprises the steps of providing a substrate (110) coupling a dielectric layer (120) to the substrate (110), coupling a barrier layer (130) to the dielectric layer (120), coupling a conductive layer (140) to the barrier layer (130), and coupling a protective layer (150) to the conductive layer (140). A method of planarizing a conductive surface of the electronic component comprises the steps of introducing or coupling a protective layer (150) onto a conductive layer (140), dispersing the protective layer (150) across the conductive layer (140), curing the protective layer (150), introducing an etching solution onto the conductive layer (140), and etching the conductive surface to substantial planarity.
摘要翻译：预期的电子部件包括衬底层（110），耦合到衬底层（110）的电介质层（120），耦合到电介质层（120）的阻挡层（130），耦合到所述阻挡层（130）以及耦合到所述导电层（140）的保护层（150）。制造电子部件的方法包括以下步骤：提供将电介质层（120）耦合到衬底（110）的衬底（110），将阻挡层（130）耦合到电介质层（120），将导电层（140）连接到阻挡层（130），并且将保护层（150）耦合到导电层（140）。平面化电子部件的导电表面的方法包括以下步骤：将保护层（150）引入或耦合到导电层（140）上，将保护层（150）分散在导电层（140）上，固化保护层层（150），将蚀刻溶液引入到导电层（140）上，并且将导电表面蚀刻到显着的平面度。

3. 发明申请

WO02059962A3 VISCOUS PROTECTIVE OVERLAYERS FOR PLANARIZATION OF INTEGRATED CIRCUITS 审中-公开
标题翻译：用于集成电路平面化的VISCOUS保护覆盖层
公开(公告)号：WO02059962A3
公开(公告)日：2003-04-17
申请号：PCT/US0201692
申请日：2002-01-22
申请人： HONEYWELL INT INC
发明人： MUKHERJEE SHYAMA , DEBEAR DONALD , LEVERT JOSEPH
IPC分类号： C23F1/02 , C23F1/18 , C23F3/06 , H01L21/306 , H01L21/321 , H01L21/3213 , H01L21/768 , H01L23/532
CPC分类号： H01L21/32115 , C23F3/06 , H01L21/32134 , H01L21/7684 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , Y10S977/712 , Y10S977/788 , H01L2924/00
摘要： The present invention relates to the planarization of surfaces as typically encountered in the fabrication of integrated circuits, particularly copper conductors and Ta/TaN barrier layers encountered in damascene and dual damascene interconnects. The present invention describes planarization methods for Cu/Ta/TaN interconnects, typically making use of a viscous overlayer (13) tending to dwell in regions of lower surface topography (8, 9, 10), protecting said lower regions from etching by a combination of chemical and mechanical effects. In some embodiments, the viscous overlayer contains species that hinder removal of copper from regions of the surface in contact with the viscous layer. Such species may be a substantially saturated solution of copper ions among other additives, thereby hindering the dissolution of interconnect copper into the protective overlayer. In some embodiments of the present invention, the viscous overlayer may be added prior to the introduction of etchant to the wafer surface, or both etchant and viscous overlayer may be introduced substantially simultaneously, typically as the wafer is spun during planarization.
摘要翻译：本发明涉及通常在集成电路的制造中遇到的表面的平坦化，特别是在镶嵌和双镶嵌互连中遇到的铜导体和Ta / TaN阻挡层。本发明描述了用于Cu / Ta / TaN互连的平坦化方法，通常使用倾向于驻留在下表面形貌（8,9,10）的区域中的粘性覆层（13），通过组合保护所述下部区域免受蚀刻的化学和机械效应。在一些实施方案中，粘性覆层包含妨碍从与粘性层接触的表面区域去除铜的物质。这样的物质可以是其他添加剂中基本饱和的铜离子溶液，从而阻碍互连铜溶解到保护性覆盖层中。在本发明的一些实施方案中，可以在将蚀刻剂引入晶片表面之前添加粘性覆层，或者基本上同时引入蚀刻剂和粘性覆盖层，通常当平坦化期间晶片旋转时。

4. 发明专利

DE01998054T1 未知
公开(公告)号：DE01998054T1
公开(公告)日：2005-01-13
申请号：DE01998054
申请日：2001-12-18
申请人： HONEYWELL INT INC
发明人： ZHANG FAN , TOWERY DANIEL , LEVERT JOSEPH , MUKHERJEE SHYAMA
IPC分类号： B24B37/00 , C09G1/02 , C09K13/06 , C23F1/18 , C23F1/26 , C23F1/30 , C23F3/04 , C23F3/06 , H01L21/304 , H01L21/321 , H01L21/3213
摘要： Chemical mechanical planarization or spin etch planarization of surfaces of copper, tantalum and tantalum nitride is accomplished by means of the chemical formulations of the present invention. The chemical formulations may optionally include abrasive particles and which may be chemically reactive or inert. Contact or non-contact CMP may be performed with the present chemical formulations. Substantially 1:1 removal rate selectivity for Cu and Ta/TaN is achieved.

5. 发明专利

ES2209676T1 未知
公开(公告)号：ES2209676T1
公开(公告)日：2004-07-01
申请号：ES01998054
申请日：2001-12-18
申请人： HONEYWELL INT INC
发明人： ZHANG FAN , TOWERY DANIEL , LEVERT JOSEPH , MUKHERJEE SHYAMA
IPC分类号： B24B37/00 , C09G1/02 , C09K13/06 , C23F1/18 , C23F1/26 , C23F1/30 , C23F3/04 , C23F3/06 , H01L21/304 , H01L21/321 , H01L21/3213
摘要： Chemical mechanical planarization or spin etch planarization of surfaces of copper, tantalum and tantalum nitride is accomplished by means of the chemical formulations of the present invention. The chemical formulations may optionally include abrasive particles and which may be chemically reactive or inert. Contact or non-contact CMP may be performed with the present chemical formulations. Substantially 1:1 removal rate selectivity for Cu and Ta/TaN is achieved.

6. 发明专利

AU2002326737A1 Electronic devices and methods of manufacture 未知
公开(公告)号：AU2002326737A1
公开(公告)日：2003-03-18
申请号：AU2002326737
申请日：2002-08-23
申请人： HONEYWELL INT INC
发明人： ENDISCH DENIS , LEVERT JOSEPH
IPC分类号： H01L21/76 , H01L21/312 , H01L21/316 , H01L21/762 , H01L29/00
摘要： An electronic device comprises a substrate with a trench having a lower portion and a top portion. The lower portion of the trench is filled with a cured spin-on compound, while the top portion is filled with a chemical vapor-deposited compound. Preferably, the chemical vapor-deposited compound has a surface that is substantially coplanar with the surface of the substrate. Particularly preferred methods of fabricating such devices include a step in which a trench is formed in the substrate, and in which a first compound is deposited in the trench by spin-on deposition. The first compound is partially removed from the trench to a level below the surface of the substrate, and in a further step, a second compound is deposited onto the upper surface of the first compound by chemical vapor deposition.

7. 发明专利

CA2432012A1 PLANARIZERS FOR SPIN ETCH PLANARIZATION OF ELECTRONIC COMPONENTS AND METHODS OF USE THEREOF 未知
公开(公告)号：CA2432012A1
公开(公告)日：2002-08-01
申请号：CA2432012
申请日：2002-01-22
申请人： HONEYWELL INT INC
发明人： DEBEAR DONALD , LEVERT JOSEPH , MUKHERJEE SHYAMA
IPC分类号： C23F1/02 , C23F1/18 , C23F3/06 , H01L21/306 , H01L21/321 , H01L21/3213 , H01L21/768 , H01L23/532 , H01L23/48
摘要： An electronic component contemplated comprises a substrate layer (110), a dielectric layer (120) coupled to the substrate layer (110), a barrier layer (130) coupled to the dielectric layer (120), a conductive layer (140) couple d to the barrier layer (130), and a protective layer (150) coupled to the conductive layer (140). A method of making the electronic component comprise s the steps of providing a substrate (110) coupling a dielectric layer (120) t o the substrate (110), coupling a barrier layer (130) to the dielectric layer (120), coupling a conductive layer (140) to the barrier layer (130), and coupling a protective layer (150) to the conductive layer (140). A method of planarizing a conductive surface of the electronic component comprises the steps of introducing or coupling a protective layer (150) onto a conductive layer (140), dispersing the protective layer (150) across the conductive lay er (140), curing the protective layer (150), introducing an etching solution on to the conductive layer (140), and etching the conductive surface to substantia l planarity.

8. 发明专利

CA2435623A1 VISCOUS PROTECTIVE OVERLAYERS FOR PLANARIZATION OF INTEGRATED CIRCUITS 未知
公开(公告)号：CA2435623A1
公开(公告)日：2002-08-01
申请号：CA2435623
申请日：2002-01-22
申请人： HONEYWELL INT INC
发明人： MUKHERJEE SHYAMA , DEBEAR DONALD , LEVERT JOSEPH
IPC分类号： C23F1/02 , C23F1/18 , C23F3/06 , H01L21/306 , H01L21/321 , H01L21/3213 , H01L21/768 , H01L23/532
摘要： The present invention relates to the planarization of surfaces as typically encountered in the fabrication of integrated circuits, particularly copper conductors and Ta/TaN barrier layers encountered in damascene and dual damascene interconnects. The present invention describes planarization metho ds for Cu/Ta/TaN interconnects, typically making use of a viscous overlayer (13 ) tending to dwell in regions of lower surface topography (8, 9, 10), protecti ng said lower regions from etching by a combination of chemical and mechanical effects. In some embodiments, the viscous overlayer contains species that hinder removal of copper from regions of the surface in contact with the viscous layer. Such species may be a substantially saturated solution of copper ions among other additives, thereby hindering the dissolution of interconnect copper into the protective overlayer. In some embodiments of th e present invention, the viscous overlayer may be added prior to the introduction of etchant to the wafer surface, or both etchant and viscous overlayer may be introduced substantially simultaneously, typically as the wafer is spun during planarization.

9. 发明专利

CA2431591A1 COMPOSITION FOR CHEMICAL MECHANICAL PLANARIZATION OF COPPER,TANTALUM AND TANTALUM NITRIDE 未知
公开(公告)号：CA2431591A1
公开(公告)日：2002-08-01
申请号：CA2431591
申请日：2001-12-18
申请人： HONEYWELL INT INC
发明人： LEVERT JOSEPH , MUKHERJEE SHYAMA , ZHANG FAN , TOWERY DANIEL
IPC分类号： B24B37/00 , C09G1/02 , C09K13/06 , C23F1/18 , C23F1/26 , C23F1/30 , C23F3/04 , C23F3/06 , H01L21/304 , H01L21/321 , H01L21/3213
摘要： Chemical mechanical planarization or spin etch planarization of surfaces of copper, tantalum and tantalum nitride is accomplished by means of the chemic al formulations of the present invention. The chemical formulations may optionally include abrasive particles and which may be chemically reactive o r inert. Contact or non-contact CMP may be performed with the present chemical formulations. Substantially 1:1 removal rate selectivity for Cu and Ta/TaN i s achieved.

10. 发明专利

AU2002237917A1 Planarizers for spin etch planarization of electronic components and methods of use thereof 未知
公开(公告)号：AU2002237917A1
公开(公告)日：2002-08-06
申请号：AU2002237917
申请日：2002-01-22
申请人： HONEYWELL INT INC
发明人： LEVERT JOSEPH , DEBEAR DONALD , MUKHERJEE SHYAMA
IPC分类号： H01L21/3205 , C23F3/06 , H01L21/321 , H01L21/3213 , H01L21/768 , H01L23/52 , H01L23/532 , H01L23/48

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式