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1. 发明专利

JPH08138400A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH08138400A
公开(公告)日：1996-05-31
申请号：JP29889094
申请日：1994-11-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUZUKI YUKIE
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04
摘要： PURPOSE: To repair a defective address efficiently by controlling a switch with a repair enable signal variable depending on the decision result of matching between a programmed repair address and an access address and connecting first and second I/O lines with a main amplifier. CONSTITUTION: When a programmed repair address is matched with an access address, a column repair enable signal YR goes High. Consequently, a switch comprising a p-channel FET Qa and an n-channel FET Qb for each redundant IF/O lines RIO0-RIO7 of a select circuit is turned ON and the I/O lines RIO 0-RIO7 are connected selectively with the common data lines CD0-CD3 of a main amplifier MA. When they do not match each other, the I/O lines RIO0-RIO 7 are connected with the data lines CD0-CD7. With such structure, defective address is repaired efficiently at high rate while suppressing the delay of access time.

2. 发明专利

JPH06215571A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH06215571A
公开(公告)日：1994-08-05
申请号：JP387893
申请日：1993-01-13
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YAMAZAKI EIJI , TANAKA HITOSHI , NAKAGOME YOSHINOBU , ETO JUN , MIYAZAWA KAZUYUKI , SUZUKI YUKIE , MUSHA TATSUNORI , AOKI MASAKAZU , EBIHARA TAKASHI
IPC分类号： G11C11/413 , G11C11/401 , G11C11/407 , G11C11/409
摘要： PURPOSE:To reduce a peak current, to accelerate the operation and to reduce a layout area by supplying electric charge from both sides of a capacitor charged to VCC and a power source line to a load when a load circuit is driven. CONSTITUTION:The read operation is started when a signal RASB becomes from 3V to 0V after precharged. A memory signal appears on a data line when a word line WL is received with the RASB and raised from 0V to 4.5V. Q15, Q16 are turned on by that phi2 becomes from 0V to 3V and phi2b becomes from 3V to 0V. The level of CSP is raised to VCC, and the level of CSN is lowered to grounded potential. Thus, an SA is started, and the charge of the data line D1 and the discharge of the D2 are started according to the memory signal. At this time, the charge to the CSP is performed from both sides of the capacitor C1 and the power source line 200. Further, the potential of the CSP is raised to 2.5V. Thus, the conductance of the MOSFET in the sense amplifier becomes large, and the speed of the charge/discharge by the sense amplifier is accelerated.

3. 发明专利

JPH0575062A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0575062A
公开(公告)日：1993-03-26
申请号：JP23444591
申请日：1991-09-13
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUZUKI YUKIE , KOYAMA YOSHIHISA
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To shorten the time period required for design and development of dynamic type RAM by reducing the number of photo masks to be corrected as a result of the adjustment or specification change of the RAM. CONSTITUTION:Combined distribution, that is selectively cut off for selectively switching the delay time of a signal generating circuit SG such as dynamic type RAM or the like, is formed by three aluminum wiring layers AL11, AL24 and AL31; also, the combined distribution selectively connected is formed by two aluminum wiring layers AL14 and AL34 or the like which are essentially arranged in parallel. By doing this, the combined distribution can be selectively cut off or connected by revising or switching any photomask related to a plurality of metal wiring layers, so that the adjustment of delay time can be efficiently realized by taking advantage of the revision of another wiring for instance.

4. 发明专利

JPH04318392A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH04318392A
公开(公告)日：1992-11-09
申请号：JP8497091
申请日：1991-04-17
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MURANAKA MASAYA , SUZUKI YUKIE
IPC分类号： G11C11/407 , G11C11/401 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To realize high speed driving of a word line without reducing the reliability and the yield of the semiconductor integrated circuit device which has a DRAM circuit region. CONSTITUTION:A memory mat 1 of DRAM is divided into plural minute memory cell regions 2, word line driving circuit regions WD1 and WD2 are dispersedly placed for each minute memory cell region 2 by surrounding it and each of the word line driving circuit located within the word line driving circuit regions WD1 and WD2 is connected to the minute memory cell region 2 by a word line WL which consists of low resistance polysilicon.

5. 发明专利

JPH04245096A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH04245096A
公开(公告)日：1992-09-01
申请号：JP1058291
申请日：1991-01-31
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUZUKI YUKIE
IPC分类号： G01R31/28 , G11C11/401 , G11C29/00 , G11C29/34 , H01L21/66 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To improve reliability by providing another one data output buffer which outputs a logical level of a predetermined bit of stored data of a plurality of bits to be simultaneously read through other predetermined external terminal. CONSTITUTION:A data output buffer DOB which outputs a logical level of a predetermined bit of stored data of a plurality of bits to be simultaneously read at the time of testing multiple bits through other predetermined external terminal is provided in a dynamic RAM, etc., having a multi-bit testing function of a binary output test mode. With such a configuration, the level is decided to match the compared collated result of the stored data of the plurality of bits to be simultaneously read at the time of testing multiple bits. Even if the level of the stored data is simultaneously inverted, it is detected to identify a malfunction of the RAM, etc.

6. 发明专利

JPH0816486A LSI FOR DEFECT REMEDY AND MEMORY DEVICE 失效
公开(公告)号：JPH0816486A
公开(公告)日：1996-01-19
申请号：JP17020794
申请日：1994-06-29
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： WADA SHOJI , KEMIZAKI KANEHIDE , MURANAKA MASAYA , OGATA SHINKO , AOYANAGI HIDEAKI , KITAME TETSUYA , KATAYAMA MASAHIRO , KUBONO SHIYOUJI , SUZUKI YUKIE , MORINO MAKOTO , MIYATAKE SHINICHI , HARUFUJI SEIICHI , KOYAMA YOSHIHISA , ONO NOBUHIKO
IPC分类号： G06F12/16 , G11C29/00 , G11C29/02 , G11C29/44 , H01L21/82
摘要： PURPOSE:To provide an LSI which can remedy a defect of a mounted DRAM and to provide a memory device which can remedy the defect of the DRAM generated after assembly. CONSTITUTION:The LSI for defect remedy consists of an interface part for the same address and control with DRAMs, an input/output interface corresponding to the memory device consisting of plural DRAMs, a nonvolatile storage circuit 3 which stores the chip addresses of the DRAMs and a defect address of an X system, a RAM part 4 for redundancy remedy consisting of an SRAM which has a word line selected with a comparison matching signal between an inputted X address and the defect address of the storage circuit and a column selected with a Y address signal, a selection part 6 which connects the data input/output bus of the RAM part for redundancy to a data input/output terminal, a data input/output part 7 which activates an input/output circuit corresponding to the selection, and a mask part 8 which outputs a signal for placing the output terminal of a DRAM judged to be defective in a high-impedance state.

7. 发明专利

JPH04155859A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH04155859A
公开(公告)日：1992-05-28
申请号：JP28148690
申请日：1990-10-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KOYAMA YOSHIHISA , MATSUURA NOBUMI , II HARUO , MURANAKA MASAYA , ABE JUNICHI , SUZUKI YUKIE , ARAI KOJI , YOSHIKAWA KAZUE
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L21/8249 , H01L27/06 , H01L27/10 , H01L27/108
摘要： PURPOSE:To enhance an electrostatic breakdown preventive circuit in breakdown strength by a method wherein the distance between the connection region of a second semiconductor region connected to an outer terminal and the peripheral edge nearest to the connection region is set equal to or larger than the junction depth of the second semiconductor region at the connection region. CONSTITUTION:A P-type well region 3 higher than a P -type semiconductor substrate 1 in impurity concentration is formed on a first region of the primary surface of the P -type semiconductor substrate 1, and an N-type well region 2 is formed on a second region of the primary surface of the P -type semiconductor substrate 1. The N-type well region 2 forms the protective resistive element R of an electrostatic breakdown protecting circuit 30, where the one end of the element R is connected to an external terminal BP provided to the primary surface and the other end is connected to an input stage circuit 31. A distance L2 between the connection region (N -type semiconductor region 8) of the N-type well region 2 which serves as the element R of the electrostatic breakdown protective circuit 30 and the nearest periphery is set equal to or larger than the junction depth L1 of the N-type well region 2 at the connection region.

8. 发明专利

JPH06333392A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH06333392A
公开(公告)日：1994-12-02
申请号：JP11813293
申请日：1993-05-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUZUKI YUKIE , NAKAI KIYOSHI , MURANAKA MASAYA
IPC分类号： G11C11/409 , G11C11/401
摘要： PURPOSE:To suppress the influence of decreasing a power source voltage affecting the margin of reading operation and an access time and to enhance the voltage lowering of a dynamic RAM, etc. CONSTITUTION:The effective level of a pre-charging control signal PCSO supplied to the gate of a pre-charging MOSFET N9 is made to be a high voltage VCH immediately after a dynamic RAM is made a non-selection state from its selection state so as to make the corresponding memory array an active state and made to become the power source voltage VCC during the period in which the corresponding memory array is made the active state after the dynamic RAM is again made the selection state. At the beginning of the non- selection state of the dynamic RAM, the voltage between the gate and the source of the MOSFET N9 is increased and the equalizing operation of a complementary bit line is surely performed at high speed. During the period in which the corresponding memory array is made the active state after the dynamic RAM is again made the selection state, the potential of the pre-charging control signal is lowered earlier down to the power source voltage VCC and the MOSFET N9 is quickly turned off.

9. 发明专利

JPH04349294A DYNAMIC TYPE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH04349294A
公开(公告)日：1992-12-03
申请号：JP12339791
申请日：1991-05-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KOYAMA YOSHIHISA , SUZUKI YUKIE
IPC分类号： G11C11/404 , G11C11/407
摘要： PURPOSE:To prevent an insulating film under a plate electrode from being collapsed with static electricity by interposing a switch for power supply/ interruption between an external source voltage terminal or a Vcc/2 generator and the plate electrode. CONSTITUTION:This memory is constituted so that the Vcc/2 voltage generated in the Vcc/2 generator 5 is capable to supply to the plate electrode in a memory array through a switch MOSQ1 and to a data line and to a sense amplifier through a switch MOSQ2. In such a case, when a start detecting signal WK is supplied to a Vcc/2 supply control signal generator 6, a supply control signal VPLC to be its output signal is low level, thus, switches MOSQ1, Q2 are turned off and even when the Vcc/2 voltage is generated in the Vcc/2 generator, the supply is interrupted. On the contrary, when high voltage as static electricity is impressed transiently to the source voltage terminal, since switchs MOSQ1, Q2 are turned off, high voltage is unsupplied to the plate electrode and the collaps of the insulating film is prevented.

10. 发明专利

JPH0489690A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0489690A
公开(公告)日：1992-03-23
申请号：JP19869590
申请日：1990-07-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUZUKI YUKIE , MATSUURA NOBUMI
IPC分类号： G11C11/401 , G11C11/409 , G11C11/419 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To reduce a peak current and to enable high-speed access by making driving ability different between two sense amplifiers allocated with two pairs of bit lines as one unit, and executing control so as to connect the bit line connected a memory cell to be selected corresponding to the selecting operation of the memory cell to the sense amplifier having higher driving ability. CONSTITUTION:A control means is provided to control each changeover switch means so as to connect the bit line coupled the memory cell to be selected corresponding to the selecting operation of the memory cell to the sense amplifier having relatively higher driving ability. Next, the driving ability is made different between two sense amplifiers SA1 and SA2 allocated with two pairs of bit lines as one unit, and control is executed so that the bit line coupled the memory cell to be selected corresponding to the selecting operation of the memory cell can be connected to the sense amplifier having higher driving ability. Thus, the peak current in the case of a sense amplifier operation can be reduced, and high-speed access can be performed at the point of a bit line amplifying operation due to the sense amplifier.

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