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1. 发明专利

JPH1021686A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH1021686A
公开(公告)日：1998-01-23
申请号：JP18889996
申请日：1996-06-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KATAYAMA MASAHIRO
IPC分类号： G11C11/409 , G11C11/401 , G11C11/407
摘要： PROBLEM TO BE SOLVED: To perform a high speed reading by transmitting the read-out signal held in a latch circuit in synchronization with the operation timing of a main amplifier after the second switch after the first switch was turned off. SOLUTION: The latch circuit is provided between complementary data lines CDL and/CDL and the grounding potential of the circuit, and comprises capacitors C1 and C3, and capacitor C3, which is provided between the lines CDL and/CDL. The capacitors C1 and C2 comprise the synthetic capacitor of the MOS capacity utilizing a MOSFET and parasitic capacity. Switches MOSFET Q8 and Q9 are provided between a common I/O bus and the input terminal of a main amplifier. A timing signal Φ2 is applied on the gates of Q8 and Q9. Thus, the signal transfer from the main amplifier to a data output buffer can be performed at a high speed. Therefore, in a syhchronous DRAM, wherein the latched circuit is provided at this part, the division of the stage in a bump line can be performed adequately.

2. 发明专利

JPH0845269A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH0845269A
公开(公告)日：1996-02-16
申请号：JP19489394
申请日：1994-07-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MATSUMOTO YOSHINORI , OOISHI TSURATOKI , KATAYAMA MASAHIRO , WATANABE KAZUFUMI
IPC分类号： G11C11/401 , G06F12/00 , G06F12/02 , G09G5/393 , G11C7/10 , G11C8/00 , G11C11/407
摘要： PURPOSE:To perform various data processing at high speed by writing a result of logical operation for input data and data read out from a memory array in a memory array and outputting it. CONSTITUTION:Input data inputted from an I/O is held in a register 9B through a buffer 7. A signal read out from a memory array 6 through an input/output bus 5 is amplified by a main amplifier 8A, and held in a register 9A. Multiplication is performed with the input signal of the register 9B and a signal read out from a memory of the register 9A by an operation circuit 9. The operation result is written in the memory array 6 through a multiplexer 10A, a write buffer 10B and the I/O bus 5, while outputted from the I/O through a multiplexer 8B and an output buffer 8C.

3. 发明专利

JPH07141870A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH07141870A
公开(公告)日：1995-06-02
申请号：JP31446393
申请日：1993-11-19
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MATSUMOTO YOSHINORI , KATAYAMA MASAHIRO
IPC分类号： G11C11/407 , G11C11/401 , G11C11/408 , G11C16/06 , G11C17/00 , G11C29/00 , G11C29/04
摘要： PURPOSE:To increase operational speed with simple constitution by latching a signal with an output of a decoding circuit to which an output signal of an input buffer taking in plural input signals synchronizing with a clock signal is supplied as it is and a required internal clock. CONSTITUTION:A row address strobe signal/RAS of an external input signal, a column address strobe signal/CAS, a write enable signal/RE, and a chip selector signal/CS are respectively supplied to corresponding input buffers 3-6, and output of the buffers is directly supplied to a mode decoder 7. And an output of the circuit 7 is latched by a latch circuit 8 which is activated by an internal clock ICLK synchronizing with a clock signal CLK. By using this constitution in which an input signal is taken in and decoded by making use of a setup time and a holding time for a clock signal of this input signal, decode deciding timing is made quick, then a semiconductor memory in which a circuit is simple and operational speed is increased is obtained.

4. 发明专利

JPH08102184A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS SCREENING METHOD 失效
公开(公告)号：JPH08102184A
公开(公告)日：1996-04-16
申请号：JP23626394
申请日：1994-09-30
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KATAYAMA MASAHIRO , WADA SHOJI
IPC分类号： G11C11/401 , G11C29/00 , G11C29/34
摘要： PURPOSE: To efficiently and surely perform the screening in a short time by performing contraction in the direction of I/O in the screening of a semiconductor integrated circuit device. CONSTITUTION: Comparison circuits 2-5 of Exclusive NOR are connected respectively to the poststage of a main amplifier of a memory circuit performing the screening, and the comparison results of the comparison circuits 2-5 are inputted to the comparison circuit 6 of AND, and the output of the comparison circuit 6 is outputted to a prescribed I/O port. When no fault exists in the memory circuit, the output of the comparison circuit 6 becomes a Hi signal output, and when the fault occurs, it becomes a Lo signal output.

5. 发明专利

JPH0816486A LSI FOR DEFECT REMEDY AND MEMORY DEVICE 失效
公开(公告)号：JPH0816486A
公开(公告)日：1996-01-19
申请号：JP17020794
申请日：1994-06-29
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： WADA SHOJI , KEMIZAKI KANEHIDE , MURANAKA MASAYA , OGATA SHINKO , AOYANAGI HIDEAKI , KITAME TETSUYA , KATAYAMA MASAHIRO , KUBONO SHIYOUJI , SUZUKI YUKIE , MORINO MAKOTO , MIYATAKE SHINICHI , HARUFUJI SEIICHI , KOYAMA YOSHIHISA , ONO NOBUHIKO
IPC分类号： G06F12/16 , G11C29/00 , G11C29/02 , G11C29/44 , H01L21/82
摘要： PURPOSE:To provide an LSI which can remedy a defect of a mounted DRAM and to provide a memory device which can remedy the defect of the DRAM generated after assembly. CONSTITUTION:The LSI for defect remedy consists of an interface part for the same address and control with DRAMs, an input/output interface corresponding to the memory device consisting of plural DRAMs, a nonvolatile storage circuit 3 which stores the chip addresses of the DRAMs and a defect address of an X system, a RAM part 4 for redundancy remedy consisting of an SRAM which has a word line selected with a comparison matching signal between an inputted X address and the defect address of the storage circuit and a column selected with a Y address signal, a selection part 6 which connects the data input/output bus of the RAM part for redundancy to a data input/output terminal, a data input/output part 7 which activates an input/output circuit corresponding to the selection, and a mask part 8 which outputs a signal for placing the output terminal of a DRAM judged to be defective in a high-impedance state.

6. 发明专利

JPH06139773A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH06139773A
公开(公告)日：1994-05-20
申请号：JP29098792
申请日：1992-10-29
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KATAYAMA MASAHIRO , MANITA KIICHI
IPC分类号： G11C11/408 , G11C11/401 , G11C11/407
摘要： PURPOSE:To stabilize the base plate potential and to reduce a power consumption by constituting a semiconductor integrated circuit of a random.access.memory which is made up with dynamic memories and serial.access.memories. CONSTITUTION:A standby mode base plate potential generating circuit 6a and a random access section operation base plate potential generating circuit 6b are made up 4 an oscillation circuit OSC and a charge pump CP. Moreover, a serial access section operation base plate potential generating circuit 6c is constituted of a charge pump only and the circuit 6c is externally supplied with serial clocks SC through a SAM control circuit 4. Thus, when clocks SC stop, the circuit 6c automatically stops and no base plate potential is generated. The circuit 6a is always operated, the circuit 6b is validated when a random access section 1 is operated and during all operation modes and the circuit 6c is validated when a serial access section 2 is operated and during all operation modes.

7. 发明专利

JP2002230999A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND TEST METHOD THEREFOR, AND MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2002230999A
公开(公告)日：2002-08-16
申请号：JP2001025227
申请日：2001-02-01
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： HASEGAWA MASATOSHI , MIYAOKA SHUICHI , AKASAKI HIROSHI , KATAYAMA MASAHIRO
IPC分类号： G01R31/28 , G01R31/3185 , G11C11/401 , G11C29/12 , G11C29/14 , G11C29/48 , G11C29/50 , G11C29/56 , G11C29/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device and a test method therefor in which a high speed operation test can be performed with a simple constitution and high reliability, and a manufacturing method for the semiconductor integrated circuit device in which an improved selection yield is realized with a simple constitution. SOLUTION: The input of a control circuit is coupled to a terminal to which an external operation control signal is supplied and a terminal to which a timing signal for test only, the internal operation control signal is changed from a first control state to a second control state responding to change from a first state to a second state of the external operation control signal at the time of a test mode, also the internal operation control signal is changed to the first control state responding to the timing for test only, the internal operation control signal is changed from a first control state to a second control state responding to change from a first state to a second state of the external operation control signal at the time of a normal operation mode, also, the internal operation control signal is changed to the first control state responding to change to the first state of the external operation control signal.

8. 发明专利

JP2001143500A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001143500A
公开(公告)日：2001-05-25
申请号：JP32633399
申请日：1999-11-17
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KATAYAMA MASAHIRO , MIYAOKA SHUICHI , YOKOYAMA YUJI , NAKAYAMA MICHIAKI
IPC分类号： G01R31/28 , G11C11/401 , G11C29/00 , G11C29/02 , G11C29/06
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device for which a burn-in time can be shortened by performing burn-in of a logic circuit and burn-in of a DRAM- macro in a logic mix memory of a logic circuit and a DRAM-macro. SOLUTION: This device is a logic mix DRAM, and constituted of a logic circuit 1, a DRAM-macro 2, a sequencer 3 for performing burn-in operation of the DRAM-macro 2, a counter 4, a selector 5 selecting the prescribed signal at the time of normal operation and burn-in operation, and the like, as signals for burn-in operation outputted from the sequencer 3 and the counter 4 and a burn-in signal are made a voltage level of 'L' and they can be selected by the selector 5, burn-in of the logic circuit 1 and the DRAM-macro 2 can be performed simultaneously, by inputting in parallel the burn-in pattern of the logic circuit 1 and inputting a burn-in pattern of the DRAM-macro 2.

9. 发明专利

JP2001101900A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2001101900A
公开(公告)日：2001-04-13
申请号：JP28094599
申请日：1999-10-01
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： YOKOYAMA YUJI , TANAKA YOSUKE , KATAYAMA MASAHIRO
IPC分类号： G11C11/401 , G01R31/28 , G11C29/00 , G11C29/02
摘要： PROBLEM TO BE SOLVED: To reduce the number of processes of a memory integrated circuit on which logics are mixedly loaded and the like incorporated in plural DRAM macro-cells DRAM0-DRAM7 without increasing the manufacturing cost and obstructing its high speed operation and to improve the accuracy of test. SOLUTION: An individual identification numbers are given to DRAM marco- cells DRAM0-DRAM7 incorporated in a memory integrated circuit loading logics mixedly and the like, while a DFT circuit of each DRAM marco-cell is provided with a function recognizing an identification number given to a corresponding DRAM marco-cell based on marco-cells identification signals TDID0-TDID2, and a function in which a row address strobe signal RASN and a column address strobe signal CASN being a start control signal are selectively taken in a marco-cell, keeping a marco-cell active signal TMATMT selectively to a valid level, or fixing it substantially to an invalid level.

10. 发明专利

JP2000299436A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000299436A
公开(公告)日：2000-10-24
申请号：JP10477499
申请日：1999-04-13
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： AKASAKI HIROSHI , YOKOYAMA YUJI , NAKAYAMA MICHIAKI , KATAYAMA MASAHIRO
IPC分类号： G11C11/401 , H01L21/822 , H01L27/04 , H01L27/10 , H03K17/22 , H03K19/0175
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device where a logic circuit and a storage circuit coexist, wherein in a power-on sequence, a gate control or internal node initialization is performed at a prestage of the storage circuit to prevent entrance of uncertain signal into the storage circuit. SOLUTION: A logic coexisting DRAM/LSI comprises a logic region 1, containing a logic circuit and a DRAM macro region 2 containing DRAM. The DRAM macro region 2 comprises an input latch circuit 21, which latches the output signal from an output latch circuit 12 of the logic region 1, a gate control circuit 22 comprising 2-input NOR gate, where that output signal is logically calculated with a reset signal for gate control, and then the output signal of fixed level is outputted, and a DRAM logic 23 which is controlled by a memory signal comprising the output signal, etc., and the input signal which is inputted in the DRAM logic 23 is set to a fixed level by the gate control circuit 22 during a power-source voltage step-up period at power on.

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