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1. 发明专利

JPH11204783A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREFOR 失效
公开(公告)号：JPH11204783A
公开(公告)日：1999-07-30
申请号：JP276098
申请日：1998-01-09
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ISHIDA HIROSHI , OYU SHIZUNORI , OOKI NAGATOSHI , SHIMIZU AKIHIRO , SHIBA TAKEO
IPC分类号： H01L29/78 , H01L21/265 , H01L21/322
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method in which increased speed diffusion or re-distribution of a punch through stopper layer formed for suppression of a short channel effect is reduced, and an inverted short channel effect is suppressed. SOLUTION: A region 17 where fluorine exists is provided at a region of a p-type conductive punch through stopper layer 16 formed in a p-type conductive silicone substrate 11. As fluorine is captured by excessive failure which is introduced in the silicone substrate when a high density source and a drain diffusion layer are formed, increased speed diffusion or re-distribution of a punch through stopper layer can be reduced, an inverted short channel effect is suppressed and a short channel effect is improved. Additionally a long term reliability represented by a hot carrier effect can be improved.

2. 发明专利

JPH0832054A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0832054A
公开(公告)日：1996-02-02
申请号：JP16349494
申请日：1994-07-15
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ISHIDA HIROSHI , SHIMIZU AKIHIRO , OOKI NAGATOSHI , YAMANAKA TOSHIAKI , NAGANO TAKAHIRO
IPC分类号： H01L29/78 , H01L21/336
摘要： PURPOSE:To provide a manufacturing method of semiconductor device having excellent threshold value controllability capable of counteracting the shortchannel effect as well as enhancing the reliability upon a gate oxide film. CONSTITUTION:After the formation of a gate oxide film 13 on an n conductivity type silicon substrate 11, an amorphous silicon film 14 is formed on this gate oxide film 13, successively, boron ions are implanted in a silicon substrate 11 through the gate oxide film l3 and the amorphous silicon film 14 to form a p conductivity type channel region 15 for threshold value adjustment. Next, after the formation of a polycrystalline film 16 on the amorphous silicon film 14, the needless part of these polycrystalline silicon film 16 and the amorphous silicon film 14 are removed and successively boron ions are implanted in the n conductivity type silicon substrate 11 using the remaining polycrystalline film 16 and the amorphous silicon material 15 as masks so that a p conductivity type source region 17 and a drain region 18 may be formed as if coming into contact with both ends of the p conductivity type channel region 15.

3. 发明专利

JPH0595113A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH0595113A
公开(公告)日：1993-04-16
申请号：JP25347191
申请日：1991-10-01
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIMIZU AKIHIRO , YAMANAKA TOSHIAKI , HASHIMOTO NAOTAKA , HASHIMOTO KOJI , OOKI NAGATOSHI , ISHIDA HIROSHI
IPC分类号： H01L29/78
摘要： PURPOSE:To provide a MIS-type field effect transistor having high reliability and high current driving ability and is proper for high integration. CONSTITUTION:A source and a drain have an LDD structure, a sidewall spacer 6 is provided to an area near the sidewall of a gate electrode above a low concentration diffusion layer 2 thereof, a gate electrode bottom part protrudes and a gate electrode protruding part is buried inside a semiconductor substrate 1 in a self-alignment manner. Thereby, it is possible to bury an overlapping part of the low concentration diffusion layer 2 and a gate electrode 5 inside the silicon substrate 1 in a self-alignment manner and to realize a semiconductor device having high reliability and high current driving ability through the plane occupied area of a transistor is small. Furthermore, contact between the transistor and an upper wiring layer can be formed in a self-alignment manner and a plane occupied area of the transistor can be further reduced.

4. 发明专利

JPH04320036A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH04320036A
公开(公告)日：1992-11-10
申请号：JP8654791
申请日：1991-04-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIMIZU AKIHIRO , YAMANAKA TOSHIAKI , JINRIKI HIROSHI , NAKADA MASAYUKI , HASHIMOTO NAOTAKA , HASHIMOTO KOJI
IPC分类号： H01L21/314 , H01L21/336 , H01L21/8242 , H01L21/8244 , H01L27/10 , H01L27/108 , H01L27/11 , H01L29/78 , H01L29/786
摘要： PURPOSE:To provide a semiconductor device having MISFETs suitable for high reliability and high current driving capacity. CONSTITUTION:A source/drain has an LDD structure provided with a high- dielectric side wall spacer 6 in a vicinity of the gate electrode side wall on top of a low-doped diffusion layer 2, and with another tunneling thin film insulating film 7 between the side wall spacer and the diffusion layer 2. A gate fringe field effect to the diffusion layer 2 is improved, and hot carrier deterioration special to the LDD structure is made hard to occur; therefore, improvement in reliability of field relaxation and improvement in current driving power can be realized simultaneously.

5. 发明专利

JPH03218667A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH03218667A
公开(公告)日：1991-09-26
申请号：JP28705990
申请日：1990-10-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ISHIBASHI KOICHIRO , SASAKI KATSURO , SHIMOHIGASHI KATSUHIRO , YAMANAKA TOSHIAKI , HASHIMOTO NAOTAKA , HASHIMOTO KOJI , SHIMIZU AKIHIRO
IPC分类号： G11C11/412 , G11C11/419 , H01L21/8244 , H01L27/11
摘要： PURPOSE:To decrease a memory cell in area and electric power consumption by a method wherein two drive MOSFETs and two transfer MOSFETs are specified in length and width of channel, and the current of an active load FET is set 1X10 A or above in intensity. CONSTITUTION:N channel drive MOSFETs 3 and 4 are set to be WDEFF and LDEFF respectively in effective length and width of channels, and N channel transfer MOSFETs 5 and 6 are set WTEFF and LTEFF respectively in effective length and width of channels. The memory cell ratio (WDEFF/LDEFF)/WTEFF/LTEFF is set smaller than 3. That is, when data is read out from a cell, as polysilicon TFTs 1 and 2 functioning as active loads through which an ON-current larger than 1X10 can be made to flow are used as memory cells, the memory cell ratio can be made smaller than 3 and the effective channel length WDEFF can be made small. By this setup, a memory cell be made small in occupying area.

6. 发明专利

JPH0374848A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0374848A
公开(公告)日：1991-03-29
申请号：JP21008289
申请日：1989-08-16
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIMIZU AKIHIRO , YAMANAKA TOSHIAKI , HASHIMOTO NAOTAKA , HASHIMOTO KOJI , ISHIBASHI KOICHIRO , SASAKI KATSURO , SHIMOHIGASHI KATSUHIRO , TAKEDA EIJI
IPC分类号： H01L29/78 , H01L21/336
摘要： PURPOSE:To obtain an MISFET having a source.drain with low diffusion area which can be used as a basic device after 0.3mum process by forming a high concentration impurity region of the same conductivity type as the substrate in the substrate surface under an element isolating region. CONSTITUTION:A first element isolating insulating film 3 is formed on a first channel stopper layer 2 on a silicon substrate 1. Then, after a gate oxide film 4, a gate electrode 5, a silicon oxide film 6 are formed, an impurity for an n-layer is implanted to form a side wall spacer 6. Next, a side wall spacer 22 of a silicon nitride film is formed, and after boron is implanted, a second element isolating oxide film 8 is formed. At that time, a high concentration impurity layer 7 due to the boron is formed under the film 8 to constitute a second channel stopper layer. Then, the spacer 22 is removed and an opening 23 for source.drain connection is formed by self-alignment. A 0.3mum level MISFET can easily be formed in accordance with this construction.

7. 发明专利

JPS62293643A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62293643A
公开(公告)日：1987-12-21
申请号：JP13594786
申请日：1986-06-13
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIMIZU AKIHIRO , KUME HITOSHI , OOKI NAGATOSHI
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/8234 , H01L27/06 , H01L29/78
摘要： PURPOSE:To reduce the area of a chip, by forming a part of interconnections in a substrate, and providing a conventional two-dimensional interconnection in three dimensions. CONSTITUTION:On a substrate 1, a high concentration diffused layer 2 is selectively formed with As. A low concentration epitaxial layer 3 is formed. An element isolating region is formed with SiO2 5. Then, a gate insulating film 6 and a gate electrode 7 are formed. Thereafter, source and drain diffused layers 8 are formed with As by a selt-aligning method. The interconnection layer in the substrate and the diffused layers 8 at the surface of the substrate are connected by using converged ion beam. Thus the interconnections are formed by the diffused layers 2, 8 and 9. Thereafter, a phosphorus silicide glass PSG film 10, which is an interlayrr insulating film, is formed. Then, contact holes are formed, and aluminum interconnections 11 are formed. Thus a part of the interconnections on the substrate can be omitted, and the area of a chip can be reduced.

8. 发明专利

JPS62274776A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62274776A
公开(公告)日：1987-11-28
申请号：JP11733986
申请日：1986-05-23
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIMIZU AKIHIRO , KUME HITOSHI , OOKI NAGATOSHI
IPC分类号： H01L27/08 , H01L27/092 , H01L29/78
摘要： PURPOSE:To ensure high-reliability operations even in submicron-rule regions by a method wherein all the sources and drains are composed of the same metal or the same metal/silicon compound and 0.4-0.7eV-high Schottky barriers are built of a metal and semiconductor or of a metal/silicon compound and semiconductor. CONSTITUTION:An oxide film 3 and N-type well 2 are formed on a silicon substrate 1 and, after the formation of a gate oxide film 4 and polycrystalline silicon film 5, a nitride film 9 is deposited. The three layers are selectively retain after a photoetching process, a gate electrode is built, the silicon substrate 1 is subjected to etching with the nitride film 9 on the gate electrode 5 and an isolating region film 3 on the silicon substrate 1 serving as mask, and then tungsten is deposited only on the silicon substrate 1. After the removal of the nitride film 9 from upon the gate electrode 5, a thermal oxide film 10 is formed and, after the deposition of a phosphosilicate glass film 7, a contact hole is provided and an aluminum electrode 8 is built. Though a source and drain are built of tungsten in this design, any will do as far as the height against electrons of a Schottky barrier is as high as 0.4-0.7eV.

9. 发明专利

JPS62274772A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS62274772A
公开(公告)日：1987-11-28
申请号：JP11733586
申请日：1986-05-23
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIMIZU AKIHIRO , TAKEDA EIJI , KUME HITOSHI , OOKI NAGATOSHI
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To remarkably enlarge capacity along the junction of a substrate and a region formed therein and to make a cell area smaller than in a twodimensional conventional design by a method wherein the region provided in the substrate is equipped with a type of conductivity different from that of the substrate and is of a three-dimensional structure. CONSTITUTION:On a P-type substrate 1, a P layer 14 is formed and richly implanted with arsenic for the formation of an N layer 3, after which a low- concentration P-type silicon layer 2 is epitaxially grown. Next, an element- insulating region 12 and gate electrode 5 are formed, and then an N layer (As) 6 is provided, formed self-alignedly. A process follows wherein an N layer 9 is formed to connect the N layer 6 on the substrate and the N layer 3 in the substrate, a phospho silicate glass (PSG) film 10 is provided as a protecting film, a contact hole is provided in the PSG layer 10, and then an aluminum wiring 11 is formed. The p layer 14 surrounds the N layer 3 in the substrate 1, for reduction in leak and increase in junction capacity, and for protection against alpha rays.

10. 发明专利

JPH06224392A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH06224392A
公开(公告)日：1994-08-12
申请号：JP978093
申请日：1993-01-25
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HASHIMOTO KOJI , MINE TOSHIYUKI , YAMANAKA TOSHIAKI , HASHIMOTO NAOTAKA , SHIMIZU AKIHIRO , OOKI NAGATOSHI , ISHIDA HIROSHI
IPC分类号： H01L27/11 , H01L21/8244 , H01L29/78 , H01L29/786 , H01L29/784
摘要： PURPOSE:To provide a semiconductor device by using a double-layer insulator of SiO2 and Si3N4 so as to solve such problems as the decrease in yield due to an increase in defect density or the adverse effects of threshold fluctuations on reliability. CONSTITUTION:A semiconductor device has a structure in which an electrode is provided on each side of an insulating laminate including an SiO2 film 105 and an Si3N4 film 104. When a positive voltage is applied to the electrode in contact with the SiO2 film 105, negative charge appears in the laminated insulator. Such a double-layer insulating laminate of SiO2 105 and Si3N4 104 is used to decrease the thickness of the gate oxide of polysilicon p-MOS transistors in memory cells. The insulating laminate is thinner than 15nm in terms of the thickness of oxide. The SiO2 105 is on the gate side while Si3N4 104 is on the channel side. The SiO2 105 is thicker than the Si3N4 104. The double-layer insulating laminate has a sufficient dielectric breakdown strength and a good aging breakdown characteristic.

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