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1. 发明专利

JPH06224392A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH06224392A
公开(公告)日：1994-08-12
申请号：JP978093
申请日：1993-01-25
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HASHIMOTO KOJI , MINE TOSHIYUKI , YAMANAKA TOSHIAKI , HASHIMOTO NAOTAKA , SHIMIZU AKIHIRO , OOKI NAGATOSHI , ISHIDA HIROSHI
IPC分类号： H01L27/11 , H01L21/8244 , H01L29/78 , H01L29/786 , H01L29/784
摘要： PURPOSE:To provide a semiconductor device by using a double-layer insulator of SiO2 and Si3N4 so as to solve such problems as the decrease in yield due to an increase in defect density or the adverse effects of threshold fluctuations on reliability. CONSTITUTION:A semiconductor device has a structure in which an electrode is provided on each side of an insulating laminate including an SiO2 film 105 and an Si3N4 film 104. When a positive voltage is applied to the electrode in contact with the SiO2 film 105, negative charge appears in the laminated insulator. Such a double-layer insulating laminate of SiO2 105 and Si3N4 104 is used to decrease the thickness of the gate oxide of polysilicon p-MOS transistors in memory cells. The insulating laminate is thinner than 15nm in terms of the thickness of oxide. The SiO2 105 is on the gate side while Si3N4 104 is on the channel side. The SiO2 105 is thicker than the Si3N4 104. The double-layer insulating laminate has a sufficient dielectric breakdown strength and a good aging breakdown characteristic.

2. 发明专利

JPH05136402A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH05136402A
公开(公告)日：1993-06-01
申请号：JP30022191
申请日：1991-11-15
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ISHIDA HIROSHI , SHIMIZU AKIHIRO , HASEGAWA NORIO , MORIMOTO TADAO , YAMANAKA TOSHIAKI , HASHIMOTO NAOTAKA , HASHIMOTO KOJI , OOKI NAGATOSHI
IPC分类号： H01L21/265 , H01L21/266 , H01L21/28 , H01L29/78
摘要： PURPOSE:To enable micromachining forming a second mask narrower than a first mask patterned by photolithography. CONSTITUTION:A silicon substrate 1 is spread with a gate oxide film 2, a polycrystalline silicon film 3, an oxide film 4, and a polycrystalline silicon film 5 serving as a second mask material up t about 50nm; and then, with lower layer and intermediate layer resist films 6,7 and formed into an upper layer resist film pattern 8 by lithography. Next, it is transferred onto the intermediate resist film 7 to form a pattern 7' and likewise a pattern 6', and the intermediate layer resist pattern 7' is removed: with the lower resist pattern 6' used as a mask to the polycrystalline film 5 is isotropically over-etched by dry-etching to form a polycrystalline silicon pattern 5' made narrower than the pattern 6'. The pattern 6' is removed and used as a mask etch the oxide film 4 anisotropically by dryetching, so that a microsize of 0.1mum or less can be controlled.

3. 发明专利

JPH04287345A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH04287345A
公开(公告)日：1992-10-12
申请号：JP5218891
申请日：1991-03-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HASHIMOTO NAOTAKA , YAMANAKA TOSHIAKI , HASHIMOTO KOJI , SHIMIZU AKIHIRO
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78
摘要： PURPOSE:To obtain a fine element isolation structure and its manufacturing method excellent in the high level of integration. CONSTITUTION:The lower part of an element isolation region is a high concentration impurity layer 2 having the same conductivity type as a semiconductor substrate. The bottom surface is in contact with the substrate 1. On the side surface, a selective epitaxial layer 5 turning to an element region is formed via a thin insulating film 3. On the upper surface, a nitride film 4 is formed via a thin oxide film. A high concentration impurity layer 6 having the same conductivity type as the substrate 1 is formed inside the element region and the element isolation region. According to this invention, by forming a nitride film on the upper surface of a field insulating film, the exfoliation of the field insulating film can be prevented when connection holes are opened. Since the effective element isolation length is not damaged, fine element isolation is realized. Further, by thinning the field insulating film, the electric potential distribution is restricted within a shallow region, and the potential on the element region end can be restrained from increasing, so that the leak current can be prevented.

4. 发明专利

JPH04162668A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH04162668A
公开(公告)日：1992-06-08
申请号：JP28705890
申请日：1990-10-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YAMANAKA TOSHIAKI , HASEGAWA NORIO , TANAKA TOSHIHIKO , HASHIMOTO KOJI , ISHIBASHI KOICHIRO , HASHIMOTO NAOTAKA , SHIMIZU AKIHIRO , SUGAWARA YASUHIRO , KURE TOKUO , IIJIMA SHINPEI , NISHIDA TAKASHI , TAKEDA EIJI
IPC分类号： G03F1/29 , G03F1/30 , G03F1/68 , H01L21/027 , H01L21/8244 , H01L27/11
摘要： PURPOSE:To enable wiring resistance to be reduced and a memory cell area to be reduced by placing a conductive film which fixes a source potential of a MOS transistor for drive at a reference potential on an upper part than the MOS transistor after covering an entire surface of the memory cell. CONSTITUTION:MOS transistors for driving an n channel T1 and T2 and MOS transistors T3 and T4 for transferring the n channel are formed within a p-type well 24 which is formed within an n-type silicon substrate 23. A connection hole 14c is opened on a high-concentration n-type impurities region 12c which becomes a common source of the MOS transistors T1 and T2. A second-layer conductive film 15c for fixing a source potential of all MOS transistors for drive within the memory cell is connected to the region 12c through the connection hole 14c, thus enabling a memory cell area to be reduced while reducing resistance of wiring resistor of the conductive film for fixing the source potential to the reference potential.

5. 发明专利

JPH08316339A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH08316339A
公开(公告)日：1996-11-29
申请号：JP13162596
申请日：1996-05-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YAMANAKA TOSHIAKI , HASHIMOTO NAOTAKA , HASHIMOTO KOJI , SHIMIZU AKIHIRO , ISHIBASHI KOICHIRO , SASAKI KATSURO , SHIMOHIGASHI KATSUHIRO , TAKEDA EIJI
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11
摘要： PURPOSE: To obtain a semiconductor memory in which a novel static random access memory cell having reduced occupation area is fabricated on a semiconductor substrate. CONSTITUTION: The word line in a memory cell comprises a pair of word lines 11a, 11d extending along a first direction on the major surface of a semiconductor substrate while being spaced apart from each other. The gate 11b, 11c of insulated gate FET T1, T2 for driving extends longitudinally along the first direction on the major surface of a semiconductor substrate between the word lines 11a, 11d and a pair of load elements, i.e., insulated gate FETs, are arranged above the gates of the transistors T1, T2. Since the gate of a transistor, i.e., a load element, is arranged on each transistor T1, T2, the occupation area of memory cell can be reduced significantly.

6. 发明专利

JPH05102294A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH05102294A
公开(公告)日：1993-04-23
申请号：JP26010191
申请日：1991-10-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OOKI NAGATOSHI , SHIMIZU AKIHIRO , HASHIMOTO NAOTAKA , YAMANAKA TOSHIAKI , HASHIMOTO KOJI , ISHIDA HIROSHI
IPC分类号： H01L21/76
摘要： PURPOSE:To restrain kinks from occurring in a semiconductor device by a method wherein a groove constant in width is formed adjacent to the boundary of an element isolating region so as to surround it, an insulating film is formed inside the groove, a conductive film is filled into the groove, and the conductive film is connected to a wiring electrode or a substrate to be fixed at a certain potential. CONSTITUTION:A groove is provided to the boundary between an element region and an element isolating region on a P-type silicon substrate 1. A silicon oxide film 5 as thick as 20mm or so is formed on the side wall of the groove through a thermal oxidation method or a chemical vapor growth method, and a polycrystalline silicon film 6 is buried in the groove. Furthermore, a thermal oxide film 3 is formed thereon adjacent to a field oxide film 2 on an element isolating region. An impurity layer of the same conductivity type with a semiconductor substrate is provided onto the base of the groove, and the polycrystalline silicon film 6 and the silicon substrate 1 are electrically connected together. Therefore, the polycrystalline silicon film 6 is fixed at the same potential with the silicon substrate 1. By this setup, kinks can be restrained from occurring.

7. 发明专利

JPH04364722A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04364722A
公开(公告)日：1992-12-17
申请号：JP13998391
申请日：1991-06-12
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HASHIMOTO NAOTAKA , YAMANAKA TOSHIAKI , HASHIMOTO KOJI , SHIMIZU AKIHIRO , OOKI NAGATOSHI , ISHIDA HIROSHI
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/768 , H01L29/78
摘要： PURPOSE:To provide a semiconductor device that is not affected by the deviation of holes to be connected to a doped region. CONSTITUTION:A titanium silicate film 8 is formed on a dope region 9. After connection holes are opened, nitrification is performed to deposit titanium nitride 11 on the titanium silicate film 8 in the connection holes, and silicon nitride film 12 on the remaining areas. If a field oxide layer 4 is scraped when the connection holes extending to the doped region 9 are opened, the silicon nitride film 12 helps prevent the effective isolation length from decreasing. Since the scraped part of the field oxide layer is not additionally covered with a doped region, junction characteristics will not deteriorate.

8. 发明专利

JPH03166735A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH03166735A
公开(公告)日：1991-07-18
申请号：JP30462089
申请日：1989-11-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIMIZU AKIHIRO , YAMANAKA TOSHIAKI , HASHIMOTO NAOTAKA , HASHIMOTO KOJI , JINRIKI HIROSHI , TAKEDA EIJI
IPC分类号： H01L29/78 , H01L21/336
摘要： PURPOSE:To form a MIS type field-effect transistor having high-current driving capacity and high reliability by employing LDD structure in at least one of a source or a drain and forming a spacer insulating film, which is composed of two kinds or more of insulators having a high dielectric constant, as a multilayer film near the sidewall of a gate electrode in the upper section of a low impurity-concentration diffusion layer. CONSTITUTION:High-concentration impurity regions 2 separate from a gate electrode 5 and low-concentration impurity regions 3 brought into contact with the high-concentration impurity regions 2 and extended just under the gate electrode 5 are provided at least one of the source and drain of a transistor. Two kinds or more of high dielectric-constant insulators 6, 7 exerting a field effect in the same extent as the lower section of the gate electrode 5 are formed onto the low-concentration impurity regions 3 in the vicinity of the sidewalls of the gate electrode in at least one parts of the low-concentration impurity regions 3 not located under the gate electrode 5. Accordingly, an electric field in an element is relaxed, and a MIS type field-effect transistor having the high- current driving capacity of high reliability can be acquired.

9. 发明专利

JPH02312271A SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH02312271A
公开(公告)日：1990-12-27
申请号：JP13264289
申请日：1989-05-29
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YAMANAKA TOSHIAKI , HASHIMOTO NAOTAKA , HASHIMOTO KOJI , SHIMIZU AKIHIRO , ISHIBASHI KOICHIRO , SASAKI KATSURO , SHIMOHIGASHI KATSUHIRO , TAKEDA EIJI
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11
摘要： PURPOSE:To lessen a semiconductor memory device in required area and to improve it in resistance to soft error by a method wherein the PN junction of the memory node of a flip-flop FF circuit is micronized in area in a self- aligned manner, a laminated capacitive element is added to the memory node, and the FF circuit is composed of a complementary inverter of laminated structure. CONSTITUTION:The area of the PN junction of a FF circuit is made smaller than those of channel sections 18c and 18d of insulated gate field effect transistors T1-T4, and a gate electrode 11b of the transistor T1 out of a pair of the insulated gate field effect transistors T1 and T2 and a drain region 18b of the other transistor T2 and a drain region 18a of the transistor T1 and a gate electrode 11c of the transistor T2 are electrically cross-connected through a first and a second conductive film, 16a and 16b. By this setup, a semiconductor memory device of this design can be lessened in required area, improved in resistance to soft error, and stabilized in operation of a memory cell.

10. 发明专利

JPH05198570A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH05198570A
公开(公告)日：1993-08-06
申请号：JP23680092
申请日：1992-09-04
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HASHIMOTO NAOTAKA , YAMANAKA TOSHIAKI , HASHIMOTO KOJI , SHIMIZU AKIHIRO , OOKI NAGATOSHI , ISHIDA HIROSHI
IPC分类号： H01L21/76 , H01L21/316
摘要： PURPOSE:To provide a semiconductor integrated circuit device which suppresses a kink current of a MOS transistor without deteriorating a connecting characteristic of a diffusion layer and which has a semiconductor element having a channel width which prevents lowering of a threshold value voltage. CONSTITUTION:This is such a semiconductor integrated circuit device that an angle at which a lower surface of an end of a field oxide film 2 in a peripheral element region is placed against the surface of a semiconductor substrate 1 is small as compared with that of a memory element region. The semiconductor integrated circuit device is an element having a narrow channel width, and it raises a substrate surface density or thickens a gate insulating film thickness.

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