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1. 发明专利

JPH11204783A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREFOR 失效
公开(公告)号：JPH11204783A
公开(公告)日：1999-07-30
申请号：JP276098
申请日：1998-01-09
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ISHIDA HIROSHI , OYU SHIZUNORI , OOKI NAGATOSHI , SHIMIZU AKIHIRO , SHIBA TAKEO
IPC分类号： H01L29/78 , H01L21/265 , H01L21/322
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method in which increased speed diffusion or re-distribution of a punch through stopper layer formed for suppression of a short channel effect is reduced, and an inverted short channel effect is suppressed. SOLUTION: A region 17 where fluorine exists is provided at a region of a p-type conductive punch through stopper layer 16 formed in a p-type conductive silicone substrate 11. As fluorine is captured by excessive failure which is introduced in the silicone substrate when a high density source and a drain diffusion layer are formed, increased speed diffusion or re-distribution of a punch through stopper layer can be reduced, an inverted short channel effect is suppressed and a short channel effect is improved. Additionally a long term reliability represented by a hot carrier effect can be improved.

2. 发明专利

JPH03228335A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH03228335A
公开(公告)日：1991-10-09
申请号：JP2200090
申请日：1990-02-02
申请人： HITACHI LTD , HITACHI DEVICE ENG , HITACHI VLSI ENG
发明人： SHIBA TAKEO , OGIWARA ITARU , TAMAOKI YOICHI , SHIMAMOTO HIROMI , KOBAYASHI TAKASHI , NANBA MITSUO
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L27/06 , H01L27/082 , H01L29/732
摘要： PURPOSE:To reduce the specific resistance and the parasitic resistance of a polycrystalline silicon electrode in a bipolar transistor by using polycrystalline silicon with a grain size above a specific value for the polycrystalline silicon electrode of base, emitter, or collector. CONSTITUTION:In a vertical bipolar transistor consisting of a conductivity-I first layer 2 provided in a semiconductor substrate 1, a conductivity-II second layer 7 provided on it, and a conductivity-I third layer 8 provided further on it, electrodes 5, 10 made of polycrystalline silicon film are connected to the first layer 2, second layer 7, or third layer 8, so that the largest side of its polycrystalline silicon grain is 1mum or larger. For example, amorphous silicon layers are deposited, injected with impurity atoms, and heat-treated at 900 deg.C or higher temperature, thus forming base electrodes 5 and emitter electrodes 10 consisting of polycrystalline silicon with a grain size of 2mu or larger. Thereafter, a passivation film 11 is deposited to form base, emitter, and collector metal electrodes 12, 14.

3. 发明专利

JPH0418733A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0418733A
公开(公告)日：1992-01-22
申请号：JP12110790
申请日：1990-05-14
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAMAOKI YOICHI , SHIBA TAKEO , SAGARA KAZUHIKO , KURE TOKUO , NAKAMURA TORU , OGIWARA ITARU
IPC分类号： H01L29/73 , H01L21/31 , H01L21/331 , H01L21/76 , H01L29/732
摘要： PURPOSE:To manufacture the title semiconductor device capable of flattening the upper part of trenches by a method wherein the insulation separating trenches are formed between elements on a substrate and after forming buried material on the whole surface and etching away the material previously formed around projection parts only, the buried material on the whole surface is further etched away. CONSTITUTION:An n type buried layer 2 for collector is formed on a P type substrate 1 to form an Si epitaxial growing layer 3 on the film 2 and then an SiO2 film 4, an Si3O4 film 5 and another SiO2 film 6 are successively formed. After halfway etching away the epitaxial growing layer 3 using the three layer film as a mask to form the SiO2 film by thermal process, another Si3N4 film 7 is deposited on the whole surface to be left only on the sidewall of projection parts by etching away process. Next, Si trenches 8 for element separation are formed further to form the other SiO2 film 9. After removing the Si3N4 film 7, the other Si3N4 film 10 is formed on the whole surface to form a polycrystal silicon film 11. Next, after the whole surface is coated with a photoresist film 13 so as to be flattened, the film 13 is removed until the projection part of the film 11 is exposed and furthermore after removing the film 13, the film 11 is etched away until the surface of the trenches 8 is exposed.

4. 发明专利

DE3277663D1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES COMPRISING ISOLATING REGIONS 未知
公开(公告)号：DE3277663D1
公开(公告)日：1987-12-17
申请号：DE3277663
申请日：1982-06-09
申请人： HITACHI LTD
发明人： TAMAKI YOICHI , KURE TOKUO , SHIBA TAKEO , HIGUCHI HISAYUKI
IPC分类号： H01L21/76 , H01L21/306 , H01L21/3105 , H01L21/3213 , H01L21/763 , H01L21/31
摘要： After filling isolation grooves (12) with a filling material (15), this filling material is etched by the use of a double-layer film (16, 17) which is made of substances different from each other.Side etching of the lower film (16) of the double-layer film and etching of the filling material (15) are alternately performed in such a manner that each etching is carried out two or more times. Thus, the upper surface of the filling material contained in each groove can be flattened, to improve the reliability of wiring formed over the upper surface.

5. 发明专利

DE3380378D1 SEMICONDUCTOR DEVICE COMPRISING DIELECTRIC ISOLATION REGIONS 未知
公开(公告)号：DE3380378D1
公开(公告)日：1989-09-14
申请号：DE3380378
申请日：1983-09-26
申请人： HITACHI LTD
发明人： TAMAKI YOICHI , SHIBA TAKEO , SAGARA KAZUHIKO , KAWAMURA MASAO
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/331 , H01L21/76 , H01L21/762 , H01L21/763 , H01L29/73
摘要： Devices formed in a semiconductor integrated circuit device are electrically isolated by a pair of narrow and deep grooves (9), thick oxide films (14) formed on the surfaces of the grooves and a thick oxide film (15) formed on a surface of an area between the grooves.

6. 发明专利

CA1179836A METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 未知
公开(公告)号：CA1179836A
公开(公告)日：1984-12-27
申请号：CA404150
申请日：1982-05-31
申请人： HITACHI LTD
发明人： TAMAKI YOICHI , KURE TOKUO , SHIBA TAKEO , HIGUCHI HISAYUKI
IPC分类号： H01L21/76 , H01L21/306 , H01L21/3105 , H01L21/3213 , H01L21/763 , H01L21/30
摘要： In the manufacture of a semiconductor device having grooves for isolating elements on the same substrate, after filling the grooves with a filling material, this material is etched using a double-layer film made of substances different from each other. Side etching of the lower film of this double-layer film and etching of the filling material are alternately performed, each etching being carried out a plurality of times. In this way the upper surface of the filling material contained in each groove can be flattened to an extent not possible with former methods.

7. 发明专利

JP2010114171A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2010114171A
公开(公告)日：2010-05-20
申请号：JP2008283861
申请日：2008-11-05
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SHIBA TAKEO , KAWASAKI MASAHIRO , FUJIMORI MASASHIGE
IPC分类号： H01L29/786 , H01L21/336 , H01L51/05 , H01L51/40
摘要： PROBLEM TO BE SOLVED: To provide a structure for improving yielding, while keeping the stable characteristic of a semiconductor device even when a gate electrode and a semiconductor layer are formed by a manufacturing method with lower accuracy compared with that of a source electrode and a drain electrode, so as to generate the position deviations. SOLUTION: Patterning is performed in the gate electrode, source electrode, drain electrode, and semiconductor layer of a TFT by a coating method, a drop method, and a print method. In this case, the comb-shape drain electrode is fitted to the comb-shape source electrode. Besides, the gate electrode and the semiconductor layer are arranged at interval from the comb back parts of the source electrode and the drain electrode. The gate electrode and the semiconductor layer are different in width in a comb shape extending direction (a channel width direction), and arranged to allow one to enclose the other, thereby raising a position deviation margin. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种用于提高屈服的结构，即使当通过与源极的精度相比制造方法形成栅电极和半导体层时，也能保持半导体器件的稳定特性和漏电极，以产生位置偏差。解决方案：通过涂布方法，滴涂法和印刷方法在TFT的栅电极，源电极，漏电极和半导体层中进行图案化。在这种情况下，梳状漏电极配合到梳状源电极。此外，栅电极和半导体层与源电极和漏电极的梳齿部间隔设置。栅电极和半导体层在梳形延伸方向（沟道宽度方向）上的宽度不同，并且被布置成允许一个包围另一个，从而提高位置偏差裕度。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2010093093A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010093093A
公开(公告)日：2010-04-22
申请号：JP2008262351
申请日：2008-10-09
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KAWASAKI MASAHIRO , FUJIMORI MASASHIGE , SHIBA TAKEO , ARAI TADASHI
IPC分类号： H01L21/336 , H01L21/28 , H01L21/368 , H01L29/417 , H01L29/786 , H01L51/05 , H01L51/40
摘要： PROBLEM TO BE SOLVED: To provide a thin-film transistor having high performance by finely forming a thin-film transistor by using coating technique and printing technique and further reducing photoconduction. SOLUTION: With respect to the thin-film transistor having respective members, such as a source-drain electrode, a gate insulating film, an organic semiconductor layer, and a gate electrode, laminated on an insulating substrate, and a display device, an IC tag device, and a sensor device including the transistor, the organic semiconductor layer is formed by a coating method or printing method, and at least a part (at least an end in a channel-length direction) in a nearly pattern plane shape of the organic semiconductor layer on the source-drain electrode is in a self-aligning shape overlapping with a pattern shape on the source-drain electrode. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：通过使用涂布技术和印刷技术，通过精细地形成薄膜晶体管并进一步降低光电导率来提供具有高性能的薄膜晶体管。解决方案：对于层叠在绝缘基板上的诸如源 - 漏电极，栅极绝缘膜，有机半导体层和栅电极的各个部件的薄膜晶体管和显示装置 IC标签装置，以及包含晶体管的传感器装置，通过涂布方法或印刷方法形成有机半导体层，并且在近似图形平面中至少形成有至少一部分（沟道长度方向的至少一端）源 - 漏电极上的有机半导体层的形状为与源极 - 漏极电极上的图案形状重叠的自对准形状。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2009164368A Organic thin film transistor, and manufacturing method thereof 有权
标题翻译：有机薄膜晶体管及其制造方法
公开(公告)号：JP2009164368A
公开(公告)日：2009-07-23
申请号：JP2008001024
申请日：2008-01-08
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HASHIZUME TOMIHIRO , ARAI TADASHI , SHIBA TAKEO , SUWA YUJI
IPC分类号： H01L29/786 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/08 , H01L27/092 , H01L29/417 , H01L51/05
摘要： PROBLEM TO BE SOLVED: To provide techniques for discriminating combinations of electrodes and organic semiconductors of organic TFTs which are improved in electron injection efficiency and hole injection efficiency, to actualize two kinds of TFTs which are n-channel TFTs and p-channel TFTs, and further to provide complementary organic thin film transistor (organic CTFT) and an organic CTFT array forming desired arbitrary circuit constitution with organic CTFTs.
SOLUTION: Only surface modifications of an electrode and an insulating film are selectively changed, without changing TFT materials, by using a mathematical expression values of differences in Fermi energy on a semiconductor-electrode interface and a semiconductor-gate insulator interface to actualize n-type and p-type TFTs. An arbitrary circuit is constituted by connecting all of source electrodes and gate electrodes of p-type channel TFTs and drain electrodes and gate electrodes of n-type channel TFTs, performing processes for the surface modifications, and then disconnecting unnecessary wiring by light irradiation etc.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供用于区分电子注入效率和空穴注入效率提高的有机TFT的电极和有机半导体的组合的技术，以实现作为n沟道TFT和p沟道的两种TFT TFT，并进一步提供互补的有机薄膜晶体管（有机CTFT）和有机CTFT阵列，形成有机CTFT所需的任意电路结构。解决方案：通过使用半导体 - 电极界面和半导体 - 栅极绝缘体界面上的费米能的差异的数学表达式来选择性地改变电极和绝缘膜的表面改性，而不改变TFT材料，以实现 n型和p型TFT。通过连接n型沟道TFT的p型沟道TFT和漏电极和栅电极的所有源电极和栅电极，进行表面改性的处理，然后通过光照射等将不必要的布线断开来构成任意电路。版权所有（C）2009，JPO＆INPIT

10. 发明专利

JP2004119919A Semiconductor thin film and method for manufacturing the same 审中-公开
公开(公告)号：JP2004119919A
公开(公告)日：2004-04-15
申请号：JP2002284735
申请日：2002-09-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TAKEDA KAZUO , GOTO JUN , SAITO MASAKAZU , OKURA OSAMU , SATO TAKESHI , FUKUDA HIROSHI , SHIBA TAKEO
IPC分类号： H01L21/20 , C30B13/00 , H01L21/336 , H01L29/786
CPC分类号： C30B29/06 , C30B13/00 , Y10S117/904
摘要： PROBLEM TO BE SOLVED: To form a silicon thin film, in which the poly-crystalline particle diameter is large in a laser annealing method.
SOLUTION: In a method of radiating pulse laser light to crystallize a semiconductor film on a sample substrate 1, a means for shaping the laser light into a line beam is provided, and a poly-crystalline film, grown in one constant direction, is collectively formed over an irradiation region of the line beam transmitting pulse laser intensity in a pattern of a vertical periodical phase shift stripe mask 2 in the long-axis direction. A crystal size is set to half the projection interval, a quarter of the period of the stripe pattern is one-time crystal growth, and the extreme value part of intensity distribution is the intensity, in which a minute crystal region does not remain. By this method, a sample can be multi-crystallized by irradiation scanning, and remarkable throughput improvement is realized. When conducting multi-shot overlap irradiation to manufacture the crystal reducing the height of a projection, lowering of throughput is suppressed by making compatible the positional control which displaces projection generation position and scanning direction, by angle regulation of the stripe and the scanning direction.
COPYRIGHT: (C)2004,JPO

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