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1. 发明专利

JPH04296041A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH04296041A
公开(公告)日：1992-10-20
申请号：JP6147591
申请日：1991-03-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO AKIRA , SAITO MASAYOSHI
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/768 , H01L23/522
摘要： PURPOSE:To make wirings superior in electro-migration resistance characteristics and to dissolve a disconnection between the wirings by a method wherein barrier metal films are respectively used for an upper wiring layer on each metal plug buried in through holes. CONSTITUTION:A high-melting point metal wiring film 1 is processed into a desired pattern as a first wiring layer and thereafter, a first interlayer insulating film is formed. A metal plug 3 is formed in a through hole on this first wiring layer. A three-layer film consisting of a barrier metal film 4, and Al film 5 and a high-melting point metal film 6 is formed on this plug 3 as a second wiring layer. Moreover, a metal plug 8 is formed in a through hole on the second wiring layer and a two-layer film consisting of a barrier metal film 9 and an Al film 10 is formed as a third wiring layer. Thereby, through-hole resistance are low, the wiring layers are superior in electron-migration resistance characteristics between the wiring layers and a disconnection between the wiring layers can be dissolved.

2. 发明专利

JPH06236874A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH06236874A
公开(公告)日：1994-08-23
申请号：JP2238593
申请日：1993-02-10
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SAITO MASAYOSHI , SAKAMA ISAO , TAKAHASHI TOSHIKAZU , MURAI FUMIO
IPC分类号： H01L21/3205 , H01L21/3213
摘要： PURPOSE:To provide a method of manufacturing a semiconductor device of multilayer wiring structure, wherein a semiconductor device high in reliability can be manufactured, and an integrated circuit is kept high in productive efficiency. CONSTITUTION:A conductor 5 is filled into an interlayer connection hole through a selective CVD method, a mask 7 is formed on the interlayer connection hole so as to prevent the conductor 5 from being removed off, and conductors 6 abnormally grown on an interlayer insulating film 4 are removed by etching. Thereafter, an upper wiring is formed.

3. 发明专利

JPH032370A FORMATION OF THIN FILM AND THIN FILM FORMING DEVICE 失效
公开(公告)号：JPH032370A
公开(公告)日：1991-01-08
申请号：JP13603589
申请日：1989-05-31
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO AKIRA , TERADA TOMOYUKI , SASAKI EIJI , TAKAHASHI TOSHIKAZU , NISHIDA TAKASHI , SAITO MASAYOSHI , TSUNEKAWA SUKEYOSHI
IPC分类号： C23C14/34 , H01L21/285
摘要： PURPOSE:To lower the sputter etching speed in the bottom of via hole, etc., and to form a thin film without chipping the bottom by bringing sputter etching species into collision against a sample at an arbitrary angle and allowing the sputter etching to the sample from plural directions. CONSTITUTION:The sputter etching species 7 are attracted or thrusted away by the electric power or magnetic force impressed to an intermediate electrode 5 at the time when the above-mentioned species are made incident perpendicularly on the electrode 5 and pass the electrode as shown in the drawing. As a result, the progressing direction of the sputter etching species 7 is changed and is brought into collision against the sample 4 at the prescribed angle. The angle distribution at which the sputter etching species 7 collide against the sample 4 is adjusted by the intensity of the electric power or magnetic force impressed to the electrode 5 and the bias voltage impressed to the substrate electrode 2. The angle of the collision of the sputter etching species 7 against the sample 4 is accurately controlled in this way and the chipping in the step part of the sample, more particularly the bottom of the via hole, etc., is prevented and the good film covering shape is simultaneously obtd.

4. 发明专利

JPH05235172A 失效
公开(公告)号：JPH05235172A
公开(公告)日：1993-09-10
申请号：JP3316392
申请日：1992-02-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO AKIRA , KONO MASAKAZU , SAITO MASAYOSHI
IPC分类号： H01L21/768 , H01L21/90
摘要： PURPOSE:To avoid the disconnection between wiring layers by enhancing the characteristics of lower wiring layers such as low wiring resistance and stress migration resistance within a semiconductor device having multilayered wiring structure. CONSTITUTION:Trenches are made in an interlayer insulating film 1 and then metallic films are formed in these trenches only so as to form the first wiring layers 2, 3, 4. Next, the second wiring layer 5 is formed without forming the second interlayer insulating film 6 so that the first wiring layers 2, 3, 4 may be electrically connected to the second wiring layer 5.

5. 发明专利

JPH01307220A MANUFACTURE OF FINE WIRING 失效
公开(公告)号：JPH01307220A
公开(公告)日：1989-12-12
申请号：JP13757388
申请日：1988-06-06
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SAITO MASAYOSHI , NISHIDA TAKASHI , SUZUKI MASAYASU , KOBAYASHI NOBUYOSHI , TAKAHASHI TOSHIKAZU
IPC分类号： H01L21/285 , H01L21/28
摘要： PURPOSE:To realize low contact resistance by eliminating a surface oxide film on the surface of an Si diffusion layer, by using diluted hydrofluoric acid system cleaning fluid, and forming a laminated layer film of high melting point metal or its nitride, in a high vacuum vessel. CONSTITUTION:The surface of an Si diffusion layer formed by contacting metal wiring is treated by using diluted hydrofluoric acid system cleaning fluid, so as to eliminate a surface oxide film. Then, by sputtering method, a laminated layer film of high melting point metal or nitride of high melting point metal, and high melting point metal is formed, in a high vacuum vessel. As a result, the segregation of oxide can be restrained at a very low level, on the interface between the high melting point metal or the nitride of high melting point metal and Si. As to fluorine, the segregation can be prevented in principle. Thereby, the high melting point metal can be buried in a contact hole of submicron order, and further, low contact resistance can be realized.

6. 发明专利

JPH04196316A FORMATION OF THIN FILM, MANUFACTURE OF SEMICONDUCTOR DEVICE AND THIN FILM FORMING APPARATUS 失效
公开(公告)号：JPH04196316A
公开(公告)日：1992-07-16
申请号：JP32316990
申请日：1990-11-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO AKIRA , SAITO MASAYOSHI
IPC分类号： H01L21/285 , H01L21/28
摘要： PURPOSE:To contrive improvement in reliability of a wiring by a method wherein the formation of a thin film by a CVD method and the additive doping by a sputtering method are conducted simultaneously or alternately in the same vacuum chamber. CONSTITUTION:When a thin film is formed on an Si substrate 142 by a CVD method and an additive doping operation is conducted using a sputtering method simultaneously or alternately, a sputtering additive matter 144 can be mixed uniformly into the CVD film 143 during the period starting from the initial stage to the final stage of formation of the thin film. Also, when the thin film formation on a substrate 145 by CVD method and the doping of additive matter by sputtering method are conducted alternately, a sputtering additive matter 147 is formed making a row in a CVD film 146. When the above-mentioned laminated thin film is heat-treated, the sputtered additive matter 147 is thermally diffused in the CVD film 146, and it is dispersed almost uniformly. As a result, electromigration-resisting characteristics, stress-migration resisting characteristics and the reliability of wiring can be improved.

7. 发明专利

JPH03285331A FORMATION OF THIN FILM AND MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03285331A
公开(公告)日：1991-12-16
申请号：JP8489590
申请日：1990-04-02
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO AKIRA , SAITO MASAYOSHI
IPC分类号： C23C14/06 , C23C16/02 , C23C16/06 , H01L21/285 , H01L21/3205
摘要： PURPOSE:To fill completely a hole with a metal film and to form a thin film into one, which is never peeled by a stress and is superior in adhesion, by a method wherein the thin film, which is substituted for the metal film, is formed on a wiring metal film by a CVD method. CONSTITUTION:A thin film 3 for substitution use is deposited on a wiring metal film 2 formed on an Si substrate 1. Moreover, the films 3 and 2 are simultaneously etched using a photoresist as a mask. Then, an insulating film 5 is formed, the film 5 is etched using a photoresist as a mask and a via hole 6 is formed. Then, a W film 7 is formed by a selective CVD method. Thereby, the film 3 formed on the film 2 is substituted for the film 7, the film 7 is formed into an inverted T-shaped form by an action of encroachment and a peeling of the film 7 from the film 5 due to a stress can be dissolved. Moreover, as a base material to have most an effect on the selective CVD method is always the film 3, the thin film 3 can be always formed on the same condition even if the film 2 which is a base of the film 3 is any wiring material.

8. 发明专利

JPH0324725A THIN FILM FORMING METHOD, AND METHOD AND DEVICE FOR MANUFACTURE OF SEMICONDUCTOR 失效
公开(公告)号：JPH0324725A
公开(公告)日：1991-02-01
申请号：JP15818989
申请日：1989-06-22
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO AKIRA , SHIMIZU AKIHIRO , TERADA TOMOYUKI , SAITO MASAYOSHI
IPC分类号： C23C16/04 , C23C16/06 , H01L21/285 , H01L21/3205
摘要： PURPOSE:To enable excellent metal burying by ionizing reaction species gas of metal to be buried, and applying a voltage of electric potential lower than the cationized reaction species gas to a substrate electrode. CONSTITUTION:Reaction species gas 3 is selectively introduced in the vicinity of a sample from a mixed system of plasma and ionized reaction species gas; a voltage of electric potential lower than the reaction species gas 3 is applied to the sample, thereby performing chemical vapor growth; thus a metal film is selectively formed in a hole 4. That is, when the hole 4 is kept at an electric potential lower than the cationized reaction species gas 3 by using power supplies 8, 9, 9', the reaction species gas 3 is attracted by the electric potential of the bottom of the hole 4, and selectively fly into the hole 4, so that the deposition of reaction product only in the hole 4 is progressed. Thereby the reaction product is highly selectively buried without depending on the base material of the sample or the surface condition, and a thin film can be formed.

9. 发明专利

JPH02199826A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02199826A
公开(公告)日：1990-08-08
申请号：JP1765289
申请日：1989-01-30
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SAITO MASAYOSHI , NISHIDA TAKASHI , TAKAHASHI TOSHIKAZU
IPC分类号： H01L23/522 , H01L21/28 , H01L21/768
摘要： PURPOSE:To enhance a heat-resistant by a method wherein, after a nitride of a high-melting- point metal has been formed, a first heat treatment at a comparatively low temperature of a specific temperature or lower is executed before a high-temperature heat treatment at a specific temperature or higher is executed in order to improve a film quality of the nitride of the high-melting-point metal. CONSTITUTION:A p-type silicon substrate 1 in which phosphorus ions have been implanted into a desired region and which has been heat-treated in an atmosphere of N2 is prepared; SiO2 is formed by a vapor growth method; in succession, an insulating film 3 on which phisphosilicate glass containing P2Q5 has been piled is formed. Then, this assembly is heat- treated in the atmosphere of N2; after that, a pattern of a photoresist is formed; a window is opened by making use of this pattern as a mask by a dry etching method. The surface is treated with a diluted-HF-based aqueous solution; after that, a TiN film 4 is vapor-deposited by a DC sputtering method; W is vapor-deposited on it. The laminated W/TiN layers 4, 5 are processed by making use of the photoresist as a mask by a dry etching method; after that, the photoresist is removed. Then, this specimen is heat-treated at 650 deg.C for 30 minutes, and, after that, is heat-treated at 700 deg.C for 30 minutes in the atmosphere of N2. Then, it is heat-treated at 900 deg.C for 30 minutes. Thereby, a reaction of a metal with Si during the high-temperature heat treatments is suppressed by the TiN film; a strain by a stress can be reduced.

10. 发明专利

DE102004003618A8 未知
公开(公告)号：DE102004003618A8
公开(公告)日：2006-08-10
申请号：DE102004003618
申请日：2004-01-16
申请人： ELPIDA MEMORY INC , HITACHI ULSI SYSTEMS CO , HITACHI LTD
发明人： KITAMURA EIJI , YAMADA SATORU , KATO YOSHIKI , SAINO KANTA , SAITO MASAYOSHI , IIJIMA SHINPEI , OYU KIYONORI
IPC分类号： H01L21/336 , H01L21/28 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78
摘要： Production of a semiconductor device comprises successively forming a gate insulating film, a polysilicon layer, a barrier film and a metal film on a semiconductor substrate, etching the metal film, the barrier film and polysilicon layer to form a gate electrode, nitriding the gate electrode at 700-950 [deg] C in an ammonia atmosphere, and selectively oxidizing to oxidize the polysilicon layer and silicon in the substrate without oxidizing the metal film. An independent claim is also included for a semiconductor device produced as described.

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